IDT7164S IDT7164L CMOS Static RAM 64K (8K x 8-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description High-speed address/chip select access time – Military: 20/25/35/45/55/70/85/100ns (max.) – Industrial: 20/25ns (max.) – Commercial: 20/25ns (max.) Low power consumption Battery backup operation – 2V data retention voltage (L Version only) Produced with advanced CMOS high-performance technology Inputs and outputs directly TTL-compatible Three-state outputs Available in 28-pin DIP, CERDIP and SOJ Military product compliant to MIL-STD-883, Class B The IDT7164 is a 65,536 bit high-speed static RAM organized as 8K x 8. It is fabricated using IDT’s high-performance, high-reliability CMOS technology. Address access times as fast as 20ns are available and the circuit offers a reduced power standby mode. When CS1 goes HIGH or CS2 goes LOW, the circuit will automatically go to, and remain in, a low-power stand by mode. The low-power (L) version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs of the IDT7164 are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ and a 28pin 600 mil CERDIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. Functional Block Diagram A0 VCC GND 65,536 BIT MEMORY ARRAY ADDRESS DECODER A12 7 0 I/O 0 I/O CONTROL I/O7 CS1 CS 2 OE CONTROL LOGIC 2967 drw 01 WE APRIL 2011 1 ©2011 Integrated Device Technology, Inc. DSC-2967/15 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Absolute Maximum Ratings(1) Pin Configurations NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 28 2 27 3 4 5 6 7 26 D28-1 D28-3 P28-2 SO28-5 8 25 24 23 22 21 20 9 10 12 19 18 17 13 16 14 15 11 Symbol VCC WE CS2 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 Rating (2) Com'l. Mil. Unit -0.5 to +7.0 -0.5 to +7.0 V VTERM Terminal Voltage with Respect to GND TA Operating Temperature 0 to +70 -55 to +125 o C TBIAS Temperature Under Bias -55 to +125 -65 to +135 o C TSTG Storage Temperature -55 to +125 -65 to +150 o C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 2967 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. , 2967 drw 02 DIP/SOJ Top View Truth Table(1,2,3) Pin Descriptions Name Description WE CS1 CS2 OE I/O Function A0 - A12 Address X H X X High-Z Deselected - Standby (ISB) I/O0 - I/O7 Data Input/Output X X L X High-Z Deselected - Standby (ISB) CS1 Chip Select X VHC X High-Z Deselected - Standby (ISB1) CS2 Chip Select VHC or VLC Write Enable X X VLC X High-Z Deselected - Standby (ISB1) WE H L H H High-Z Output Disabled OE Output Enable H L H L DATAOUT Read Data GND Ground L L H X DATAIN Write Data VCC Power Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VCC + 0.5 V 0.8 V VCC Supply Voltage GND Ground VIH Input HIGH Voltage 2.2 ____ VIL Input LOW Voltage -0.5(1) ____ NOTE: 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. 2967 tbl 03 NOTES: 1. CS2 will power-down CS1, but CS1 will not power-down CS2. 2. H = VIH, L = VIL, X = don't care. 3. VLC = 0.2V, VHC = VCC - 0.2V 2967 tbl 01 Recommended Operating Temperature and Supply Voltage Grade Temperature GND Vcc Military -55 C to +125 C 0V 5V ± 10% Industrial -40 C to +85 C 0V 5V ± 10% 0OC to +70OC 0V 5V ± 10% Commercial 2967 tbl 05 O O O O 2967 tbl 04 2 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 0V 8 pF CI/O I/O Capacitance VOUT = 0V 8 pF 2967 tbl 06 NOTE: 1. This parameter is determined by device characterization, but is not production tested. DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7164S20 7164L20 Symbol ICC1 ICC2 ISB ISB1 7164S25 7164L25 Power Com'l. Ind. Mi l . Com'l. Ind. Mi l . Unit Op e rating Po we r Sup p ly Curre nt CS1 = VIL, CS2 = VIH, Outp uts Op e n VCC = Max., f = 0(2) S 100 110 110 90 110 110 mA L 90 100 100 90 100 100 Dynamic Op e rating Curre nt CS1 = VIL, CS2 = VIH, Outp uts Op e n VCC = Max., f = fMAX(2) S 170 170 180 170 170 180 L 150 150 160 150 150 160 Stand b y Po we r Sup p ly Curre nt (TTL Le ve l), CS1 > VIH, CS2 < VIL, Outp uts Op e n, VCC = Max., f = fMAX(2) S 20 20 20 20 20 20 L 3 3 5 3 3 5 Full Stand b y Po we r Sup p ly Curre nt (CMOS Le ve l), f = 0(2), VCC = Max. 1. CS1 > VHC and CS2 > VHC, o r 2. CS2 < VLC S 15 15 20 15 15 20 L 0.2 0.2 1 0.2 0.2 1 Parameter mA mA mA 2967 tb l 07 Symbol ICC1 ICC2 ISB ISB1 7164S35 7164L35 7164S45 7164L45 7164S55 7164L55 7164S70 7164L70 7164S85/100 7164L85/100 Power Mi l . Mi l . Mi l . Mi l . Mi l . Unit Op e rating Po we r Sup p ly Curre nt CS1 = VIL, CS2 = VIH, Outp uts Op e n VCC = Max., f = 0(2) S 100 100 100 100 100 mA L 90 90 90 90 90 Dynamic Op e rating Curre nt CS1 = VIL, CS2 = VIH, Outp uts Op e n VCC = Max., f = fMAX(2) S 160 160 160 160 160 L 140 130 125 120 120 Stand b y Po we r Sup p ly Curre nt (TTL Le ve l), CS1 > VIH, CS2 < VIL, Outp uts Op e n, VCC = Max., f = fMAX(2) S 20 20 20 20 20 L 5 5 5 5 5 Full Stand b y Po we r Sup p ly Curre nt (CMOS Le ve l), f = 0(2), VCC = Max. 1. CS1 > VHC and CS2 > VHC, o r 2. CS2 < VLC S 20 20 20 20 20 L 1 1 1 1 1 Parameter mA mA mA 2967 tb l 08 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 6.42 3 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V ± 10%) IDT7164S Symbol Parameter Test Conditions IDT7164L Min. Max. Min. Max. Unit 10 5 ____ 5 2 µA 10 5 ____ 5 2 µA V |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC MIL. COM'L. & IND ____ |ILO| Output Leakage Current VCC = Max., CS1 = VIH, VOUT = GND to V CC MIL. COM'L. & IND ____ VOL Output Low Voltage IOL = 8mA, VCC = Min. ____ 0.4 ____ 0.4 IOL = 10mA, VCC = Min. ____ 0.5 ____ 0.5 IOH = -4mA, VCC = Min. 2.4 ____ 2.4 ____ VOH Output High Voltage ____ ____ ____ ____ V 2967 tbl 09 Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V) Max. VCC @ Typ.(1) VCC @ Symbol Parameter Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit 2.0 ____ ____ ____ ____ V ____ 10 10 15 15 200 60 300 90 μA 0 ____ ____ ____ ____ ns tRC(2) ____ ____ ____ ____ ns ____ ____ ____ 2 2 μA VDR VCC for Data Retention ____ ICCDR Data Retention Current MIL. COM'L. & IND tCDR(3) Chip Deselect to Data Retention Time tR(3) Operation Recovery Time IILII(3) Input Leakage Current 1. CS1 > VHC CS 2 > VHC, or 2. CS2 < VLC ____ 2967 tbl 10 NOTES: 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2967 tbl 11 5V 5V 480Ω 480Ω DATAOUT DATAOUT 255Ω 255Ω 30pF* 5pF* , , 2967 drw 04 2967 drw 03 Figure 2. AC Test Load (for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load *Includes scope and jig capacitances 4 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges) 7164S20 7164L20 Symbol Parameter 7164S25 7164L25 Min. Max. M i n. Max. Unit Read Cycle tRC Re ad Cycle Time 20 ____ 25 ____ ns tAA Ad d re ss Acce ss Time ____ 19 ____ 25 ns tACS1(1) Chip Se le ct-1 Acce ss Time ____ 20 ____ 25 ns tACS2(1) Chip Se le ct-2 Acce ss Time ____ 25 ____ 30 ns tCLZ1,2(2) Chip Se le ct-1, 2 to Outp ut in Lo w-Z 5 ____ 5 ____ ns tOE Outp ut Enab le to Outp ut Valid ____ 8 ____ 12 ns tOLZ(2) Outp ut Enab le to Outp ut in Lo w-Z 0 ____ 0 ____ ns tCHZ1,2(2) Chip Se le ct-1,2 to Outp ut in Hig h-Z ____ 9 ____ 13 ns tOHZ(2) Outp ut Disab le to Outp ut in Hig h-Z ____ 8 ____ 10 ns tOH Outp ut Ho ld fro m Ad d re ss Chang e 5 ____ 5 ____ ns tPU(2) Chip Se le ct to Po we r Up Time 0 ____ 0 ____ ns tPD(2) Chip De se le ct to Po we r Do wn Time ____ 20 ____ 25 ns Write Cycle tWC Write Cycle Time 20 ____ 25 ____ ns tCW1,2 Chip Se le ct to End -o f-Write 15 ____ 18 ____ ns tAW Ad d re ss Valid to End -o f-Write 15 ____ 18 ____ ns tAS Ad d re ss Se t-up Time 0 ____ 0 ____ ns tWP Write Pulse Wid th 15 ____ 21 ____ ns tWR1 Write Re co ve ry Time (CS1, WE) 0 ____ 0 ____ ns tWR2 Write Re co ve ry Time (CS2) 5 ____ 5 ____ ns tWHZ(2) Write Enab le to Outp ut in Hig h-Z ____ 8 ____ 10 ns tDW Data to Write Time Ove rlap 10 ____ 13 ____ ns tDH1 Data Ho ld fro m Write Time (CS1, WE) 0 ____ 0 ____ ns tDH2 Data Ho ld fro m Write Time (CS2) 5 ____ 5 ____ ns tOW(2) Outp ut Active fro m End -o f-Write 4 ____ 4 ____ ns NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested. 6.42 5 2967 tb l 12 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (con't.) (VCC = 5.0V ± 10%, Military Temperature Ranges) 7164S35 7164L35 Symbol Parameter 7164S45 7164L45 7164S55 7164L55 7164S70 7164L70 7164S85/100 7164L85/100 Unit Max. Min. M i n. Max. M i n. Max. Min. Max. Min. Max. Re ad Cycle Time 35 ____ 45 ____ 55 ____ 70 ____ 85/100 ____ ns tAA Ad d re ss Acce ss Time ____ 35 ____ 45 ____ 55 ____ 70 ____ 85/100 ns tACS1(1) Chip Se le ct-1 Acce ss Time ____ 35 ____ 45 ____ 55 ____ 70 ____ 85/100 ns tACS2(1) Chip Se le ct-2 Acce ss Time ____ 40 ____ 45 ____ 55 ____ 70 ____ 85/100 ns tCLZ1,2(2) Chip Se le ct-1, 2 to Outp ut in Lo w-Z 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ ns tOE Outp ut Enab le to Outp ut Valid ____ 18 ____ 25 ____ 30 ____ 35 ____ 40 ns 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns 35 ns Read Cycle tRC (2) tOLZ Outp ut Enab le to Outp ut in Lo w-Z tCHZ1,2(2) Chip Se le ct-1,2 to Outp ut in Hig h-Z ____ 15 ____ 20 ____ 25 ____ 30 ____ tOHZ(2) Outp ut Disab le to Outp ut in Hig h-Z ____ 15 ____ 20 ____ 25 ____ 30 ____ 35 ns 5 ____ 5 ____ 5 ____ 5 ____ ns tOH Outp ut Ho ld fro m Ad d re ss Chang e 5 ____ tPU(2) Chip Se le ct to Po we r Up Time 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(2) Chip De se le ct to Po we r Do wn Time ____ 35 ____ 45 ____ 55 ____ 70 ____ 85/100 ns Write Cycle tWC Write Cycle Time 35 ____ 45 ____ 55 ____ 70 ____ 85/100 ____ ns tCW1,2 Chip Se le ct to End -o f-Write 25 ____ 33 ____ 50 ____ 60 ____ 75 ____ ns 25 ____ 33 ____ 50 ____ 60 ____ 75 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns tAW Ad d re ss Valid to End -o f-Write tAS Ad d re ss Se t-up Time 0 ____ tWP Write Pulse Wid th 25 ____ 25 ____ 50 ____ 60 ____ 75 ____ ns tWR1 Write Re co ve ry Time (CS1, WE) 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ ns tWR2 Write Re co ve ry Time (CS2) tWHZ(2) Write Enab le to Outp ut in Hig h-Z ____ 14 ____ 18 ____ 25 ____ 30 ____ 35 ns tDW Data to Write Time Ove rlap 15 ____ 20 ____ 25 ____ 30 ____ 35 ____ ns tDH1 Data Ho ld fro m Write Time (CS1, WE) 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ 5 ____ ns 4 ____ 4 ____ 4 ____ 4 ____ tDH2 Data Ho ld fro m Write Time (CS2) 5 ____ tOW(2) Outp ut Active fro m End -o f-Write 4 ____ ns 2967 tb l 13 NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested. 6 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tOH tAA OE tOE tOLZ (5) CS2 tACS2 tCHZ2 (5) tCLZ2 (5) CS1 tOHZ (5) tCHZ1 (5) tACS1 tCLZ1(5) DATAOUT DATA VALID 2967 drw 05 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH tOH DATAOUT DATA VALID 2967 drw 06 Timing Waveform of Read Cycle No. 3(1,3,4) CS1 CS2 tACS2 tCLZ2 (5) tACS1 tCLZ1 (5) DATAOUT POWER SUPPLY CURRENT tCHZ2 tCHZ1 (5) (5) DATA VALID tPU ICC ISB NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 7 tPD 2967 drw 07 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,5) tWC ADDRESS CS2 CS1 tWR1(2) tAW tAS WE (3) tWP (5) tOW(6) DATAOUT tDH1,2 tDW tWHZ (6) DATAIN DATA VALID 2967 drw 08 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1) tWC ADDRESS tWR2(2) tAS CS2 tWR1(2) tCW CS1 (4) tAW WE tDW DATAIN tDH1,2 DATA VALID 2967 drw 09 NOTES: 1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2. 2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified tWP. 6. Transition is measured ±200mV from steady state. 8 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Low VCC Data Retention Waveform DATA RETENTION MODE VCC 4.5V 4.5V VDR ≥ 2V tCDR CS VIH tR VIH VDR 2967 drw 10 Ordering Information 7164 Device Type X XX Power Speed XXX Package X X X Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant with MIL-STD-883, Class B G Green Y TP D TD 20 25 35 45 55 70 85 100 S L 300 mil SOJ (SO28-5) 300 mil Plastic DIP (P28-2) 600 mil CERDIP (D28-1) 300 mil CERDIP (D28-3) Commercial/Industrial/Military Military Only Standard Power Low Power 2967 drw 11 6.42 9 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Datasheet Document History 01/13/00 Pp. 1, 2, 3, 5, 10 Pp. 1, 3, 9 Pp. 1, 3, 6, 10 Pg. 3 Pp. 5, 6 Pg. 8 Pp. 9, 10 Pg. 11 08/09/00 02/01/01 12/07/01 09/30/04 11/16/06 Pg. 10 Pg. 9,10 Pg.3 02/20/07 04/27/11 Pg.10 Pg. 9, 10 Pg. 1-3,5,6,9 Updated to new format Added Industrial Temperature range offerings Removed commercial 70ns speed grade offering Added 100ns speed grade specification details Revised notes and footnotes in DC Electrical tables Revised notes and footnotes in AC Electrical tables Removed Note 1 from Write Cycle No. 1 and No. 2 diagrams; renumbered notes and footnotes Separated Ordering Information into commercial, industrial, and military offerings Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Add PJ28 to Industrial temperature. Added "restricted hazardous substance device" to ordering information. Added inustrial temp power limits for 20ns part. Changed power limits for 25ns part for commercial and industrial. Changed power limits for commercial and industrial for 35ns part. Added 20ns part to ordering information. Refer to PCN SR-0602-01 Added L generation die step to data sheet ordering informatiom. Obsoleted 24-pin 600 mil, 15ns for Commercial and 35ns for Industrial & Commercial. Added Tape and Reel to Ordering information and updated description of Restricted hazardous substance device to Green. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 10 for Tech Support: [email protected] 800-345-7015