PIC18F2458/2553/4458/4553 Data Sheet

PIC18F2458/2553/4458/4553
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash, USB Microcontrollers
with 12-Bit A/D and nanoWatt Technology
© 2009 Microchip Technology Inc.
DS39887C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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Information contained in this publication regarding device
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rfPIC and UNI/O are registered trademarks of Microchip
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Solutions Company are registered trademarks of Microchip
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ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
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Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39887C-page 2
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
28/40/44-Pin High-Performance, Enhanced Flash, USB
Microcontrollers with 12-Bit A/D and nanoWatt Technology
Universal Serial Bus Features:
Flexible Oscillator Structure:
• USB V2.0 Compliant
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• 1-Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver with On-Chip Voltage
Regulator
• Interface for Off-Chip USB Transceiver
• Streaming Parallel Port (SPP) for USB Streaming
Transfers (40/44-pin devices only)
• Four Crystal modes, Including High-Precision PLL
for USB
• Two External Clock modes, up to 48 MHz
• Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz
to 8 MHz
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Power-Managed Modes:
Run: CPU On, Peripherals On
Idle: CPU Off, Peripherals On
Sleep: CPU Off, Peripherals Off
Idle mode Currents Down to 5.8 μA Typical
Sleep mode Currents Down to 0.1 μA Typical
Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V
Watchdog Timer: 2.1 μA Typical
Two-Speed Oscillator Start-up
Peripheral Highlights:
Special Microcontroller Features:
•
• C Compiler Optimized Architecture with Optional
Extended Instruction Set
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: > 40 Years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
• Programmable Code Protection
• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Optional Dedicated ICD/ICSP Port (44-pin TQFP
package only)
• Wide Operating Voltage Range (2.0V to 5.5V)
Device
•
•
•
•
High-Current Sink/Source: 25 mA/25 mA
Three External Interrupts
Four Timer modules (Timer0 to Timer3)
Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bits
Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Enhanced USART module:
- LIN bus support
Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C™
Master and Slave modes
12-Bit, up to 13-Channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time
Dual Analog Comparators with Input Multiplexing
Note:
This document is supplemented by
the “PIC18F2455/2550/4455/4550 Data
Sheet” (DS39632). See Section 1.0
“Device Overview”.
Program Memory
Data Memory
12-Bit CCP/ECCP
Flash # Single-Word SRAM EEPROM I/O A/D (ch)
(PWM)
(bytes) Instructions (bytes) (bytes)
PIC18F2458
24K
12288
PIC18F2553
32K
16384
PIC18F4458
24K
12288
PIC18F4553
32K
16384
© 2009 Microchip Technology Inc.
2048
SPI
Master
I2C™
Comp.
•
•
•
•
EUSART
•
•
•
•
•
•
•
•
Timers
8/16-Bit
Y
Y
1
2
1/3
MSSP
SPP
24
10
2/0
No
35
13
1/1
Yes
256
DS39887C-page 3
PIC18F2458/2553/4458/4553
Pin Diagrams
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18F2458
PIC18F2553
28-Pin SPDIP, SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
Note 1:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F4458
PIC18F4553
40-Pin PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RB3 is the alternate pin for CCP2 multiplexing.
DS39887C-page 4
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
1
2
3
4
5
6
7
8
9
10
11
PIC18F4458
PIC18F4553
33
32
31
30
29
28
27
26
25
24
23
NC/ICRST(2)/ICVPP(2)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
NC/ICCK(2)/ICPGC(2)
NC/ICDT(2)/ICPGD(2)
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
12
13
14
15
16
17
18
19
20
21
22
44-Pin TQFP
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
44-Pin QFN
PIC18F4458
PIC18F4553
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RB3/AN9/CCP2(1)/VPO
NC
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
VDD
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
Note
1:
2:
RB3 is the alternate pin for CCP2 multiplexing.
Special ICPORT features are available only in 44-pin TQFP packages. See Section 25.9 “Special ICPORT Features” in
the “PIC18F2455/2550/4455/4550 Data Sheet”’.
© 2009 Microchip Technology Inc.
DS39887C-page 5
PIC18F2458/2553/4458/4553
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 21
3.0 Special Features of the CPU ...................................................................................................................................................... 31
4.0 Electrical Characteristics ............................................................................................................................................................ 33
5.0 Packaging Information................................................................................................................................................................ 37
Appendix A: Revision History............................................................................................................................................................... 39
Appendix B: Device Differences........................................................................................................................................................... 39
Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 40
Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 40
Index .................................................................................................................................................................................................... 41
The Microchip Web Site ....................................................................................................................................................................... 43
Customer Change Notification Service ................................................................................................................................................ 43
Customer Support ................................................................................................................................................................................ 43
Reader Response ................................................................................................................................................................................ 44
Product Identification System............................................................................................................................................................... 45
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS39887C-page 6
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC18F2458
• PIC18F4458
• PIC18F2553
• PIC18F4553
Note:
This data sheet documents only the
devices’ features and specifications that are
in addition to the features and specifications of the PIC18F2455/2550/4455/4550
devices. For information on the features
and
specifications
shared
by
the PIC18F2458/2553/4458/4553
and
PIC18F2455/2550/4455/4550
devices,
see the “PIC18F2455/2550/4455/4550
Data Sheet” (DS39632).
The PIC18F4553 family of devices offers the advantages of all PIC18 microcontrollers – namely, high
computational performance at an economical price –
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for
many high-performance, power sensitive applications.
1.1
Special Features
• 12-Bit A/D Converter: The PIC18F4553 family
implements a 12-bit A/D Converter. The A/D
Converter incorporates programmable acquisition time. This allows for a channel to be selected
and a conversion to be initiated, without waiting
for a sampling period and thus, reducing code
overhead.
© 2009 Microchip Technology Inc.
1.2
Details on Individual Family
Members
The PIC18F2458/2553/4458/4553 devices are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in the
following ways:
1.
2.
3.
4.
5.
Flash program memory (24 Kbytes for
PIC18FX458
devices,
32 Kbytes
for
PIC18FX553).
A/D channels (10 for 28-pin devices, 13 for
40-pin and 44-pin devices).
I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40-pin and 44-pin devices).
CCP and Enhanced CCP implementation
(28-pin devices have two standard CCP
modules, 40-pin and 44-pin devices have one
standard CCP module and one ECCP module).
Streaming Parallel Port (present only on
40/44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Members of the PIC18F4553 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2458),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2458), function over an extended VDD range
of 2.0V to 5.5V.
DS39887C-page 7
PIC18F2458/2553/4458/4553
TABLE 1-1:
DEVICE FEATURES
Features
Operating Frequency
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
DC – 48 MHz
Program Memory (Bytes)
24576
32768
24576
32768
Program Memory
(Instructions)
12288
16384
12288
16384
Data Memory (Bytes)
2048
2048
2048
2048
Data EEPROM Memory
(Bytes)
256
256
256
256
Interrupt Sources
19
19
20
20
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, (E)
Ports A, B, C, D, E
Ports A, B, C, D, E
Timers
4
4
4
4
Capture/Compare/PWM
Modules
2
2
1
1
Enhanced Capture/
Compare/PWM Modules
0
0
1
1
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
1
1
1
1
Serial Communications
Universal Serial Bus (USB)
Module
Streaming Parallel Port (SPP)
12-Bit Analog-to-Digital
Converter Module
Comparators
No
No
Yes
Yes
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
2
2
2
2
Resets (and Delays)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
POR, BOR, WDT,
RESET Instruction,
Stack Full, Stack
Underflow, MCLR
(optional),
(PWRT, OST)
Programmable High/
Low-Voltage Detect
Yes
Yes
Yes
Yes
Programmable Brown-out
Reset
Yes
Yes
Yes
Yes
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
Packages
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
Corresponding Devices with
10-Bit A/D
PIC18F2455
PIC18F2550
PIC18F4455
PIC18F4550
Instruction Set
DS39887C-page 8
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
FIGURE 1-1:
PIC18F2458/2553 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
8
inc/dec logic
PORTA
Data Memory
(2 Kbytes)
PCLATU PCLATH
21
20
Address Latch
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
4
BSR
Address Latch
Program Memory
(24/32 Kbytes)
STKPTR
Data Latch
8
Instruction Bus <16>
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
Data Latch
8
4
Access
Bank
12
FSR0
FSR1
FSR2
12
PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
IR
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
3
(2)
Internal
Oscillator
Block
OSC1
OSC2(2)
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
MCLR(1)
VDD, VSS
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
W
8
8
8
8
ALU<8>
8
Brown-out
Reset
Fail-Safe
Clock Monitor
PORTE
Band Gap
Reference
MCLR/VPP/RE3(1)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
CCP2
MSSP
EUSART
ADC
12-Bit
Note 1:
2:
3:
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
8
BITOP
8
Watchdog
Timer
USB Voltage
Regulator
VUSB
PORTC
8 x 8 Multiply
USB
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
RB3 is the alternate pin for CCP2 multiplexing.
© 2009 Microchip Technology Inc.
DS39887C-page 9
PIC18F2458/2553/4458/4553
FIGURE 1-2:
PIC18F4458/4553(40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Memory
(2 Kbytes)
PCLATU PCLATH
21
20
Address Latch
PCU PCH PCL
Program Counter
12
Data Address<12>
31 Level Stack
4
BSR
Address Latch
Program Memory
(24/32 Kbytes)
STKPTR
Data Latch
8
Instruction Bus <16>
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
Data Latch
8
8
inc/dec logic
PORTA
12
FSR0
FSR1
FSR2
PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
Access
Bank
12
inc/dec
logic
Table Latch
PORTC
Address
Decode
ROM Latch
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
IR
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
3
VDD, VSS
(2)
OSC1
OSC2(2)
T1OSI
T1OSO
ICPGC(3)
Internal
Oscillator
Block
Power-up
Timer
INTRC
Oscillator
Oscillator
Start-up Timer
8 MHz
Oscillator
Power-on
Reset
Single-Supply
Programming
ICPGD(3)
In-Circuit
Debugger
ICPORTS(3)
MCLR(1)
8
BITOP
8
W
RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
8
8
8
8
ALU<8>
Watchdog
Timer
8
Brown-out
Reset
Fail-Safe
Clock Monitor
ICRST(3)
PORTD
8 x 8 Multiply
PORTE
Band Gap
Reference
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/VPP/RE3(1)
USB Voltage
Regulator
VUSB
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
ECCP1
CCP2
MSSP
EUSART
ADC
12-Bit
Note 1:
2:
3:
4:
USB
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
These pins are only available on 44-pin TQFP packages under certain conditions.
RB3 is the alternate pin for CCP2 multiplexing.
DS39887C-page 10
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS
Pin
Number
Pin
Type
Buffer
Type
I
ST
P
I
ST
I
I
Analog
Analog
O
—
CLKO
O
—
RA6
I/O
TTL
Pin Name
SPDIP,
SOIC
MCLR/VPP/RE3
MCLR
1
VPP
RE3
OSC1/CLKI
OSC1
CLKI
9
OSC2/CLKO/RA6
OSC2
10
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc.
DS39887C-page 11
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number
SPDIP,
SOIC
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
RA1/AN1
RA1
AN1
3
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV
6
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
RA6
—
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
I
ST
ST
—
TTL
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
—
—
See the OSC2/CLKO/RA6 pin.
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
DS39887C-page 12
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number
SPDIP,
SOIC
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
21
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
22
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
23
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
24
RB4/AN11/KBI0
RB4
AN11
KBI0
25
RB5/KBI1/PGM
RB5
KBI1
PGM
26
RB6/KBI2/PGC
RB6
KBI2
PGC
27
RB7/KBI3/PGD
RB7
KBI3
PGD
28
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C™ data I/O.
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I
O
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
I/O
I
I/O
O
TTL
Analog
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc.
DS39887C-page 13
PIC18F2458/2553/4458/4553
TABLE 1-2:
PIC18F2458/2553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number
SPDIP,
SOIC
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11
RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE
12
RC2/CCP1
RC2
CCP1
13
RC4/D-/VM
RC4
DVM
15
RC5/D+/VP
RC5
D+
VP
16
RC6/TX/CK
RC6
TX
CK
17
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18
RE3
—
VUSB
14
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
—
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
I
I/O
O
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
—
—
O
—
P
—
See MCLR/VPP/RE3 pin.
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is the
regulator output.
When the internal USB regulator is disabled, VUSB is the
power input for the USB transceiver.
VSS
8, 19
P
—
Ground reference for logic and I/O pins.
VDD
20
P
—
Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O = Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
DS39887C-page 14
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-3:
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS
Pin Name
MCLR/VPP/RE3
MCLR
Pin Number
Pin Buffer
PDIP QFN TQFP Type Type
1
18
18
I
ST
P
I
ST
I
I
Analog
Analog
O
—
CLKO
O
—
RA6
I/O
TTL
VPP
RE3
OSC1/CLKI
OSC1
CLKI
13
OSC2/CLKO/RA6
OSC2
14
32
33
30
31
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I
= Input
O
= Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc.
DS39887C-page 15
PIC18F2458/2553/4458/4553
TABLE 1-3:
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
RA1/AN1
RA1
AN1
3
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREFCVREF
4
RA3/AN3/VREF+
RA3
AN3
VREF+
5
RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV
6
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
RA6
—
19
20
21
22
23
24
—
19
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
I
ST
ST
—
TTL
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
—
—
See the OSC2/CLKO/RA6 pin.
20
21
22
23
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
24
—
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I
= Input
O
= Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39887C-page 16
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-3:
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
34
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
36
RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP
37
RB5/KBI1/PGM
RB5
KBI1
PGM
38
RB6/KBI2/PGC
RB6
KBI2
PGC
39
RB7/KBI3/PGD
RB7
KBI3
PGD
40
9
10
11
12
14
15
16
17
8
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I2C™ data I/O.
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I
O
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
I/O
I
I/O
O
TTL
Analog
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
I/O
I
I
O
TTL
Analog
TTL
—
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
9
10
11
14
15
16
17
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I
= Input
O
= Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc.
DS39887C-page 17
PIC18F2458/2553/4458/4553
TABLE 1-3:
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15
RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE
16
RC2/CCP1/P1A
RC2
CCP1
P1A
17
RC4/D-/VM
RC4
DVM
23
RC5/D+/VP
RC5
D+
VP
24
RC6/TX/CK
RC6
TX
CK
25
RC7/RX/DT/SDO
RC7
RX
DT
SDO
26
34
35
36
42
43
44
1
32
I/O
O
I
ST
—
ST
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
I/O
I/O
O
ST
ST
TTL
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 PWM output, channel A.
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
I
I/O
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
35
36
42
43
44
1
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I
= Input
O
= Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39887C-page 18
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). PORTD can be software
programmed for internal weak pull-ups on all inputs.
These pins have TTL input buffers when the SPP
module is enabled.
RD0/SPP0
RD0
SPP0
19
RD1/SPP1
RD1
SPP1
20
RD2/SPP2
RD2
SPP2
21
RD3/SPP3
RD3
SPP3
22
RD4/SPP4
RD4
SPP4
27
RD5/SPP5/P1B
RD5
SPP5
P1B
28
RD6/SPP6/P1C
RD6
SPP6
P1C
29
RD7/SPP7/P1D
RD7
SPP7
P1D
30
38
39
40
41
2
3
4
5
38
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel B.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel C.
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel D.
39
40
41
2
3
4
5
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I
= Input
O
= Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc.
DS39887C-page 19
PIC18F2458/2553/4458/4553
TABLE 1-3:
PIC18F4458/4553 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
8
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
9
RE2/AN7/OESPP
RE2
AN7
OESPP
10
27
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 5.
SPP clock 1 output.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
SPP clock 2 output.
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
SPP output enable output.
26
27
—
—
See MCLR/VPP/RE3 pin.
P
—
Ground reference for logic and I/O pins.
11, 32 7, 8, 7, 28
28, 29
P
—
Positive supply for logic and I/O pins.
O
—
P
—
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
ICSP programming clock.
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICSP programming data.
I
P
—
—
No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
Programming voltage input.
—
VSS
12,
31
VUSB
26
25
6, 30, 6, 29
31
RE3
VDD
25
18
—
37
—
37
Internal USB transceiver power supply.
When the internal USB regulator is enabled, VUSB is
the regulator output.
When the internal USB regulator is disabled, VUSB
is the power input for the USB transceiver.
NC/ICCK/ICPGC(3)
ICCK
ICPGC
—
NC/ICDT/ICPGD(3)
ICDT
ICPGD
—
NC/ICRST/ICVPP(3)
ICRST
ICVPP
—
NC/ICPORTS(3)
ICPORTS
—
—
34
P
—
No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.
NC
—
13
—
—
—
No Connect.
—
—
—
12
13
33
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I
= Input
O
= Output
P
= Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
DS39887C-page 20
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 40-pin
and 44-pin devices. This module allows conversion of an
analog input signal to a corresponding 12-bit digital
number.
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
The module has five registers:
•
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
bit 1
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0
ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
Note 1:
2:
x = Bit is unknown
These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return a floating input measurement.
© 2009 Microchip Technology Inc.
DS39887C-page 21
PIC18F2458/2553/4458/4553
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W(1)
R/W(1)
R/W(1)
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
PCFG3:
PCFG0
AN5(2)
AN4
AN3
AN2
AN1
AN0
PCFG3:PCFG0: A/D Port Configuration Control bits:
AN6(2)
bit 3-0
AN7(2)
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD
AN8
bit 4
AN9
VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
AN10
bit 5
AN11
Unimplemented: Read as ‘0’
AN12
bit 7-6
0000(1)
0001
0010
0011
0100
0101
0110
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A = Analog input
Note 1:
2:
x = Bit is unknown
D = Digital I/O
The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
AN5 through AN7 are available only on 40-pin and 44-pin devices.
DS39887C-page 22
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
© 2009 Microchip Technology Inc.
DS39887C-page 23
PIC18F2458/2553/4458/4553
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and the A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in Figure 2-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
FIGURE 2-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
1011
1010
1001
1000
0111
0110
0101
0100
12-Bit
A/D
Converter
VAIN
(Input Voltage)
0011
0010
0001
VCFG1:VCFG0
0000
VDD
Reference
Voltage
VREF+
X0
X1
1X
VREF-
0X
AN12
AN11
AN10
AN9
AN8
AN7(1)
AN6(1)
AN5(1)
AN4
AN3
AN2
AN1
AN0
VSS
Note 1:
Channels AN5 through AN7 are not available on 28-pin devices.
DS39887C-page 24
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
6.
7.
FIGURE 2-2:
The following steps should be followed to perform an A/D
conversion:
FIGURE 2-3:
FFEh
003h
002h
001h
4095 LSB
4095.5 LSB
4094 LSB
4094.5 LSB
3 LSB
2 LSB
000h
2.5 LSB
3.
4.
FFFh
0.5 LSB
2.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time (if required).
Start conversion:
• Set GO/DONE bit (ADCON0 register)
Digital Code Output
1.
A/D TRANSFER FUNCTION
1 LSB
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
5.
1.5 LSB
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets,
and is not affected by any other Reset.
Analog Input Voltage
ANALOG INPUT MODEL
VDD
Rs
VAIN
Sampling
Switch
VT = 0.6V
ANx
RIC ≤ 1k
CPIN
5 pF
VT = 0.6V
SS
RSS
CHOLD = 25 pF
ILEAKAGE
±100 nA
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Sampling Switch
SS
= Sample/Hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance
© 2009 Microchip Technology Inc.
VDD
6V
5V
4V
3V
2V
1
2 3
4
Sampling Switch (kΩ)
DS39887C-page 25
PIC18F2458/2553/4458/4553
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
the minimum acquisition time before starting a
conversion.
Note:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 4 kΩ
85°C (system max.)
ACQUISITION TIME
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=
TAMP + TC + TCOFF
EQUATION 2-2:
VHOLD
or
TC
Example 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
TACQ
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
A/D MINIMUM CHARGING TIME
=
(VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
TAMP
=
0.2 µs
TCOFF
=
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ
=
0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
DS39887C-page 26
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
2.2
Selecting and Configuring
Acquisition Time
2.3
Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provides a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
•
•
•
•
•
•
•
Manual
acquisition
is
selected
when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 2-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Assumes TAD Min. = 0.8 μs
A/D Clock Source (TAD)
Note 1:
2:
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
000
2.50 MHz
4 TOSC
100
5.00 MHz
8 TOSC
001
10.00 MHz
16 TOSC
101
20.00 MHz
32 TOSC
010
40.00 MHz
64 TOSC
RC(1)
110
48.00 MHz
x11
1.00 MHz(2)
The RC source has a typical TAD time of 2.5 μs.
For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
© 2009 Microchip Technology Inc.
DS39887C-page 27
PIC18F2458/2553/4458/4553
2.4
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After
entering the mode, an A/D acquisition or conversion
may be started. Once started, the device should
continue to be clocked by the same clock source until
the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If bits ACQT2:ACQT0 are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN bit
(OSCCON<7>) must have already been cleared prior
to starting the conversion.
DS39887C-page 28
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog conversion on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a digital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by controlling how the PCFG3:PCFG0 bits in
ADCON1 are reset.
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
2.6
A/D Conversions
After the A/D conversion is completed or aborted, a
2 TCY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are set to ‘010’, and selecting a
4 TAD acquisition time before the conversion starts.
2.7
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b11
b10
b9
b8
b7
b6
b3
b4
b5
b2
b1
b0
Conversion starts
Discharge
(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
FIGURE 2-5:
TAD Cycles
TACQT Cycles
1
2
3
4
1
Automatic
Acquisition
Time
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
© 2009 Microchip Technology Inc.
2
b11
3
b10
4
b9
5
b8
6
b7
7
b6
8
b5
9
b4
10
b3
11
b2
12
b1
13
b0
TAD1
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS39887C-page 29
PIC18F2458/2553/4458/4553
2.8
Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion, and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automatically
repeat the A/D acquisition period with minimal software
overhead (firmware must move ADRESH:ADRESL to
TABLE 2-2:
Name
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate TACQ
time selected before the Special Event Trigger sets the
GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
(4)
INTCON
GIE/GIEH PEIE/GIEL
PIR1
SPPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
(4)
PIE1
SPPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
(4)
IPR1
SPPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
(4)
PIR2
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
(4)
PIE2
OSCFIE
CMIE
USBIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
(4)
IPR2
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
(4)
ADRESH
A/D Result Register High Byte
(4)
ADRESL
A/D Result Register Low Byte
(4)
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
21
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
22
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
23
PORTA
—
RA6(2)
RA5
RA4
RA3
RA2
RA1
RA0
(4)
TRISA
—
PORTB
RB7
TRISA6(2) PORTA Data Direction Control Register
RB6
RB5
RB4
RB3
RB2
(4)
RB1
RB0
(4)
TRISB
PORTB Data Direction Control Register
(4)
LATB
PORTB Data Latch Register (Read and Write to Data Latch)
(4)
PORTE(1)
RDPU
—
—
—
RE3(3)
RE2(1)
RE1(1)
RE0(1)
(4)
TRISE
—
—
—
—
—
TRISE2
TRISE1
TRISE0
(4)
LATE(1)
—
—
—
—
—
(1)
PORTE Data Latch Register
(4)
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’.
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: For these Reset values, see the “PIC18F2455/2550/4455/4550 Data Sheet”.
DS39887C-page 30
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
3.0
SPECIAL FEATURES OF THE
CPU
Note:
3.1
For additional details on the Configuration
bits,
refer
to
the
“PIC18F2455/2550/4455/4550 Data Sheet”,
Section 25.1 “Configuration Bits”. Device
ID information presented in this section is for
PIC18F2458/2553/4458/4553 only.
Device ID Registers
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers, and can be read by firmware using
table reads.
PIC18F2458/2553/4458/4553 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These include:
• Device ID Registers
TABLE 3-1:
DEVICE IDs
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(1)
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
xxxx xxxx(1)
Legend:
Note 1:
x = unknown, u = unchanged
See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
File Name
© 2009 Microchip Technology Inc.
DS39887C-page 31
PIC18F2458/2553/4458/4553
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F2458/2553/4458/4553 DEVICES
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
bit 4-0
REV3:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F2458/2553/4458/4553 DEVICES
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
-n = Value when device is unprogrammed
bit 7-0
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
DEV10:DEV3: Device ID bits
DS39887C-page 32
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>)
Device
0010 1010
011
PIC18F2458
0010 1010
010
PIC18F2553
0010 1010
001
PIC18F4458
0010 1010
000
PIC18F4553
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
4.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP/
RE3 pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2009 Microchip Technology Inc.
DS39887C-page 33
PIC18F2458/2553/4458/4553
FIGURE 4-1:
PIC18F2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18F2458/2553/4458/4553
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
48 MHz
Frequency
FIGURE 4-2:
PIC18LF2458/2553/4458/4553 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
Voltage
5.0V
PIC18LF2458/2553/4458/4553
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
48 MHz
Frequency
For 2.0V ≤ VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz
For 4.2V ≤ VDD: FMAX = 48 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39887C-page 34
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
TABLE 4-1:
Param
No.
Sym
A/D CONVERTER CHARACTERISTICS: PIC18F2458/2553/4458/4553 (INDUSTRIAL)
PIC18LF2458/2553/4458/4553 (INDUSTRIAL)
Characteristic
A01
NR
Resolution
A03
EIL
Integral Linearity Error
A04
A06
A07
EDL
EOFF
EGN
Differential Linearity Error
Offset Error
Gain Error
A10
—
A20
ΔVREF Reference Voltage Range
(VREFH – VREFL)
Min
Typ
Max
Units
Conditions
—
—
12
bit
ΔVREF ≥ 3.0V
VDD = 3.0V ΔVREF ≥ 3.0V
—
±1
±2.0
LSB
—
—
±2.0
LSB
VDD = 5.0V
—
±1
+1.5/-1.0
LSB
VDD = 3.0V ΔVREF ≥ 3.0V
—
—
+1.5/-1.0
LSB
VDD = 5.0V
—
±1
±5
LSB
VDD = 3.0V ΔVREF ≥ 3.0V
—
—
±3
LSB
VDD = 5.0V
—
±1
±1.25
LSB
VDD = 3.0V ΔVREF ≥ 3.0V
—
—
±2.00
LSB
VDD = 5.0V
Monotonicity
Guaranteed(1)
—
VSS ≤ VAIN ≤ VREF
—
VDD – VSS
V
For 12-bit resolution
3
A21
VREFH Reference Voltage High
VSS + 3.0V
—
VDD + 0.3V
V
For 12-bit resolution
A22
VREFL Reference Voltage Low
VSS – 0.3V
—
VDD – 3.0V
V
For 12-bit resolution
A25
VAIN
Analog Input Voltage
VREFL
—
VREFH
V
A30
ZAIN
Recommended
Impedance of Analog
Voltage Source
—
—
2.5
kΩ
A50
IREF
VREF Input Current(2)
—
—
—
—
5
150
μA
μA
Note 1:
2:
During VAIN acquisition.
During A/D conversion
cycle.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
© 2009 Microchip Technology Inc.
DS39887C-page 35
PIC18F2458/2553/4458/4553
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
Q4
A/D CLK
130
(1)
132
11
A/D DATA
10
9
...
...
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
Param
Symbol
No.
130
TAD
A/D CONVERSION REQUIREMENTS
Characteristic
A/D Clock Period
Min
Max
Units
PIC18FXXXX
0.8
12.5(1)
μs
TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
1.4
25.0(1)
μs
VDD = 3.0V;
TOSC based, VREF full range
PIC18FXXXX
—
1
μs
A/D RC mode
VDD = 3.0V; A/D RC mode
—
3
μs
131
TCNV
Conversion Time
(not including acquisition time)(2)
13
14
TAD
132
TACQ
Acquisition Time(3)
1.4
—
μs
135
TSWC
Switching Time from Convert → Sample
—
(Note 4)
137
TDIS
Discharge Time
0.2
—
PIC18LFXXXX
Note 1:
2:
3:
4:
Conditions
μs
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
DS39887C-page 36
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F2455/
2550/4455/4550 Data Sheet” (DS39632).
© 2009 Microchip Technology Inc.
DS39887C-page 37
PIC18F2458/2553/4458/4553
NOTES:
DS39887C-page 38
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
APPENDIX A:
REVISION HISTORY
Revision A (May 2007)
Original data sheet for the PIC18F2458/2553/4458/
4553 devices.
APPENDIX B:
DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
Revision B (June 2007)
Changes to Figure 4-2: PIC18LF2458/2553/4458/4553
Voltage-Frequency Graph (Industrial).
Revision C (October 2009)
Removed “Preliminary” marking.
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
Program Memory (Bytes)
24576
32768
24576
32768
Program Memory (Instructions)
12288
16384
12288
16384
19
19
20
20
Ports A, B, C, (E)
Ports A, B, C, (E)
Interrupt Sources
I/O Ports
Ports A, B, C, D, E Ports A, B, C, D, E
Capture/Compare/PWM Modules
2
2
1
1
Enhanced Capture/Compare/
PWM Modules
0
0
1
1
Parallel Communications (SPP)
No
No
Yes
Yes
12-Bit Analog-to-Digital Module
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
Packages
© 2009 Microchip Technology Inc.
DS39887C-page 39
PIC18F2458/2553/4458/4553
APPENDIX C:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
APPENDIX D:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Application Note is available as Literature Number
DS00726.
This Application Note is available as Literature Number
DS00716.
DS39887C-page 40
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
INDEX
A
M
A/D ..................................................................................... 21
A/D Converter Interrupt, Configuring ......................... 25
Acquisition Requirements .......................................... 26
ADCON0 Register ...................................................... 21
ADCON1 Register ...................................................... 21
ADCON2 Register ...................................................... 21
ADRESH Register ................................................ 21, 24
ADRESL Register ...................................................... 21
Analog Port Pins, Configuring .................................... 28
Associated Registers ................................................. 30
Calculating the Minimum Required Acquisition Time . 26
Configuring the Module .............................................. 25
Conversion Clock (TAD) ............................................. 27
Conversion Status (GO/DONE Bit) ............................ 24
Conversions ............................................................... 29
Converter Characteristics .......................................... 35
Discharge ................................................................... 29
Operation in Power-Managed Modes ........................ 28
Selecting and Configuring Acquisition Time .............. 27
Special Event Trigger (CCP) ...................................... 30
Use of the CCP2 Trigger ............................................ 30
Absolute Maximum Ratings ............................................... 33
ADCON0 Register .............................................................. 21
GO/DONE Bit ............................................................. 24
ADCON1 Register .............................................................. 21
ADCON2 Register .............................................................. 21
ADRESH Register .............................................................. 21
ADRESL Register ........................................................ 21, 24
Analog-to-Digital Converter. See A/D.
Microchip Internet Web Site ............................................... 43
Migration from High-End to Enhanced Devices ................. 40
Migration from Mid-Range to Enhanced Devices .............. 40
B
Block Diagrams
A/D ............................................................................. 24
Analog Input Model .................................................... 25
PIC18F2458/2553 ........................................................ 9
PIC18F4458/4553 ...................................................... 10
C
Compare (CCP Module)
Special Event Trigger ................................................. 30
Customer Change Notification Service .............................. 43
Customer Notification Service ............................................ 43
Customer Support .............................................................. 43
D
Device Differences ............................................................. 39
Device ID Registers ........................................................... 31
Device Overview .................................................................. 7
Other Special Features ................................................ 7
E
Electrical Characteristics .................................................... 33
Equations
A/D Acquisition Time .................................................. 26
A/D Minimum Charging Time ..................................... 26
Errata ................................................................................... 6
I
Internet Address ................................................................. 43
Interrupt Sources
A/D Conversion Complete ......................................... 25
© 2009 Microchip Technology Inc.
P
Packaging Information ....................................................... 37
Pin Functions
MCLR/VPP/RE3 ......................................................... 11
MCLR/VPP/RE3 ......................................................... 15
NC/ICCK/ICPGC ....................................................... 20
NC/ICDT/ICPGD ........................................................ 20
NC/ICPORTS ............................................................ 20
NC/ICRST/ICVPP ....................................................... 20
OSC1/CLKI .......................................................... 11, 15
OSC2/CLKO/RA6 ................................................ 11, 15
RA0/AN0 .............................................................. 12, 16
RA1/AN1 .............................................................. 12, 16
RA2/AN2/VREF-/CVREF ....................................... 12, 16
RA3/AN3/VREF+ .................................................. 12, 16
RA4/T0CKI/C1OUT/RCV ..................................... 12, 16
RA5/AN4/SS/HLVDIN/C2OUT ............................ 12, 16
RB0/AN12/INT0/FLT0/SDI/SDA .......................... 13, 17
RB1/AN10/INT1/SCK/SCL .................................. 13, 17
RB2/AN8/INT2/VMO ............................................ 13, 17
RB3/AN9/CCP2/VPO .......................................... 13, 17
RB4/AN11/KBI0 ......................................................... 13
RB4/AN11/KBI0/CSSPP ............................................ 17
RB5/KBI1/PGM .................................................... 13, 17
RB6/KBI2/PGC .................................................... 13, 17
RB7/KBI3/PGD .................................................... 13, 17
RC0/T1OSO/T13CKI ........................................... 14, 18
RC1/T1OSI/CCP2/UOE ....................................... 14, 18
RC2/CCP1 ................................................................. 14
RC2/CCP1/P1A ......................................................... 18
RC4/D-/VM .......................................................... 14, 18
RC5/D+/VP .......................................................... 14, 18
RC6/TX/CK .......................................................... 14, 18
RC7/RX/DT/SDO ................................................. 14, 18
RD0/SPP0 ................................................................. 19
RD1/SPP1 ................................................................. 19
RD2/SPP2 ................................................................. 19
RD3/SPP3 ................................................................. 19
RD4/SPP4 ................................................................. 19
RD5/SPP5/P1B ......................................................... 19
RD6/SPP6/P1C ......................................................... 19
RD7/SPP7/P1D ......................................................... 19
RE0/AN5/CK1SPP .................................................... 20
RE1/AN6/CK2SPP .................................................... 20
RE2/AN7/OESPP ...................................................... 20
VDD ...................................................................... 14, 20
VSS ...................................................................... 14, 20
VUSB .................................................................... 14, 20
Pinout I/O Descriptions
PIC18F2458/2553 ..................................................... 11
PIC18F4458/4553 ..................................................... 15
Power-Managed Modes
and A/D Operation ..................................................... 28
R
Reader Response .............................................................. 44
Registers
ADCON0 (A/D Control 0) ........................................... 21
DS39887C-page 41
PIC18F2458/2553/4458/4553
ADCON1 (A/D Control 1) ........................................... 22
ADCON2 (A/D Control 2) ........................................... 23
DEVID1 (Device ID 1) ................................................ 32
DEVID2 (Device ID 2) ................................................ 32
Revision History ................................................................. 39
S
Special Features of the CPU .............................................. 31
T
Timing Diagrams
A/D Conversion .......................................................... 36
Timing Diagrams and Specifications
A/D Conversion Requirements .................................. 36
W
WWW Address ................................................................... 43
WWW, On-Line Support ....................................................... 6
DS39887C-page 42
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
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© 2009 Microchip Technology Inc.
DS39887C-page 43
PIC18F2458/2553/4458/4553
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Device: PIC18F2458/2553/4458/4553
Literature Number: DS39887C
Questions:
1. What are the best features of this document?
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3. Do you find the organization of this document easy to follow? If not, why?
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DS39887C-page 44
© 2009 Microchip Technology Inc.
PIC18F2458/2553/4458/4553
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device
PIC18F2458/2553(1), PIC18F4458/4553(1),
PIC18F2458/2553T(2), PIC18F4458/4553T(2);
VDD range 4.2V to 5.5V
PIC18LF2458/2553(1), PIC18LF4458/4553(1),
PIC18LF2458/2553T(2), PIC18LF4458/4553T(2);
VDD range 2.0V to 5.5V
Temperature Range
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package
PT
SO
SP
P
ML
=
=
=
=
=
TQFP (Thin Quad Flatpack)
SOIC
Skinny PDIP
PDIP
QFN
Pattern
c)
PIC18LF4553-I/P 301 = Industrial temp., PDIP
package, Extended VDD limits, QTP pattern
#301.
PIC18LF2458-I/SO = Industrial temp., SOIC
package, Extended VDD limits.
PIC18F4458-I/P = Industrial temp., PDIP
package, normal VDD limits.
Note 1:
2:
F = Standard Voltage Range
LF = Wide Voltage Range
T = In tape and reel TQFP
packages only.
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2009 Microchip Technology Inc.
DS39887C-page 45
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03/26/09
DS39887C-page 46
© 2009 Microchip Technology Inc.