PIC18F2XXX/4XXX Flash MCU Programming Specification

PIC18F2XXX/4XXX FAMILY
Flash Microcontroller Programming Specification
1.0
DEVICE OVERVIEW
This document includes the programming specifications for the following devices:
• PIC18F2221
• PIC18F2580
• PIC18F4480
• PIC18F2321
• PIC18F2585
• PIC18F4510
• PIC18F2410
• PIC18F2610
• PIC18F4515
• PIC18F2420
• PIC18F2620
• PIC18F4520
• PIC18F2423
• PIC18F2680
• PIC18F4523
• PIC18F2450
• PIC18F2682
• PIC18F4525
• PIC18F2455
• PIC18F2685
• PIC18F4550
• PIC18F2458
• PIC18F4221
• PIC18F4553
• PIC18F2480
• PIC18F4321
• PIC18F4580
• PIC18F2510
• PIC18F4410
• PIC18F4585
• PIC18F2515
• PIC18F4420
• PIC18F4610
• PIC18F2520
• PIC18F4423
• PIC18F4620
• PIC18F2523
• PIC18F4450
• PIC18F4680
• PIC18F2525
• PIC18F4455
• PIC18F4682
• PIC18F2550
• PIC18F4458
• PIC18F4685
• PIC18F2553
2.0
PROGRAMMING OVERVIEW
PIC18F2XXX/4XXX Family devices can be programmed using either the high-voltage In-Circuit Serial Programming™
(ICSP™) method or the low-voltage ICSP method. Both methods can be done with the device in the user’s system. The
low-voltage ICSP method is slightly different than the high-voltage method and these differences are noted where
applicable.
This programming specification applies to the PIC18F2XXX/4XXX Family devices in all package types.
2.1
Hardware Requirements
In High-Voltage ICSP mode, PIC18F2XXX/4XXX Family devices require two programmable power supplies: one for
VDD and one for MCLR/VPP/RE3. Both supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 “AC/
DC Characteristics Timing Requirements for Program/Verify Test Mode” for additional hardware parameters.
2.1.1
LOW-VOLTAGE ICSP PROGRAMMING
In Low-Voltage ICSP mode, PIC18F2XXX/4XXX Family devices can be programmed using a VDD source in the
operating range. The MCLR/VPP/RE3 does not have to be brought to a different voltage, but can instead be left at the
normal operating voltage. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify
Test Mode” for additional hardware parameters.
2.2
Pin Diagrams
The pin diagrams for the PIC18F2XXX/4XXX Family are shown in Figure 2-1, Figure 2-2, Figure 2-3, Figure 2-4,
Figure 2-5.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 1
PIC18F2XXX/4XXX FAMILY
TABLE 2-1:
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XXX/4XXX FAMILY
During Programming
Pin Name
Pin Name
Pin Type
MCLR/VPP/RE3
VPP
P
Programming Enable
VDD(2)
VDD
P
Power Supply
VSS(2)
VSS
P
Ground
RB5
PGM
I
Low-Voltage ICSP™ Input when LVP Configuration bit equals ‘1’(1)
RB6
PGC
I
Serial Clock
RB7
PGD
I/O
Serial Data
Legend:
Note 1:
2:
Pin Description
I = Input, O = Output, P = Power
See Figure 5-1 for more information.
All power supply (VDD) and ground (VSS) pins must be connected.
The following devices are included in 28-pin SPDIP, PDIP and SOIC parts:
• PIC18F2221
• PIC18F2480
• PIC18F2580
• PIC18F2321
• PIC18F2510
• PIC18F2585
• PIC18F2410
• PIC18F2515
• PIC18F2610
• PIC18F2420
• PIC18F2520
• PIC18F2620
• PIC18F2423
• PIC18F2523
• PIC18F2680
• PIC18F2450
• PIC18F2525
• PIC18F2682
• PIC18F2455
• PIC18F2550
• PIC18F2685
• PIC18F2458
• PIC18F2553
The following devices are included in 28-pin SSOP parts:
• PIC18F2221
28-Pin SPDIP, PDIP, SOIC,SSOP
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
DS30009622M-page 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18F2XXX
FIGURE 2-1:
• PIC18F2321
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
The following devices are included in 28-pin QFN parts:
• PIC18F2221
• PIC18F2423
• PIC18F2510
• PIC18F2580
• PIC18F2321
• PIC18F2450
• PIC18F2520
• PIC18F2682
• PIC18F2410
• PIC18F2480
• PIC18F2523
• PIC18F2685
• PIC18F2420
•
•
•
MCLR/VPP/RE3
RB7/PGD
RB6/PGC
RB5/PGM
RB4
28-Pin QFN
RA1
RA0
FIGURE 2-2:
28 27 26 25 24 23 22
RA2
RA3
RA4
RA5
VSS
OSC1
OSC2
1
2
3
4
5
6
7
PIC18F2XXX
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
8 9 10 11 12 13 14
The following devices are included in 40-pin PDIP parts:
• PIC18F4221
• PIC18F4455
• PIC18F4523
• PIC18F4610
• PIC18F4321
• PIC18F4458
• PIC18F4525
• PIC18F4620
• PIC18F4410
• PIC18F4480
• PIC18F4550
• PIC18F4680
• PIC18F4420
• PIC18F4510
• PIC18F4553
• PIC18F4682
• PIC18F4423
• PIC18F4515
• PIC18F4580
• PIC18F4685
• PIC18F4450
• PIC18F4520
• PIC18F4585
•
40-Pin PDIP
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
OSC1
OSC2
RC0
RC1
RC2
RC3
RD0
RD1
 2010-2015 Microchip Technology Inc.
2
40
39
3
4
38
37
5
36
6
35
7
8
34
33
32
1
9
10
11
12
13
14
PIC18F4XXX
FIGURE 2-3:
31
30
29
28
15
27
26
16
25
17
18
24
23
19
20
22
21
RB7/PGD
RB6/PGC
RB5/PGM
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
DS30009622M-page 3
PIC18F2XXX/4XXX FAMILY
The following devices are included in 44-pin TQFP parts:
• PIC18F4221
• PIC18F4523
• PIC18F4321
• PIC18F4525
• PIC18F4410
• PIC18F4550
• PIC18F4420
• PIC18F4553
• PIC18F4423
• PIC18F4580
• PIC18F4450
• PIC18F4585
• PIC18F4455
• PIC18F4610
• PIC18F4458
• PIC18F4620
• PIC18F4480
• PIC18F4680
• PIC18F4510
• PIC18F4682
• PIC18F4520
• PIC18F4685
• PIC18F4515
44-PIN TQFP
PIC18F4XXX
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC(1)/ICVPP
RC0
OSC2
OSC1
VSS
VDD
RE2
RE1
RE0
RA5
RA4
NC(1)/ICPGC
NC(1)/ICPGD
RB4
RB5/PGM
RB6/PGC
RB7/PGD
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC(1)/ICPORTS
FIGURE 2-4:
Note 1:
These pins are NC (No Connect) for all devices listed above with the exception of the PIC18F4450, PIC18F4455,
PIC18F4458 and the PIC18F4553 devices (see Section 2.8 “Dedicated ICSP/ICD Port (44-Pin TQFP Only)” for
more information on programming these pins in these devices).
DS30009622M-page 4
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
The following devices are included in 44-pin QFN parts:
• PIC18F4221
• PIC18F4523
• PIC18F4321
• PIC18F4525
• PIC18F4410
• PIC18F4550
• PIC18F4420
• PIC18F4553
• PIC18F4423
• PIC18F4580
• PIC18F4450
• PIC18F4585
• PIC18F4455
• PIC18F4610
• PIC18F4458
• PIC18F4620
• PIC18F4480
• PIC18F4680
• PIC18F4510
• PIC18F4682
• PIC18F4520
• PIC18F4685
• PIC18F4515
44-PIN QFN
44
43
42
41
40
39
38
37
36
35
34
RC6
D+/VP
D-/VM
RD3
RD2
RD1
RD0
VUSB
RC2
RC1
RC0
FIGURE 2-5:
PIC18F4XXX
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2
OSC1
VSS
AVSS
VDD
AVDD
RE2
RE1
RE0
RA5
RA4
RB3
NC
RB4
RB5/PGM
RB6/PGC
RB7/PGD
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RC7
RD4
RD5
RD6
RD7
VSS
AVDD
VDD
RB0
RB1
RB2
2.3
Memory Maps
For PIC18FX6X0 devices, the code memory space extends from 0000h to 0FFFFh (64 Kbytes) in four 16-Kbyte blocks.
For PIC18FX5X5 devices, the code memory space extends from 0000h to 0BFFFFh (48 Kbytes) in three 16-Kbyte
blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block
0. All of these blocks define code protection boundaries within the code memory space.
The size of the Boot Block in PIC18F2585/2680/4585/4680 devices can be configured as 1, 2 or 4K words (see
Figure 2-6). This is done through the BBSIZ<1:0> bits in the Configuration register, CONFIG4L. It is important to note
that increasing the size of the Boot Block decreases the size of Block 0.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 5
PIC18F2XXX/4XXX FAMILY
TABLE 2-2:
IMPLEMENTATION OF CODE MEMORY
Device
Code Memory Size (Bytes)
PIC18F2515
PIC18F2525
PIC18F2585
000000h-00BFFFh (48K)
PIC18F4515
PIC18F4525
PIC18F4585
PIC18F2610
PIC18F2620
PIC18F2680
000000h-00FFFFh (64K)
PIC18F4610
PIC18F4620
PIC18F4680
FIGURE 2-6:
MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FX5X5/X6X0 DEVICES
000000h
MEMORY SIZE/DEVICE
Code Memory
48 Kbytes
(PIC18FX5X5)
64 Kbytes
(PIC18FX6X0)
01FFFFh
Address
Range
BBSIZ<1:0>
11/10
Unimplemented
Read as ‘0’
Boot
Block*
01
Boot
Block*
00
11/10
Boot
Block*
Boot
Block*
01
Boot
Block*
Boot
Block*
Block 0
Block 0
Block 0
000000h
0007FFh
000800h
000FFFh
001000h
Block 0
200000h
00
001FFFh
002000h
Block 0
Block 0
003FFFh
004000h
Block 1
Configuration
and ID
Space
Block 1
007FFFh
008000h
Block 2
Block 2
00BFFFh
00C000h
Block 3
Unimplemented
Reads all ‘0’s
3FFFFFh
Note:
*
Unimplemented
Reads all ‘0’s
00FFFFh
01FFFFh
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register.
DS30009622M-page 6
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
For PIC18F2685/4685 devices, the code memory space extends from 0000h to 017FFFh (96 Kbytes) in five 16-Kbyte
blocks. For PIC18F2682/4682 devices, the code memory space extends from 0000h to 0013FFFh (80 Kbytes) in four
16-Kbyte blocks. Addresses, 0000h through 0FFFh, however, define a “Boot Block” region that is treated separately
from Block 0. All of these blocks define code protection boundaries within the code memory space.
The size of the Boot Block in PIC18F2685/4685 and PIC18F2682/4682 devices can be configured as 1, 2 or 4K words
(see Figure 2-7). This is done through the BBSIZ<2:1> bits in the Configuration register, CONFIG4L. It is important to
note that increasing the size of the Boot Block decreases the size of Block 0.
TABLE 2-3:
IMPLEMENTATION OF CODE MEMORY
Device
PIC18F2682
PIC18F4682
PIC18F2685
PIC18F4685
 2010-2015 Microchip Technology Inc.
Code Memory Size (Bytes)
000000h-013FFFh (80K)
000000h-017FFFh (96K)
DS30009622M-page 7
PIC18F2XXX/4XXX FAMILY
FIGURE 2-7:
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18F2685/4685 AND PIC18F2682/4682 DEVICES
Address
Range
MEMORY SIZE/DEVICE
000000h
Code Memory
80 Kbytes
(PIC18F2682/4682)
96 Kbytes
(PIC18F2685/4685)
01FFFFh
BBSIZ1:BBSIZ2
11/10
Unimplemented
Read as ‘0’
Boot
Block*
01
Boot
Block*
00
11/10
Boot
Block*
Boot
Block*
01
Boot
Block*
00
Boot
Block*
0007FFh
000800h
000FFFh
001000h
Block 0
Block 0
Block 0
Block 0
000000h
001FFFh
002000h
Block 0
Block 0
003FFFh
004000h
200000h
Block 1
Block 1
007FFFh
008000h
Block 2
Configuration
and ID
Space
Block 2
00BFFFh
00C000h
Block 3
Block 3
00FFFFh
010000h
Block 4
Block 4
013FFFh
014000h
Block 5
3FFFFFh
Note:
*
Unimplemented
Reads all ‘0’s
Unimplemented
Reads all ‘0’s
017FFFh
01FFFFh
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:2> bits in the CONFIG4L register.
For PIC18FX5X0/X5X3 devices, the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte
blocks. For PIC18FX4X5/X4X8 devices, the code memory space extends from 000000h to 005FFFh (24 Kbytes) in
three 8-Kbyte blocks. Addresses, 000000h through 0007FFh, however, define a “Boot Block” region that is treated
separately from Block 0. All of these blocks define code protection boundaries within the code memory space.
DS30009622M-page 8
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 2-4:
IMPLEMENTATION OF CODE MEMORY
Device
Code Memory Size (Bytes)
PIC18F2455
PIC18F2458
PIC18F4455
PIC18F4458
PIC18F2510
PIC18F2520
PIC18F2523
PIC18F2550
PIC18F2553
PIC18F4510
PIC18F4520
PIC18F4523
PIC18F4550
PIC18F4553
FIGURE 2-8:
000000h-005FFFh (24K)
000000h-007FFFh (32K)
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18FX4X5/X4X8/X5X0/X5X3 DEVICES
000000h
Code Memory
1FFFFFh
MEMORY SIZE/DEVICE
Unimplemented
Read as ‘0’
32 Kbytes
(PIC18FX5X0/X5X3)
24 Kbytes
(PIC18FX4X5/X4X8)
Address
Range
Boot Block
Boot Block
000000h
0007FFh
Block 0
Block 0
000800h
001FFFh
Block 1
Block 1
002000h
003FFFh
Block 2
Block 2
004000h
005FFFh
200000h
006000h
007FFFh
Block 3
008000h
Configuration
and ID
Space
Unimplemented
Reads all ‘0’s
Unimplemented
Reads all ‘0’s
1FFFFFh
3FFFFFh
Note:
Sizes of memory areas are not to scale.
For PIC18FX4X0/X4X3 devices, the code memory space extends from 000000h to 003FFFh (16 Kbytes) in two 8-Kbyte
blocks. Addresses, 000000h through 0003FFh, however, define a “Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection boundaries within the code memory space.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 9
PIC18F2XXX/4XXX FAMILY
TABLE 2-5:
IMPLEMENTATION OF CODE MEMORY
Device
Code Memory Size (Bytes)
PIC18F2410
PIC18F2420
PIC18F2423
PIC18F2450
000000h-003FFFh (16K)
PIC18F4410
PIC18F4420
PIC18F4450
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18FX4X0/X4X3 DEVICES
FIGURE 2-9:
000000h
Code Memory
1FFFFFh
MEMORY SIZE/
DEVICE
16 Kbytes
Address
(PIC18FX4X0/X4X3) Range
Unimplemented
Read as ‘0’
Boot Block
000000h
0007FFh
Block 0
000800h
001FFFh
Block 1
002000h
003FFFh
004000h
005FFFh
200000h
006000h
007FFFh
008000h
Unimplemented
Reads all ‘0’s
Configuration
and ID
Space
1FFFFFh
3FFFFFh
Note:
Sizes of memory areas are not to scale.
For PIC18F2480/4480 devices, the code memory space extends from 0000h to 03FFFh (16 Kbytes) in one 16-Kbyte
block. For PIC18F2580/4580 devices, the code memory space extends from 0000h to 07FFFh (32 Kbytes) in two
16-Kbyte blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately
from Block 0. All of these blocks define code protection boundaries within the code memory space.
The size of the Boot Block in PIC18F2480/2580/4480/4580 devices can be configured as 1 or 2K words (see
Figure 2-10). This is done through the BBSIZ<0> bit in the Configuration register, CONFIG4L. It is important to note that
increasing the size of the Boot Block decreases the size of Block 0.
DS30009622M-page 10
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 2-6:
IMPLEMENTATION OF CODE MEMORY
Device
Code Memory Size (Bytes)
PIC18F2480
000000h-003FFFh (16K)
PIC18F4480
PIC18F2580
000000h-007FFFh (32K)
PIC18F4580
FIGURE 2-10:
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18F2480/2580/4480/4580 DEVICES
000000h
Address
Range
MEMORY SIZE/DEVICE
Code Memory
01FFFFh
32 Kbytes
(PIC18FX580)
16 Kbytes
(PIC18FX480)
BBSIZ<0>
1
Unimplemented
Read as ‘0’
0
1
Boot Block*
Boot Block*
Boot Block*
0
000000h
0007FFh
000800h
000FFFh
001000h
Boot Block*
Block 0
Block 0
Block 0
Block 0
001FFFh
002000h
200000h
Block 1
Configuration
and ID
Space
003FFFh
004000h
Block 2
005FFFh
006000h
Block 3
Unimplemented
Reads all ‘0’s
007FFFh
3FFFFFh
Unimplemented
Reads all ‘0’s
01FFFFh
Note:
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<0> bit in the CONFIG4L register.
For PIC18F2221/4221 devices, the code memory space extends from 0000h to 00FFFh (4 Kbytes) in one 4-Kbyte
block. For PIC18F2321/4321 devices, the code memory space extends from 0000h to 01FFFh (8 Kbytes) in two 4-Kbyte
blocks. Addresses, 0000h through 07FFh, however, define a variable “Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection boundaries within the code memory space.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 11
PIC18F2XXX/4XXX FAMILY
The size of the Boot Block in PIC18F2221/2321/4221/4321 devices can be configured as 256, 512 or 1024 words (see
Figure 2-11). This is done through the BBSIZ<1:0> bits in the Configuration register, CONFIG4L (see Figure 2-11). It is
important to note that increasing the size of the Boot Block decreases the size of Block 0.
TABLE 2-7:
IMPLEMENTATION OF CODE MEMORY
Device
Code Memory Size (Bytes)
PIC18F2221
000000h-000FFFh (4K)
PIC18F4221
PIC18F2321
000000h-001FFFh (8K)
PIC18F4321
FIGURE 2-11:
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18F2221/2321/4221/4321 DEVICES
Address
Range
MEMORY SIZE/DEVICE
8 Kbytes
(PIC18FX321)
000000h
01FFFFh
4 Kbytes
(PIC18FX221)
Code Memory
BBSIZ<1:0>
11/10
Unimplemented
Read as ‘0’
01
Boot Block*
512 words
00
Boot Block*
256 words
11/10/01
Boot Block*
512 words
Boot Block*
1K word
Block 0
0.5K words
Block 0
1.5K words
Boot Block*
256 words
Block 0
0.75K words
000000h
0001FFh
000200h
0003FFh
000400h
0007FFh
000800h
Block 0
1.75K words
Block 1
1K word
Block 0
1K word
200000h
00
000FFFh
001000h
Configuration
and ID
Space
Block 1
2K words
3FFFFFh
Note:
*
Unimplemented
Reads all ‘0’s
Unimplemented
Reads all ‘0’s
001FFFh
002000h
1FFFFFh
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register.
DS30009622M-page 12
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
In addition to the code memory space, there are three blocks that are accessible to the user through Table Reads and
Table Writes. Their locations in the memory map are shown in Figure 2-12.
Users may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses, 200000h
through 200007h. The ID locations read out normally, even after code protection is applied.
Locations, 300000h through 30000Dh, are reserved for the Configuration bits. These bits select various device options
and are described in Section 5.0 “Configuration Word”. These Configuration bits read out normally, even after code
protection.
Locations, 3FFFFEh and 3FFFFFh, are reserved for the Device ID bits. These bits may be used by the programmer to
identify what device type is being programmed and are described in Section 5.0 “Configuration Word”. These Device
ID bits read out normally, even after code protection.
2.3.1
MEMORY ADDRESS POINTER
Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised
of three pointer registers:
• TBLPTRU at RAM address 0FF8h
• TBLPTRH at RAM address 0FF7h
• TBLPTRL at RAM address 0FF6h
TBLPTRU
TBLPTRH
TBLPTRL
Addr[21:16]
Addr[15:8]
Addr[7:0]
The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write
operations.
 2010-2015 Microchip Technology Inc.
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PIC18F2XXX/4XXX FAMILY
FIGURE 2-12:
CONFIGURATION AND ID LOCATIONS FOR PIC18F2XXX/4XXX FAMILY DEVICES
000000h
Code Memory
01FFFFh
Unimplemented
Read as ‘0’
1FFFFFh
Configuration
and ID
Space
2FFFFFh
ID Location 1
200000h
ID Location 2
200001h
ID Location 3
200002h
ID Location 4
200003h
ID Location 5
200004h
ID Location 6
200005h
ID Location 7
200006h
ID Location 8
200007h
CONFIG1L
300000h
CONFIG1H
300001h
CONFIG2L
300002h
CONFIG2H
300003h
CONFIG3L
300004h
CONFIG3H
300005h
CONFIG4L
300006h
CONFIG4H
300007h
CONFIG5L
300008h
CONFIG5H
300009h
CONFIG6L
30000Ah
CONFIG6H
30000Bh
CONFIG7L
30000Ch
CONFIG7H
30000Dh
Device ID1
3FFFFEh
Device ID2
3FFFFFh
3FFFFFh
Note:
Sizes of memory areas are not to scale.
DS30009622M-page 14
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2.4
High-Level Overview of the Programming Process
Figure 2-13 shows the high-level overview of the programming process. First, a Bulk Erase is performed. Next, the code
memory, ID locations and data EEPROM are programmed (selected devices only, see Section 3.3 “Data EEPROM
Programming”). These memories are then verified to ensure that programming was successful. If no errors are detected,
the Configuration bits are then programmed and verified.
FIGURE 2-13:
HIGH-LEVEL PROGRAMMING FLOW
Start
Perform Bulk
Erase
Program Memory
Program IDs
Program Data EE(1)
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Note 1:
Selected devices only, see Section 3.3 “Data EEPROM Programming”.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 15
PIC18F2XXX/4XXX FAMILY
2.5
Entering and Exiting High-Voltage ICSP Program/Verify Mode
As shown in Figure 2-14, the High-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low and
then raising MCLR/VPP/RE3 to VIHH (high voltage). Once in this mode, the code memory, data EEPROM (selected
devices only, see Section 3.3 “Data EEPROM Programming”), ID locations and Configuration bits can be accessed
and programmed in serial fashion. Figure 2-15 shows the exit sequence.
The sequence that enters the device into the Program/Verify mode places all unused I/Os in the high-impedance state.
FIGURE 2-14:
ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE
P13
P12
P1
D110
MCLR/VPP/RE3
VDD
PGD
PGC
PGD = Input
FIGURE 2-15:
EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE
P16
MCLR/VPP/RE3
P17
P1
D110
VDD
PGD
PGC
PGD = Input
DS30009622M-page 16
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2.6
Entering and Exiting Low-Voltage ICSP Program/Verify Mode
When the LVP Configuration bit is ‘1’ (see Section 5.3 “Single-Supply ICSP Programming”), the Low-Voltage ICSP
mode is enabled. As shown in Figure 2-16, Low-Voltage ICSP Program/Verify mode is entered by holding PGC and
PGD low, placing a logic high on PGM and then raising MCLR/VPP/RE3 to VIH. In this mode, the RB5/PGM pin is
dedicated to the programming function and ceases to be a general purpose I/O pin. Figure 2-17 shows the exit
sequence.
The sequence that enters the device into the Program/Verify mode places all unused I/Os in the high-impedance state.
FIGURE 2-16:
ENTERING LOW-VOLTAGE PROGRAM/VERIFY MODE
P12
P15
VIH
MCLR/VPP/RE3
VDD
VIH
PGM
PGD
PGC
PGD = Input
FIGURE 2-17:
EXITING LOW-VOLTAGE PROGRAM/VERIFY MODE
P16
P18
VIH
MCLR/VPP/RE3
VDD
PGM
PGD
VIH
PGC
PGD = Input
 2010-2015 Microchip Technology Inc.
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PIC18F2XXX/4XXX FAMILY
2.7
Serial Program/Verify Operation
The PGC pin is used as a clock input pin and the PGD pin is used for entering command bits and data input/output
during serial operation. Commands and data are transmitted on the rising edge of PGC, latched on the falling edge of
PGC and are Least Significant bit (LSb) first.
2.7.1
4-BIT COMMANDS
All instructions are 20 bits, consisting of a leading 4-bit command followed by a 16-bit operand, which depends on the type
of command being executed. To input a command, PGC is cycled four times. The commands needed for programming
and verification are shown in Table 2-8.
Depending on the 4-bit command, the 16-bit operand represents 16 bits of input data or 8 bits of input data and 8 bits
of output data.
Throughout this specification, commands and data are presented as illustrated in Table 2-9. The 4-bit command is shown
Most Significant bit (MSb) first. The command operand, or “Data Payload”, is shown as <MSB><LSB>. Figure 2-18
demonstrates how to serially present a 20-bit command/operand to the device.
2.7.2
CORE INSTRUCTION
The core instruction passes a 16-bit instruction to the CPU core for execution. This is needed to set up registers as
appropriate for use with other commands.
TABLE 2-8:
COMMANDS FOR PROGRAMMING
Description
4-Bit Command
Core Instruction
(Shift in16-bit instruction)
0000
Shift Out TABLAT Register
0010
Table Read
1000
Table Read, Post-Increment
1001
Table Read, Post-Decrement
1010
Table Read, Pre-Increment
1011
Table Write
1100
Table Write, Post-Increment by 2
1101
Table Write, Start Programming, 
Post-Increment by 2
1110
Table Write, Start Programming
1111
TABLE 2-9:
SAMPLE COMMAND SEQUENCE
4-Bit Command
Data Payload
1101
3C 40
DS30009622M-page 18
Core Instruction
Table Write, 
post-increment by 2
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FIGURE 2-18:
TABLE WRITE, POST-INCREMENT TIMING (1101)
P2
1
2
3
4
P2A
P2B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
1
3
4
PGC
P5A
P5
P4
P3
PGD
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
4
C
16-Bit Data Payload
4-Bit Command
1
0
0
n
n
n
n
3
Fetch Next 4-Bit Command
PGD = Input
2.8
Dedicated ICSP/ICD Port (44-Pin TQFP Only)
The PIC18F4455/4458/4550/4553 44-pin TQFP devices are designed to support an alternate programming input: the
dedicated ICSP/ICD port. The primary purpose of this port is to provide an alternate In-Circuit Debugging (ICD) option
and free the pins (RB6, RB7 and MCLR) that would normally be used for debugging the application. In conjunction with
ICD capability, however, the dedicated ICSP/ICD port also provides an alternate port for ICSP.
Setting the ICPRT Configuration bit enables the dedicated ICSP/ICD port. The dedicated ICSP/ICD port functions the
same as the default ICSP/ICD port; however, alternate pins are used instead of the default pins. Table 2-10 identifies
the functionally equivalent pins for ICSP purposes:
The dedicated ICSP/ICD port is an alternate port. Thus, ICSP is still available through the default port even though the
ICPRT Configuration bit is set. When the VIH is seen on the MCLR/VPP/RE3 pin prior to applying VIH to the ICRST/ICVPP
pin, then the state of the ICRST/ICVPP pin is ignored. Likewise, when the VIH is seen on ICRST/ICVPP prior to applying
VIH to MCLR/VPP/RE3, then the state of the MCLR/VPP/RE3 pin is ignored.
Note:
The ICPRT Configuration bit can only be programmed through the default ICSP port. Chip Erase functions
through the dedicated ICSP/ICD port do not affect this bit.
When the ICPRT Configuration bit is set (dedicated ICSP/ICD port enabled), the NC/ICPORTS pin must
be tied to either VDD or VSS.
The ICPRT Configuration bit must be maintained clear for all 28-pin and 40-pin devices; otherwise,
unexpected operation may occur.
TABLE 2-10:
ICSP™ EQUIVALENT PINS
During Programming
Pin Name
Pin Name
Pin Type
Dedicated Pins
Pin Description
MCLR/VPP/RE3
VPP
P
NC/ICRST/ICVPP
Programming Enable
RB6
PGC
I
NC/ICCK/ICPGC
Serial Clock
RB7
PGD
I/O
NC/ICDT/ICPGD
Serial Data
Legend: I = Input, O = Output, P = Power
 2010-2015 Microchip Technology Inc.
DS30009622M-page 19
PIC18F2XXX/4XXX FAMILY
3.0
DEVICE PROGRAMMING
Programming includes the ability to erase or write the various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the EECON1 register must be configured in order to operate on a
particular memory region.
When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS
bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g.,
erases) and this must be done prior to initiating a write sequence. The FREE bit must be set (EECON1<4> = 1) in order
to erase the program space being pointed to by the Table Pointer. The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended that the WREN bit only be set immediately prior to a program
erase.
3.1
ICSP Erase
3.1.1
HIGH-VOLTAGE ICSP BULK ERASE
Erasing code or data EEPROM is accomplished by configuring two Bulk Erase Control registers located at 3C0004h
and 3C0005h. Code memory may be erased, portions at a time, or the user may erase the entire device in one action.
Bulk Erase operations will also clear any code-protect settings associated with the memory block being erased. Erase
options are detailed in Table 3-1. If data EEPROM is code-protected (CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 3-1).
TABLE 3-1:
BULK ERASE OPTIONS
Description
Data
(3C0005h:3C0004h)
Chip Erase
Erase Data EEPROM
3F8Fh
(1)
0084h
Erase Boot Block
0081h
Erase Configuration Bits
0082h
Erase Code EEPROM Block 0
0180h
Erase Code EEPROM Block 1
0280h
Erase Code EEPROM Block 2
0480h
Erase Code EEPROM Block 3
0880h
Erase Code EEPROM Block 4
1080h
Erase Code EEPROM Block 5
2080h
Note 1:
Selected devices only, see Section 3.3 “Data EEPROM Programming”.
The actual Bulk Erase function is a self-timed operation. Once the erase has started (falling edge of the 4th PGC after
the NOP command), serial execution will cease until the erase completes (Parameter P11). During this time, PGC may
continue to toggle but PGD must be held low.
The code sequence to erase the entire device is shown in Table and the flowchart is shown in Figure 3-1.
Note:
A Bulk Erase is the only way to reprogram code-protect bits from an ON state to an OFF state.
DS30009622M-page 20
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PIC18F2XXX/4XXX FAMILY
TABLE 3-2:
BULK ERASE COMMAND SEQUENCE
4-Bit Command
Data Payload
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0E
6E
0E
6E
0E
6E
3F
0E
6E
0E
6E
0E
6E
8F
0000
0000
00 00
00 00
FIGURE 3-1:
3C
F8
00
F7
05
F6
3F
3C
F8
00
F7
04
F6
8F
Core Instruction
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 3F3Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8F8Fh TO 3C0004h to erase entire device.
NOP
Hold PGD low until erase completes.
BULK ERASE FLOW
Start
Write 3F3Fh
to 3C0005h
Write 8F8Fh to
3C0004h to Erase
Entire Device
Delay P11 + P10
Time
Done
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DS30009622M-page 21
PIC18F2XXX/4XXX FAMILY
3.1.2
LOW-VOLTAGE ICSP BULK ERASE
When using low-voltage ICSP, the part must be supplied by the voltage specified in Parameter D111 if a Bulk Erase is
to be executed. All other Bulk Erase details, as described above, apply.
If it is determined that a program memory erase must be performed at a supply voltage below the Bulk Erase limit, refer
to the erase methodology described in Section 3.1.3 “ICSP Row Erase” and Section 3.2.1 “Modifying Code
Memory”.
If it is determined that a data EEPROM erase (selected devices only, see Section 3.3 “Data EEPROM
Programming”) must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described
in Section 3.3 “Data EEPROM Programming” and write ‘1’s to the array.
FIGURE 3-2:
BULK ERASE TIMING
P10
1
2
3
4
2
1
15 16
1
2
3
4
1
2
15 16
1
2
3
4
1
2
n
n
PGC
P5A
P5
PGD
0
0
1
1
4-Bit Command
1
1
0
16-Bit
Data Payload
0
P5A
P5
0
0
0
0
4-Bit Command
0
0
0
0
16-Bit
Data Payload
P11
0
0
0
0
4-Bit Command
Erase Time
16-Bit
Data Payload
PGD = Input
3.1.3
ICSP ROW ERASE
Regardless of whether high or low-voltage ICSP is used, it is possible to erase one row (64 bytes of data), provided the block
is not code or write-protected. Rows are located at static boundaries, beginning at program memory address, 000000h,
extending to the internal program memory limit (see Section 2.3 “Memory Maps”).
The Row Erase duration is externally timed and is controlled by PGC. After the WR bit in EECON1 is set, a NOP is
issued, where the 4th PGC is held high for the duration of the programming time, P9.
After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by
Parameter P10 to allow high-voltage discharge of the memory array.
The code sequence to Row Erase a PIC18F2XXX/4XXX Family device is shown in Table 3-3. The flowchart, shown in
Figure 3-3, depicts the logic necessary to completely erase a PIC18F2XXX/4XXX Family device. The timing diagram
that details the Start Programming command and Parameters P9 and P10 is shown in Figure 3-5.
Note:
The TBLPTR register can point to any byte within the row intended for erase.
DS30009622M-page 22
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PIC18F2XXX/4XXX FAMILY
TABLE 3-3:
4-Bit
Command
ERASE CODE MEMORY CODE SEQUENCE
Data Payload
Core Instruction
Step 1: Direct access to code memory and enable writes.
0000
0000
0000
8E A6
9C A6
84 A6
BSF
BCF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
CLRF
CLRF
CLRF
TBLPTRU
TBLPTRH
TBLPTRL
Step 2: Point to first row in code memory.
0000
0000
0000
6A F8
6A F7
6A F6
Step 3: Enable erase and erase single row.
0000
0000
0000
88 A6
82 A6
00 00
BSF
EECON1, FREE
BSF
EECON1, WR
NOP – hold PGC high for time P9 and low for time P10.
Step 4: Repeat Step 3, with the Address Pointer incremented by 64 until all rows are erased.
FIGURE 3-3:
SINGLE ROW ERASE CODE MEMORY FLOW
Start
Addr = 0
Configure
Device for
Row Erases
Start Erase Sequence
and Hold PGC High
for Time P9
Addr = Addr + 64
Hold PGC Low
for Time P10
No
All
rows
done?
Yes
Done
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PIC18F2XXX/4XXX FAMILY
3.2
Code Memory Programming
Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming
sequence. The write and erase buffer sizes, shown in Table 3-4, can be mapped to any location of the same size,
beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the proper
amount of code memory that contains the Table Pointer.
The programming duration is externally timed and is controlled by PGC. After a Start Programming command is issued
(4-bit command, ‘1111’), a NOP is issued, where the 4th PGC is held high for the duration of the programming time, P9.
After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by
Parameter P10 to allow high-voltage discharge of the memory array.
The code sequence to program a PIC18F2XXX/4XXX Family device is shown in Table 3-5. The flowchart, shown in
Figure 3-4, depicts the logic necessary to completely write a PIC18F2XXX/4XXX Family device. The timing diagram
that details the Start Programming command and Parameters P9 and P10 is shown in Figure 3-5.
Note:
The TBLPTR register must point to the same region when initiating the programming sequence as it did
when the write buffers were loaded.
TABLE 3-4:
WRITE AND ERASE BUFFER SIZES
Devices (Arranged by Family)
Write Buffer Size (Bytes)
Erase Buffer Size (Bytes)
PIC18F2221, PIC18F2321, PIC18F4221, PIC18F4321
8
64
PIC18F2450, PIC18F4450
16
64
32
64
64
64
PIC18F2410, PIC18F2510, PIC18F4410, PIC18F4510
PIC18F2420, PIC18F2520, PIC18F4420, PIC18F4520
PIC18F2423, PIC18F2523, PIC18F4423, PIC18F4523
PIC18F2480, PIC18F2580, PIC18F4480, PIC18F4580
PIC18F2455, PIC18F2550, PIC18F4455, PIC18F4550
PIC18F2458, PIC18F2553, PIC18F4458, PIC18F4553
PIC18F2515, PIC18F2610, PIC18F4515, PIC18F4610
PIC18F2525, PIC18F2620, PIC18F4525, PIC18F4620
PIC18F2585, PIC18F2680, PIC18F4585, PIC18F4680
PIC18F2682, PIC18F2685, PIC18F4682, PIC18F4685
DS30009622M-page 24
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PIC18F2XXX/4XXX FAMILY
TABLE 3-5:
WRITE CODE MEMORY CODE SEQUENCE
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to code memory and enable writes.
0000
0000
8E A6
9C A6
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
<Addr[21:16]>
TBLPTRU
<Addr[15:8]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
Step 2: Load write buffer.
0000
0000
0000
0000
0000
0000
0E
6E
0E
6E
0E
6E
<Addr[21:16]>
F8
<Addr[15:8]>
F7
<Addr[7:0]>
F6
Step 3: Repeat for all but the last two bytes.
1101
<MSB><LSB>
Write 2 bytes and post-increment address by 2.
Step 4: Load write buffer for last two bytes.
1111
0000
<MSB><LSB>
00 00
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
To continue writing data, repeat Steps 2 through 4, where the Address Pointer is incremented by 2 at each iteration of the loop.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 25
PIC18F2XXX/4XXX FAMILY
FIGURE 3-4:
PROGRAM CODE MEMORY FLOW
Start
N=1
LoopCount = 0
Configure
Device for
Writes
Load 2 Bytes
to Write
Buffer at <Addr>
N=N+1
All
bytes
written?
No
Yes
N=1
LoopCount =
LoopCount + 1
Start Write Sequence
and Hold PGC
High until Done
and Wait P9
Hold PGC Low
for Time P10
All
locations
done?
No
Yes
Done
TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
FIGURE 3-5:
P10
1
2
3
4
1
3
2
4
5
6
15
16
1
2
3
4
PGC
2
3
P5A
P5
PGD
1
P9
1
1
1
1
4-Bit Command
n
n
n
n
n
n
n
n
16-Bit Data Payload
0
0
0
0
4-Bit Command
0
Programming Time
0
0
16-Bit
Data Payload
PGD = Input
DS30009622M-page 26
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3.2.1
MODIFYING CODE MEMORY
The previous programming example assumed that the device had been Bulk Erased prior to programming (see
Section 3.1.1 “High-Voltage ICSP Bulk Erase”). It may be the case, however, that the user wishes to modify only a
section of an already programmed device.
The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in
Section 4.2 “Verify Code Memory and ID Locations”) and buffered. Modifications can be made on this buffer. Then,
the block of code memory that was read out must be erased and rewritten with the modified data.
The WREN bit must be set if the WR bit in EECON1 is used to initiate a write sequence.
TABLE 3-6:
MODIFYING CODE MEMORY
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to code memory.
Step 2: Read and modify code memory (see Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”).
0000
0000
8E A6
9C A6
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
Step 3: Set the Table Pointer for the block to be erased.
0000
0000
0000
0000
0000
0000
0E
6E
0E
6E
0E
6E
<Addr[21:16]>
F8
<Addr[8:15]>
F7
<Addr[7:0]>
F6
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
Step 4: Enable memory writes and set up an erase.
0000
0000
84 A6
88 A6
BSF
BSF
EECON1, WREN
EECON1, FREE
Step 5: Initiate erase.
0000
0000
82 A6
00 00
BSF
EECON1, WR
NOP - hold PGC high for time P9 and low for time P10.
Step 6: Load write buffer. The correct bytes will be selected based on the Table Pointer.
0000
0000
0000
0000
0000
0000
1101
.
.
.
1111
0000
0E <Addr[21:16]>
6E F8
0E <Addr[8:15]>
6E F7
0E <Addr[7:0]>
6E F6
<MSB><LSB>
.
.
.
<MSB><LSB>
00 00
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write 2
<Addr[21:16]>
TBLPTRU
<Addr[8:15]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
bytes and post-increment address by 2.
Repeat as many times as necessary to fill the write buffer
Write 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
To continue modifying data, repeat Steps 2 through 6, where the Address Pointer is incremented by the appropriate number of bytes
(see Table 3-4) at each iteration of the loop. The write cycle must be repeated enough times to completely rewrite the contents of
the erase buffer.
Step 7: Disable writes.
0000
94 A6
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BCF
EECON1, WREN
DS30009622M-page 27
PIC18F2XXX/4XXX FAMILY
3.3
Note:
Data EEPROM Programming
Data EEPROM programming is not available on the following devices:
PIC18F2410
PIC18F4410
PIC18F2450
PIC18F4450
PIC18F2510
PIC18F4510
PIC18F2515
PIC18F4515
PIC18F2610
PIC18F4610
Data EEPROM is accessed one byte at a time via an Address Pointer (register pair: EEADRH:EEADR) and a data latch
(EEDATA). Data EEPROM is written by loading EEADRH:EEADR with the desired memory location, EEDATA, with the
data to be written and initiating a memory write by appropriately configuring the EECON1 register. A byte write
automatically erases the location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data EEPROM write, both the EEPGD and CFGS bits must be cleared
(EECON1<7:6> = 00). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort and this must be done
prior to initiating a write sequence. The write sequence is initiated by setting the WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC after the WR bit is set. It ends when the WR bit is cleared by
hardware.
After the programming sequence terminates, PGC must still be held low for the time specified by Parameter P10 to allow
high-voltage discharge of the memory array.
FIGURE 3-6:
PROGRAM DATA FLOW
Start
Set Address
Set Data
Enable Write
Start Write
Sequence
WR bit
clear?
No
Yes
No
Done?
Yes
Done
DS30009622M-page 28
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
FIGURE 3-7:
DATA EEPROM WRITE TIMING
P10
1
2
3
4
1
2
1
15 16
2
PGC
P5A
P5
PGD
0
0
0
P11A
n
0
4-Bit Command
16-Bit Data
Payload
Poll WR bit, Repeat until Clear
(see below)
BSF EECON1, WR
n
PGD = Input
1
2
3
4
1
2
15 16
1
2
3
4
1
2
15 16
PGC
P5
P5
P5A
P5A
Poll WR bit
PGD
0
0
0
0
0
4-Bit Command MOVF EECON1, W, 0
PGD = Input
 2010-2015 Microchip Technology Inc.
0
0
0
4-Bit Command
MOVWF TABLAT
Shift Out Data
(see Figure 4-4)
PGD = Output
DS30009622M-page 29
PIC18F2XXX/4XXX FAMILY
TABLE 3-7:
PROGRAMMING DATA MEMORY
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF
BCF
EECON1, EEPGD
EECON1, CFGS
MOVLW
MOVWF
MOVLW
MOVWF
<Addr>
EEADR
<AddrH>
EEADRH
MOVLW
MOVWF
<Data>
EEDATA
BSF
EECON1, WREN
BSF
EECON1, WR
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E
6E
OE
6E
<Addr>
A9
<AddrH>
AA
Step 3: Load the data to be written.
0000
0000
0E <Data>
6E A8
Step 4: Enable memory writes.
0000
84 A6
Step 5: Initiate write.
0000
82 A6
Step 6: Poll WR bit, repeat until the bit is clear.
0000
0000
0000
0010
50 A6
6E F5
00 00
<MSB><LSB>
MOVF
EECON1, W, 0
MOVWF
TABLAT
NOP
Shift out data(1)
Step 7: Hold PGC low for time P10.
Step 8: Disable writes.
0000
94 A6
BCF
EECON1, WREN
Repeat Steps 2 through 8 to write more data.
Note 1: See Figure 4-4 for details on shift out data timing.
DS30009622M-page 30
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
3.4
ID Location Programming
The ID locations are programmed much like the code memory. The ID registers are mapped in addresses, 200000h
through 200007h. These locations read out normally even after code protection.
Note:
The user only needs to fill the first 8 bytes of the write buffer in order to write the ID locations.
Table 3-8 demonstrates the code sequence required to write the ID locations.
In order to modify the ID locations, refer to the methodology described in Section 3.2.1 “Modifying Code Memory”.
As with code memory, the ID locations must be erased before being modified.
TABLE 3-8:
4-Bit
Command
WRITE ID SEQUENCE
Data Payload
Core Instruction
Step 1: Direct access to code memory and enable writes.
0000
0000
8E A6
9C A6
BSF
BCF
EECON1, EEPGD
EECON1, CFGS
Step 2: Load write buffer with 8 bytes and write.
0000
0000
0000
0000
0000
0000
1101
1101
1101
1111
0000
3.5
0E 20
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
<MSB><LSB>
00 00
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Write
Write
Write
Write
NOP -
20h
TBLPTRU
00h
TBLPTRH
00h
TBLPTRL
2 bytes and post-increment address by
2 bytes and post-increment address by
2 bytes and post-increment address by
2 bytes and start programming.
hold PGC high for time P9 and low for
2.
2.
2.
time P10.
Boot Block Programming
The code sequence detailed in Table 3-5 should be used, except that the address used in “Step 2” will be in the range
of 000000h to 0007FFh.
3.6
Configuration Bits Programming
Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit
command (‘1111’) is used, but only eight bits of the following 16-bit payload will be written. The LSB of the payload will be
written to even addresses and the MSB will be written to odd addresses. The code sequence to program two consecutive
configuration locations is shown in Table 3-9.
Note:
The address must be explicitly written for each byte programmed. The addresses can not be incremented
in this mode.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 31
PIC18F2XXX/4XXX FAMILY
TABLE 3-9:
SET ADDRESS POINTER TO CONFIGURATION LOCATION
4-Bit
Command
Data Payload
Core Instruction
Step 1: Enable writes and direct access to configuration memory.
0000
0000
8E A6
8C A6
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
Step 2: Set Table Pointer for configuration byte to be written. Write even/odd addresses.(1)
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
1111
0000
Note 1:
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<MSB ignored><LSB>
00 00
0E 01
6E F6
<MSB><LSB ignored>
00 00
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
MOVLW 01h
MOVWF TBLPTRL
Load 2 bytes and start programming.
NOP - hold PGC high for time P9 and low for time P10.
Enabling the write protection of Configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of the
Configuration bits. Always write all the Configuration bits before enabling the write protection for Configuration bits.
FIGURE 3-8:
DS30009622M-page 32
CONFIGURATION PROGRAMMING FLOW
Start
Start
Load Even
Configuration
Address
Load Odd
Configuration
Address
Program
LSB
Program
MSB
Delay P9 and P10
Time for Write
Delay P9 and P10
Time for Write
Done
Done
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
4.0
READING THE DEVICE
4.1
Read Code Memory, ID Locations and Configuration Bits
Code memory is accessed, one byte at a time, via the 4-bit command, ‘1001’ (Table Read, post-increment). The
contents of memory pointed to by the Table Pointer (TBLPTRU:TBLPTRH:TBLPTRL) are serially output on PGD.
The 4-bit command is shifted in, LSb first. The read is executed during the next eight clocks, then shifted out on PGD
during the last eight clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the
operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1).
This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read.
This technique will work to read any memory in the 000000h to 3FFFFFh address space, so it also applies to the reading
of the ID and Configuration registers.
TABLE 4-1:
READ CODE MEMORY SEQUENCE
4-Bit
Command
Data Payload
Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E
6E
0E
6E
0E
6E
<Addr[21:16]>
F8
<Addr[15:8]>
F7
<Addr[7:0]>
F6
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
Addr[21:16]
TBLPTRU
<Addr[15:8]>
TBLPTRH
<Addr[7:0]>
TBLPTRL
Step 2: Read memory and then shift out on PGD, LSb to MSb.
1001
00 00
FIGURE 4-1:
1
TBLRD *+
TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
2
3
4
1
2
3
4
5
6
7
9
8
10
11
12
13
14
15
1
16
2
3
4
PGC
P5
P5A
P6
P14
PGD
1
0
0
LSb 1
1
2
3
4
5
Shift Data Out
PGD = Input
 2010-2015 Microchip Technology Inc.
PGD = Output
6
MSb
n
n
n
n
Fetch Next 4-Bit Command
PGD = Input
DS30009622M-page 33
PIC18F2XXX/4XXX FAMILY
4.2
Verify Code Memory and ID Locations
The verify step involves reading back the code memory space and comparing it against the copy held in the
programmer’s buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the
word in the programmer’s buffer. Refer to Section 4.1 “Read Code Memory, ID Locations and Configuration Bits”
for implementation details of reading code memory.
The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been
verified. The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer
beyond the code memory space. In a 64-Kbyte device, for example, a post-increment read of address, FFFFh, will wrap
the Table Pointer back to 000000h, rather than point to the unimplemented address, 010000h.
FIGURE 4-2:
VERIFY CODE MEMORY FLOW
Start
Set TBLPTR = 0
Set TBLPTR = 200000h
Read Low Byte
with Post-Increment
Read Low Byte
with Post-Increment
Read High Byte
with Post-Increment
Does
Word = Expect
Data?
Increment
Pointer
No
Read High Byte
with Post-Increment
Does
Word = Expect
Data?
Failure,
Report
Error
Yes
No
All
code memory
verified?
Yes
No
Failure,
Report
Error
Yes
No
All
ID locations
verified?
Yes
Done
4.3
Verify Configuration Bits
A configuration address may be read and output on PGD via the 4-bit command, ‘1001’. Configuration data is read and
written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may
then be immediately compared to the appropriate configuration data in the programmer’s memory for verification. Refer
to Section 4.1 “Read Code Memory, ID Locations and Configuration Bits” for implementation details of reading
configuration data.
DS30009622M-page 34
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
4.4
Read Data EEPROM Memory
Data EEPROM is accessed, one byte at a time, via an Address Pointer (register pair: EEADRH:EEADR) and a data
latch (EEDATA). Data EEPROM is read by loading EEADRH:EEADR with the desired memory location and initiating a
memory read by appropriately configuring the EECON1 register. The data will be loaded into EEDATA, where it may be
serially output on PGD via the 4-bit command, ‘0010’ (Shift Out Data Holding register). A delay of P6 must be introduced
after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this
time, PGC must be held low (see Figure 4-4).
The command sequence to read a single byte of data is shown in Table 4-2.
FIGURE 4-3:
READ DATA EEPROM FLOW
Start
Set
Address
Read
Byte
Move to TABLAT
Shift Out Data
No
Done?
Yes
Done
TABLE 4-2:
READ DATA EEPROM MEMORY
4-Bit
Command
Data Payload
Core Instruction
Step 1: Direct access to data EEPROM.
0000
0000
9E A6
9C A6
BCF
BCF
EECON1, EEPGD
EECON1, CFGS
MOVLW
MOVWF
MOVLW
MOVWF
<Addr>
EEADR
<AddrH>
EEADRH
BSF
EECON1, RD
Step 2: Set the data EEPROM Address Pointer.
0000
0000
0000
0000
0E
6E
OE
6E
<Addr>
A9
<AddrH>
AA
Step 3: Initiate a memory read.
0000
80 A6
Step 4: Load data into the Serial Data Holding register.
0000
0000
0000
0010
Note 1:
50 A8
6E F5
00 00
<MSB><LSB>
MOVF
EEDATA, W, 0
MOVWF
TABLAT
NOP
Shift Out Data(1)
The <LSB> is undefined. The <MSB> is the data.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 35
PIC18F2XXX/4XXX FAMILY
FIGURE 4-4:
1
SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
2
3
4
1
2
3
4
5
6
7
9
8
10
11
12
13
14
15
16
1
2
3
4
PGC
P5
P5A
P6
P14
PGD
0
1
0
LSb 1
0
3
2
4
5
Shift Data Out
PGD = Input
4.5
PGD = Output
6
MSb
n
n
n
n
Fetch Next 4-Bit Command
PGD = Input
Verify Data EEPROM
A data EEPROM address may be read via a sequence of core instructions (4-bit command, ‘0000’) and then output on
PGD via the 4-bit command, ‘0010’ (TABLAT register). The result may then be immediately compared to the appropriate
data in the programmer’s memory for verification. Refer to Section 4.4 “Read Data EEPROM Memory” for
implementation details of reading data EEPROM.
4.6
Blank Check
The term Blank Check means to verify that the device has no programmed memory cells. All memories must be verified:
code memory, data EEPROM, ID locations and Configuration bits. The Device ID registers (3FFFFEh:3FFFFFh) should
be ignored.
A “blank” or “erased” memory cell will read as ‘1’. Therefore, Blank Checking a device merely means to verify that all bytes
read as FFh, except the Configuration bits. Unused (reserved) Configuration bits will read ‘0’ (programmed). Refer to
Figure 4-5 for blank configuration expect data for the various PIC18F2XXX/4XXX Family devices.
Given that Blank Checking is merely code and data EEPROM verification with FFh expect data, refer to Section 4.4 “Read
Data EEPROM Memory” and Section 4.2 “Verify Code Memory and ID Locations” for implementation details.
FIGURE 4-5:
BLANK CHECK FLOW
Start
Blank Check Device
Is
device
blank?
Yes
Continue
No
Abort
DS30009622M-page 36
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
5.0
CONFIGURATION WORD
The PIC18F2XXX/4XXX Family devices have several Configuration Words. These bits can be set or cleared to select
various device configurations. All other memory areas should be programmed and verified prior to setting the Configuration
Words. These bits may be read out normally, even after read or code protection. See Table 5-1 for a list of Configuration
bits and Device IDs, and Table 5-3 for the Configuration bit descriptions.
5.1
ID Locations
A user may store identification information (ID) in eight ID locations, mapped in 200000h:200007h. It is recommended
that the Most Significant nibble of each ID be Fh. In doing so, if the user code inadvertently tries to execute from the ID
space, the ID data will execute as a NOP.
5.2
Device ID Word
The Device ID Word for the PIC18F2XXX/4XXX Family devices is located at 3FFFFEh:3FFFFFh. These bits may be
used by the programmer to identify what device type is being programmed and read out normally, even after code or
read protection.
In some cases, devices may share the same DEVID values. In such cases, the Most Significant bit of the device revision,
REV4 (DEVID1<4>), will need to be examined to completely determine the device being accessed.
See Table 5-2 for a complete list of Device ID values.
FIGURE 5-1:
READ DEVICE ID WORD FLOW
Start
Set TBLPTR = 3FFFFE
Read Low Byte
with Post-Increment
Read High Byte
with Post-Increment
Done
 2010-2015 Microchip Technology Inc.
DS30009622M-page 37
PIC18F2XXX/4XXX FAMILY
TABLE 5-1:
CONFIGURATION BITS AND DEVICE IDS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h(1,8) CONFIG1L
—
—
USBDIV
CPUDIV1
CPUDIV0
PLLDIV2
PLLDIV1
PLLDIV0
300001h
CONFIG1H
IESO
FCMEN
300002h
CONFIG2L
—
—
300003h
CONFIG2H
—
—
300005h
CONFIG3H
MCLRE
—
300006h
CONFIG4L
DEBUG
XINST
—
—
FOSC3
FOSC2
FOSC1
FOSC0
BORV1
BORV0
BOREN1
BOREN0
PWRTEN
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
WDTEN
—
—
—
LPT1OSC
PBADEN
—
VREGEN(1,8)
CCP2MX(7)
—
Default/
Unprogrammed
Value
--00 0000
00-- 0111
00-- 0101(1,8)
---1 1111
--01 1111(1,8)
---1 1111
1--- -011(7)
1--- -01-
ICPRT(1)
—
—
100- -1-1(1)
BBSIZ1
BBSIZ0
—
1000 -1-1
—
BBSIZ(3)
—
ICPRT(8)
—
BBSIZ(8)
100- 01-1(8)
BBSIZ1(2)
BBSIZ2(2)
—
1000 -1-1(2)
LVP
—
STVREN
10-0 -1-1(3)
300008h
CONFIG5L
—
—
CP5(10)
CP4(9)
CP3(4)
CP2(4)
CP1
CP0
--11 1111
300009h
CONFIG5H
CPD
CPB
—
—
—
—
—
—
11-- ----
30000Ah
CONFIG6L
—
—
WRT5(10)
WRT4(9)
WRT3(4)
WRT2(4)
WRT1
WRT0
--11 1111
30000Bh
CONFIG6H
WRTD
WRTB
WRTC(5)
—
—
—
—
—
111- ----
30000Ch
CONFIG7L
—
—
EBTR5(10)
EBTR4(9)
EBTR3(4)
EBTR2(4)
EBTR1
EBTR0
--11 1111
30000Dh
CONFIG7H
—
EBTRB
—
—
—
—
—
—
-1-- ----
3FFFFEh
DEVID1(6)
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
See Table 5-2
3FFFFFh
DEVID2(6)
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
See Table 5-2
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
- = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Implemented only on PIC18F2455/2550/4455/4550 and PIC18F2458/2553/4458/4553 devices.
Implemented on PIC18F2585/2680/4585/4680, PIC18F2682/2685 and PIC18F4682/4685 devices only.
Implemented on PIC18F2480/2580/4480/4580 devices only.
These bits are only implemented on specific devices based on available memory. Refer to Section 2.3 “Memory Maps”.
In PIC18F2480/2580/4480/4580 devices, this bit is read-only in Normal Execution mode; it can be written only in Program mode.
DEVID registers are read-only and cannot be programmed by the user.
Implemented on all devices with the exception of the PIC18FXX8X and PIC18F2450/4450 devices.
Implemented on PIC18F2450/4450 devices only.
Implemented on PIC18F2682/2685 and PIC18F4682/4685 devices only.
Implemented on PIC18F2685/4685 devices only.
DS30009622M-page 38
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 5-2:
DEVICE ID VALUES
Device ID Value
Device
DEVID2
DEVID1
PIC18F2221
21h
011x xxxx
PIC18F2321
21h
001x xxxx
PIC18F2410
11h
011x xxxx
PIC18F2420
11h
010x xxxx(1)
PIC18F2423
11h
010x xxxx(2)
PIC18F2450
24h
001x xxxx
PIC18F2455
12h
011x xxxx
PIC18F2458
2Ah
011x xxxx
PIC18F2480
1Ah
111x xxxx
PIC18F2510
11h
001x xxxx
PIC18F2515
0Ch
111x xxxx
PIC18F2520
11h
000x xxxx(1)
PIC18F2523
11h
000x xxxx(2)
PIC18F2525
0Ch
110x xxxx
PIC18F2550
12h
010x xxxx
PIC18F2553
2Ah
010x xxxx
PIC18F2580
1Ah
110x xxxx
PIC18F2585
0Eh
111x xxxx
PIC18F2610
0Ch
101x xxxx
PIC18F2620
0Ch
100x xxxx
PIC18F2680
0Eh
110x xxxx
PIC18F2682
27h
000x xxxx
PIC18F2685
27h
001x xxxx
PIC18F4221
21h
010x xxxx
PIC18F4321
21h
000x xxxx
PIC18F4410
10h
111x xxxx
PIC18F4420
10h
110x xxxx(1)
PIC18F4423
10h
110x xxxx(2)
PIC18F4450
24h
000x xxxx
PIC18F4455
12h
001x xxxx
PIC18F4458
2Ah
001x xxxx
PIC18F4480
1Ah
101x xxxx
PIC18F4510
10h
101x xxxx
PIC18F4515
0Ch
011x xxxx
PIC18F4520
10h
100x xxxx(1)
PIC18F4523
10h
100x xxxx(2)
PIC18F4525
0Ch
010x xxxx
PIC18F4550
12h
000x xxxx
PIC18F4553
2Ah
000x xxxx
PIC18F4580
1Ah
100x xxxx
Legend: The ‘x’s in DEVID1 contain the device revision code.
Note 1: DEVID1 bit 4 is used to determine the device type (REV4 = 0).
2: DEVID1 bit 4 is used to determine the device type (REV4 = 1).
 2010-2015 Microchip Technology Inc.
DS30009622M-page 39
PIC18F2XXX/4XXX FAMILY
TABLE 5-2:
DEVICE ID VALUES (CONTINUED)
Device ID Value
Device
DEVID2
DEVID1
PIC18F4585
0Eh
101x xxxx
PIC18F4610
0Ch
001x xxxx
PIC18F4620
0Ch
000x xxxx
PIC18F4680
0Eh
100x xxxx
PIC18F4682
27h
010x xxxx
PIC18F4685
27h
011x xxxx
Legend: The ‘x’s in DEVID1 contain the device revision code.
Note 1: DEVID1 bit 4 is used to determine the device type (REV4 = 0).
2: DEVID1 bit 4 is used to determine the device type (REV4 = 1).
DS30009622M-page 40
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 5-3:
Bit Name
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS
Configuration
Words
Description
IESO
CONFIG1H
Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
FCMEN
CONFIG1H
Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
FOSC<3:0>
CONFIG1H
Oscillator Selection bits
11xx = External RC oscillator, CLKO function on RA6
101x = External RC oscillator, CLKO function on RA6
1001 = Internal RC oscillator, CLKO function on RA6, port function on RA7
1000 = Internal RC oscillator, port function on RA6, port function on RA7
0111 = External RC oscillator, port function on RA6
0110 = HS oscillator, PLL is enabled (Clock Frequency = 4 x FOSC1)
0101 = EC oscillator, port function on RA6
0100 = EC oscillator, CLKO function on RA6
0011 = External RC oscillator, CLKO function on RA6
0010 = HS oscillator
0001 = XT oscillator
0000 = LP oscillator
FOSC<3:0>
CONFIG1H
Oscillator Selection bits 
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
111x = HS oscillator, PLL is enabled, HS is used by USB
110x = HS oscillator, HS is used by USB
1011 = Internal oscillator, HS is used by USB
1010 = Internal oscillator, XT is used by USB
1001 = Internal oscillator, CLKO function on RA6, EC is used by USB
1000 = Internal oscillator, port function on RA6, EC is used by USB
0111 = EC oscillator, PLL is enabled, CLKO function on RA6, EC is used by USB
0110 = EC oscillator, PLL is enabled, port function on RA6, EC is used by USB
0101 = EC oscillator, CLKO function on RA6, EC is used by USB
0100 = EC oscillator, port function on RA6, EC is used by USB
001x = XT oscillator, PLL is enabled, XT is used by USB
000x = XT oscillator, XT is used by USB
USBDIV
CONFIG1L
USB Clock Selection bit 
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Selects the clock source for full-speed USB operation:
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the OSC1/OSC2 oscillator block; 
no divide
CPUDIV<1:0>
CONFIG1L
CPU System Clock Selection bits 
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
11 = CPU system clock divided by 4
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide
Note 1:
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 41
PIC18F2XXX/4XXX FAMILY
TABLE 5-3:
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
PLLDIV<2:0>
CONFIG1L
Oscillator Selection bits 
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL:
111 = Oscillator divided by 12 (48 MHz input)
110 = Oscillator divided by 10 (40 MHz input)
101 = Oscillator divided by 6 (24 MHz input)
100 = Oscillator divided by 5 (20 MHz input)
011 = Oscillator divided by 4 (16 MHz input)
010 = Oscillator divided by 3 (12 MHz input)
001 = Oscillator divided by 2 (8 MHz input)
000 = No divide – oscillator used directly (4 MHz input)
VREGEN
CONFIG2L
USB Voltage Regulator Enable bit 
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
1 = USB voltage regulator is enabled
0 = USB voltage regulator is disabled
BORV<1:0>
CONFIG2L
Brown-out Reset Voltage bits
11 = VBOR is set to 2.0V
10 = VBOR is set to 2.7V
01 = VBOR is set to 4.2V
00 = VBOR is set to 4.5V
BOREN<1:0>
CONFIG2L
Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode
SBOREN is disabled)
01 = Brown-out Reset is enabled and controlled by software (SBOREN is
enabled)
00 = Brown-out Reset is disabled in hardware and software
PWRTEN
CONFIG2L
Power-up Timer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
WDPS<3:0>
CONFIG2H
Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
Note 1:
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
DS30009622M-page 42
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 5-3:
Bit Name
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Configuration
Words
Description
WDTEN
CONFIG2H
Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)
MCLRE
CONFIG3H
MCLR Pin Enable bit
1 = MCLR pin is enabled, RE3 input pin is disabled
0 = RE3 input pin is enabled, MCLR pin is disabled
LPT1OSC
CONFIG3H
Low-Power Timer1 Oscillator Enable bit
1 = Timer1 is configured for low-power operation
0 = Timer1 is configured for high-power operation
PBADEN
CONFIG3H
PORTB A/D Enable bit
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
PBADEN
CONFIG3H
PORTB A/D Enable bit (PIC18FXX8X devices only)
1 = PORTB A/D<4:0> and PORTB A/D<1:0> pins are configured as analog input 
channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2MX
CONFIG3H
CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1(2)
0 = CCP2 input/output is multiplexed with RB3
DEBUG
CONFIG4L
Background Debugger Enable bit
1 = Background debugger is disabled, RB6 and RB7 are configured as general 
purpose I/O pins
0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit 
Debug
XINST
CONFIG4L
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled 
(Legacy mode)
ICPRT
CONFIG4L
Dedicated In-Circuit (ICD/ICSP™) Port Enable bit 
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
1 = ICPORT is enabled
0 = ICPORT is disabled
BBSIZ<1:0>(1)
CONFIG4L
Boot Block Size Select bits (PIC18F2585/2680/4585/4680 devices only)
11 = 4K words (8 Kbytes) Boot Block
10 = 4K words (8 Kbytes) Boot Block
01 = 2K words (4 Kbytes) Boot Block
00 = 1K word (2 Kbytes) Boot Block
BBSIZ<2:1>(1)
CONFIG4L
Boot Block Size Select bits (PIC18F2682/2685/4582/4685 devices only)
11 = 4K words (8 Kbytes) Boot Block
10 = 4K words (8 Kbytes) Boot Block
01 = 2K words (4 Kbytes) Boot Block
00 = 1K word (2 Kbytes) Boot Block
Note 1:
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 43
PIC18F2XXX/4XXX FAMILY
TABLE 5-3:
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name
BBSIZ<1:0>(1)
Configuration
Words
CONFIG4L
Description
Boot Block Size Select bits (PIC18F2321/4321 devices only)
11 = 1K word (2 Kbytes) Boot Block
10 = 1K word (2 Kbytes) Boot Block
01 = 512 words (1 Kbyte) Boot Block
00 = 256 words (512 bytes) Boot Block
Boot Block Size Select bits (PIC18F2221/4221 devices only)
11 = 512 words (1 Kbyte) Boot Block
10 = 512 words (1 Kbyte) Boot Block
01 = 512 words (1 Kbyte) Boot Block
00 = 256 words (512 bytes) Boot Block
BBSIZ(1)
CONFIG4L
Boot Block Size Select bits 
(PIC18F2480/2580/4480/4580 and PIC18F2450/4450 devices only)
1 = 2K words (4 Kbytes) Boot Block
0 = 1K word (2 Kbytes) Boot Block
LVP
CONFIG4L
Low-Voltage Programming Enable bit
1 = Low-Voltage Programming is enabled, RB5 is the PGM pin
0 = Low-Voltage Programming is disabled, RB5 is an I/O pin
STVREN
CONFIG4L
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
CP5
CONFIG5L
Code Protection bit (Block 5 code memory area) 
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not code-protected
0 = Block 5 is code-protected
CP4
CONFIG5L
Code Protection bit (Block 4 code memory area) 
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not code-protected
0 = Block 4 is code-protected
CP3
CONFIG5L
Code Protection bit (Block 3 code memory area)
1 = Block 3 is not code-protected
0 = Block 3 is code-protected
CP2
CONFIG5L
Code Protection bit (Block 2 code memory area)
1 = Block 2 is not code-protected
0 = Block 2 is code-protected
CP1
CONFIG5L
Code Protection bit (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
CP0
CONFIG5L
Code Protection bit (Block 0 code memory area)
1 = Block 0 is not code-protected
0 = Block 0 is code-protected
CPD
CONFIG5H
Code Protection bit (Data EEPROM)
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CPB
CONFIG5H
Code Protection bit (Boot Block memory area)
1 = Boot Block is not code-protected
0 = Boot Block is code-protected
Note 1:
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
DS30009622M-page 44
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 5-3:
Bit Name
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Configuration
Words
Description
WRT5
CONFIG6L
Write Protection bit (Block 5 code memory area) 
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not write-protected
0 = Block 5 is write-protected
WRT4
CONFIG6L
Write Protection bit (Block 4 code memory area) 
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not write-protected
0 = Block 4 is write-protected
WRT3
CONFIG6L
Write Protection bit (Block 3 code memory area)
1 = Block 3 is not write-protected
0 = Block 3 is write-protected
WRT2
CONFIG6L
Write Protection bit (Block 2 code memory area)
1 = Block 2 is not write-protected
0 = Block 2 is write-protected
WRT1
CONFIG6L
Write Protection bit (Block 1 code memory area)
1 = Block 1 is not write-protected
0 = Block 1 is write-protected
WRT0
CONFIG6L
Write Protection bit (Block 0 code memory area)
1 = Block 0 is not write-protected
0 = Block 0 is write-protected
WRTD
CONFIG6H
Write Protection bit (Data EEPROM)
1 = Data EEPROM is not write-protected
0 = Data EEPROM is write-protected
WRTB
CONFIG6H
Write Protection bit (Boot Block memory area)
1 = Boot Block is not write-protected
0 = Boot Block is write-protected
WRTC
CONFIG6H
Write Protection bit (Configuration registers)
1 = Configuration registers are not write-protected
0 = Configuration registers are write-protected
EBTR5
CONFIG7L
Table Read Protection bit (Block 5 code memory area) 
(PIC18F2685 and PIC18F4685 devices only)
1 = Block 5 is not protected from Table Reads executed in other blocks
0 = Block 5 is protected from Table Reads executed in other blocks
EBTR4
CONFIG7L
Table Read Protection bit (Block 4 code memory area) 
(PIC18F2682/2685 and PIC18F4682/4685 devices only)
1 = Block 4 is not protected from Table Reads executed in other blocks
0 = Block 4 is protected from Table Reads executed in other blocks
EBTR3
CONFIG7L
Table Read Protection bit (Block 3 code memory area)
1 = Block 3 is not protected from Table Reads executed in other blocks
0 = Block 3 is protected from Table Reads executed in other blocks
EBTR2
CONFIG7L
Table Read Protection bit (Block 2 code memory area)
1 = Block 2 is not protected from Table Reads executed in other blocks
0 = Block 2 is protected from Table Reads executed in other blocks
EBTR1
CONFIG7L
Table Read Protection bit (Block 1 code memory area)
1 = Block 1 is not protected from Table Reads executed in other blocks
0 = Block 1 is protected from Table Reads executed in other blocks
Note 1:
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 45
PIC18F2XXX/4XXX FAMILY
TABLE 5-3:
PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
EBTR0
CONFIG7L
Table Read Protection bit (Block 0 code memory area)
1 = Block 0 is not protected from Table Reads executed in other blocks
0 = Block 0 is protected from Table Reads executed in other blocks
EBTRB
CONFIG7H
Table Read Protection bit (Boot Block memory area)
1 = Boot Block is not protected from Table Reads executed in other blocks
0 = Boot Block is protected from Table Reads executed in other blocks
DEV<10:3>
DEVID2
Device ID bits
These bits are used with the DEV<2:0> bits in the DEVID1 register to identify
part number.
DEV<2:0>
DEVID1
Device ID bits
These bits are used with the DEV<10:3> bits in the DEVID2 register to identify
part number.
REV<4:0>
DEVID1
Revision ID bits
These bits are used to indicate the revision of the device. The REV4 bit is 
sometimes used to fully specify the device type.
Note 1:
2:
The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
Not available in PIC18FXX8X and PIC18F2450/4450 devices.
DS30009622M-page 46
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
5.3
Single-Supply ICSP Programming
The LVP bit in Configuration register, CONFIG4L, enables Single-Supply (Low-Voltage) ICSP Programming. The LVP
bit defaults to a ‘1’ (enabled) from the factory.
If Single-Supply Programming mode is not used, the LVP bit can be programmed to a ‘0’ and RB5/PGM becomes a digital
I/O pin. However, the LVP bit may only be programmed by entering the High-Voltage ICSP mode, where MCLR/VPP/RE3
is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is available and only the
High-Voltage ICSP mode can be used to program the device.
Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying
VIHH to the MCLR/V PP/RE3 pin.
2: While in Low-Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O.
5.4
Embedding Configuration Word Information in the HEX File
To allow portability of code, a PIC18F2XXX/4XXX Family programmer is required to read the Configuration Word
locations from the hex file. If Configuration Word information is not present in the hex file, then a simple warning
message should be issued. Similarly, while saving a hex file, all Configuration Word information must be included. An
option to not include the Configuration Word information may be provided. When embedding Configuration Word
information in the hex file, it should start at address, 300000h.
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
5.5
Embedding Data EEPROM Information In the HEX File
To allow portability of code, a PIC18F2XXX/4XXX Family programmer is required to read the data EEPROM
information from the hex file. If data EEPROM information is not present, a simple warning message should be issued.
Similarly, when saving a hex file, all data EEPROM information must be included. An option to not include the data
EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at
address, F00000h.
Microchip Technology Inc. believes that this feature is important for the benefit of the end customer.
5.6
Checksum Computation
The checksum is calculated by summing the following:
• The contents of all code memory locations
• The Configuration Words, appropriately masked
• ID locations (if any block is code-protected)
The Least Significant 16 bits of this sum is the checksum. The contents of the data EEPROM are not used.
5.6.1
PROGRAM MEMORY
When program memory contents are summed, each 16-bit word is added to the checksum. The contents of program
memory, from 000000h to the end of the last program memory block, are used for this calculation. Overflows from bit
15 may be ignored.
5.6.2
CONFIGURATION WORDS
For checksum calculations, unimplemented bits in Configuration Words should be ignored as such bits always read
back as ‘1’s. Each 8-bit Configuration Word is ANDed with a corresponding mask to prevent unused bits from affecting
checksum calculations.
The mask contains a ‘0’ in unimplemented bit positions, or a ‘1’ where a choice can be made. When ANDed with the
value read out of a Configuration Word, only implemented bits remain. A list of suitable masks is provided in Table 5-5.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 47
PIC18F2XXX/4XXX FAMILY
5.6.3
ID LOCATIONS
Normally, the contents of these locations are defined by the user, but MPLAB® IDE provides the option of writing the
device’s unprotected 16-bit checksum in the 16 Most Significant bits of the ID locations (see MPLAB IDE Configure/ID
Memory” menu). The lower 16 bits are not used and remain clear. This is the sum of all program memory contents and
Configuration Words (appropriately masked) before any code protection is enabled.
If the user elects to define the contents of the ID locations, nothing about protected blocks can be known. If the user
uses the preprotected checksum, provided by MPLAB IDE, an indirect characteristic of the programmed code is
provided.
5.6.4
CODE PROTECTION
Blocks that are code-protected read back as all ‘0’s and have no effect on checksum calculations. If any block is
code-protected, then the contents of the ID locations are included in the checksum calculation.
All Configuration Words and the ID locations can always be read out normally, even when the device is fully
code-protected. Checking the code protection settings in Configuration Words can direct which, if any, of the program
memory blocks can be read, and if the ID locations should be used for checksum calculations.
DS30009622M-page 48
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 5-4:
Device
DEVICE BLOCK LOCATIONS AND SIZES
Memory
Size
Pins
(Bytes)
PIC18F2221
4K
28
PIC18F2321
8K
28
Ending Address
Boot
Block
0001FF
Size (Bytes)
Block 0 Block 1 Block 2 Block 3 Block 4 Block 5
0007FF 000FFF
—
—
—
—
0003FF 000FFF 001FFF
—
—
—
—
0003FF
0001FF
0007FF
Boot
Block
Block 0
512
1536
1024
1024
512
3584
1024
3072
2048
2048
Remaining Device
Blocks
Total
2048
4096
4096
8192
PIC18F2410
16K
28
0007FF 001FFF 003FFF
—
—
—
—
2048
6144
8192
16384
PIC18F2420
16K
28
0007FF 001FFF 003FFF
—
—
—
—
2048
6144
8192
16384
PIC18F2423
16K
28
0007FF 001FFF 003FFF
—
—
—
—
2048
6144
8192
16384
2048
6144
4096
4096
8192
16384
PIC18F2450
16K
28
PIC18F2455
24K
28
PIC18F2458
24K
28
PIC18F2480
16K
28
PIC18F2510
32K
28
PIC18F2515
48K
PIC18F2520
32K
PIC18F2523
0007FF
—
—
—
0007FF 001FFF 003FFF 005FFF
—
—
—
2048
6144
16384
24576
0007FF 001FFF 003FFF 005FFF
—
—
—
2048
6144
16384
24576
2048
6144
4096
4096
8192
16384
000FFF
0007FF
001FFF 003FFF
—
—
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
6144
24576
32768
28
0007FF 003FFF 007FFF 00BFFF
—
—
2048
14336
32768
49152
28
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
14336
16384
32768
32K
28
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
14336
16384
32768
PIC18F2525
48K
28
0007FF 003FFF 007FFF 00BFFF
—
—
2048
14336
32768
49152
PIC18F2550
32K
28
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
6144
24576
32768
PIC18F2553
32K
28
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
6144
24576
32768
2048
6144
4096
4096
24576
32768
2048
14336
4096
12288
32768
49152
8192
8192
PIC18F2580
32K
28
000FFF
0007FF
000FFF
001FFF 003FFF
—
—
—
—
—
001FFF 003FFF 005FFF 007FFF
—
—
0007FF
PIC18F2585
48K
28
000FFF 003FFF 007FFF 00BFFF
—
—
—
001FFF
PIC18F2610
64K
28
0007FF 003FFF 007FFF 00BFFF 00FFFF
—
—
2048
14336
49152
65536
PIC18F2620
64K
28
0007FF 003FFF 007FFF 00BFFF 00FFFF
—
—
2048
14336
49152
65536
2048
14336
4096
12288
49152
65536
8192
8192
2048
14336
4096
12288
65536
81920
001FFF
8192
8192
81920
98304
2048
4096
4096
8192
0007FF
PIC18F2680
64K
28
000FFF 003FFF 007FFF 00BFFF 00FFFF
—
—
001FFF
0007FF
PIC18F2682
PIC18F2685
80K
96K
28
28
PIC18F4221
4K
40
PIC18F4321
8K
40
000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF
—
0007FF
2048
14336
000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF
4096
12288
001FFF
8192
8192
0001FF
0007FF 000FFF
—
—
—
—
0003FF 000FFF 001FFF
—
—
—
—
0003FF
0001FF
0007FF
512
1536
1024
1024
512
3584
1024
3072
2048
2048
PIC18F4410
16K
40
0007FF 001FFF 003FFF
—
—
—
—
2048
6144
8192
16384
PIC18F4420
16K
40
0007FF 001FFF 003FFF
—
—
—
—
2048
6144
8192
16384
PIC18F4423
16K
40
0007FF 001FFF 003FFF
—
—
—
—
2048
6144
8192
16384
2048
6144
4096
4096
8192
16384
PIC18F4450
Legend:
16K
40
0007FF
000FFF
001FFF 003FFF
—
—
—
—
— = unimplemented.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 49
PIC18F2XXX/4XXX FAMILY
TABLE 5-4:
Device
DEVICE BLOCK LOCATIONS AND SIZES (CONTINUED)
Memory
Size
Pins
(Bytes)
Ending Address
Boot
Block
Size (Bytes)
Block 0 Block 1 Block 2 Block 3 Block 4 Block 5
Boot
Block
Block 0
Remaining Device
Blocks
Total
PIC18F4455
24K
40
0007FF 001FFF 003FFF 005FFF
—
—
—
2048
6144
16384
24576
PIC18F4458
24K
40
0007FF 001FFF 003FFF 005FFF
—
—
—
2048
6144
16384
24576
2048
6144
4096
4096
8192
16384
PIC18F4480
16K
40
PIC18F4510
32K
40
PIC18F4515
48K
40
PIC18F4520
32K
40
PIC18F4523
32K
PIC18F4525
0007FF
—
—
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
6144
24576
32768
0007FF 003FFF 007FFF 00BFFF
—
—
2048
14336
32768
49152
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
14336
16384
32768
40
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
14336
16384
32768
48K
40
0007FF 003FFF 007FFF 00BFFF
—
—
2048
14336
32768
49152
PIC18F4550
32K
40
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
6144
24576
32768
PIC18F4553
32K
40
0007FF 001FFF 003FFF 005FFF 007FFF
—
—
2048
6144
24576
32768
PIC18F4580
32K
40
—
—
2048
6144
4096
4096
24576
32768
2048
14336
PIC18F4585
48K
40
—
—
4096
12288
32768
49152
8192
8192
000FFF
0007FF
000FFF
001FFF 003FFF
—
—
—
—
001FFF 003FFF 005FFF 007FFF
0007FF
000FFF 003FFF 007FFF 00BFFF
—
001FFF
PIC18F4610
64K
40
0007FF 003FFF 007FFF 00BFFF 00FFFF
—
—
2048
14336
49152
65536
PIC18F4620
64K
40
0007FF 003FFF 007FFF 00BFFF 00FFFF
—
—
2048
14336
49152
65536
2048
14336
4096
12288
49152
65536
8192
8192
2048
14336
4096
12288
65536
81920
001FFF
8192
8192
81920
98304
0007FF
PIC18F4680
64K
40
000FFF 003FFF 007FFF 00BFFF 00FFFF
—
—
001FFF
0007FF
PIC18F4682
PIC18F4685
Legend:
80K
96K
40
44
000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF
—
0007FF
2048
14336
000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF
4096
12288
001FFF
8192
8192
— = unimplemented.
DS30009622M-page 50
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
TABLE 5-5:
CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS
Configuration Word (CONFIGxx)
1L
Device
1H
2L
2H
3L
3H
4L
4H
5L
5H
6L
6H
7L
7H
Address (30000xh)
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
PIC18F2221
00
CF
1F
1F
00
87
F5
00
03
C0
03
E0
03
40
PIC18F2321
00
CF
1F
1F
00
87
F5
00
03
C0
03
E0
03
40
PIC18F2410
00
CF
1F
1F
00
87
C5
00
03
C0
03
E0
03
40
PIC18F2420
00
CF
1F
1F
00
87
C5
00
03
C0
03
E0
03
40
PIC18F2423
00
CF
1F
1F
00
87
C5
00
03
C0
03
E0
03
40
PIC18F2450
3F
CF
3F
1F
00
86
ED
00
03
40
03
60
03
40
PIC18F2455
3F
CF
3F
1F
00
87
E5
00
07
C0
07
E0
07
40
PIC18F2458
3F
CF
3F
1F
00
87
E5
00
07
C0
07
E0
07
40
PIC18F2480
00
CF
1F
1F
00
86
D5
00
03
C0
03
E0
03
40
PIC18F2510
00
1F
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2515
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2520
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2523
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2525
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2550
3F
CF
3F
1F
00
87
E5
00
0F
C0
0F
E0
0F
40
PIC18F2553
3F
CF
3F
1F
00
87
E5
00
0F
C0
0F
E0
0F
40
PIC18F2580
00
CF
1F
1F
00
86
D5
00
0F
C0
0F
E0
0F
40
PIC18F2585
00
CF
1F
1F
00
86
C5
00
0F
C0
0F
E0
0F
40
PIC18F2610
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2620
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F2680
00
CF
1F
1F
00
86
C5
00
0F
C0
0F
E0
0F
40
PIC18F2682
00
CF
1F
1F
00
86
C5
00
3F
C0
3F
E0
3F
40
PIC18F2685
00
CF
1F
1F
00
86
C5
00
3F
C0
3F
E0
3F
40
PIC18F4221
00
CF
1F
1F
00
87
F5
00
03
C0
03
E0
03
40
PIC18F4321
00
CF
1F
1F
00
87
F5
00
03
C0
03
E0
03
40
PIC18F4410
00
CF
1F
1F
00
87
C5
00
03
C0
03
E0
03
40
PIC18F4420
00
CF
1F
1F
00
87
C5
00
03
C0
03
E0
03
40
PIC18F4423
00
CF
1F
1F
00
87
C5
00
03
C0
03
E0
03
40
PIC18F4450
3F
CF
3F
1F
00
86
ED
00
03
40
03
60
03
40
PIC18F4455
3F
CF
3F
1F
00
87
E5
00
07
C0
07
E0
07
40
PIC18F4458
3F
CF
3F
1F
00
87
E5
00
07
C0
07
E0
07
40
PIC18F4480
00
CF
1F
1F
00
86
D5
00
03
C0
03
E0
03
40
PIC18F4510
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F4515
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F4520
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F4523
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F4525
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F4550
3F
CF
3F
1F
00
87
E5
00
0F
C0
0F
E0
0F
40
PIC18F4553
3F
CF
3F
1F
00
87
E5
00
0F
C0
0F
E0
0F
40
PIC18F4580
00
CF
1F
1F
00
86
D5
00
0F
C0
0F
E0
0F
40
PIC18F4585
00
CF
1F
1F
00
86
C5
00
0F
C0
0F
E0
0F
40
PIC18F4610
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
Legend:
Shaded cells are unimplemented.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 51
PIC18F2XXX/4XXX FAMILY
TABLE 5-5:
CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS (CONTINUED)
Configuration Word (CONFIGxx)
1L
Device
1H
2L
2H
3L
3H
4L
4H
5L
5H
6L
6H
7L
7H
Address (30000xh)
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
PIC18F4620
00
CF
1F
1F
00
87
C5
00
0F
C0
0F
E0
0F
40
PIC18F4680
00
CF
1F
1F
00
86
C5
00
0F
C0
0F
E0
0F
40
PIC18F4682
00
CF
1F
1F
00
86
C5
00
3F
C0
3F
E0
3F
40
PIC18F4685
00
CF
1F
1F
00
86
C5
00
3F
C0
3F
E0
3F
40
Legend:
Shaded cells are unimplemented.
DS30009622M-page 52
 2010-2015 Microchip Technology Inc.
PIC18F2XXX/4XXX FAMILY
AC/DC CHARACTERISTICS TIMING REQUIREMENTS 
FOR PROGRAM/VERIFY TEST MODE
6.0
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Sym
Characteristic
Min
Max
Units
Conditions
VIHH
High-Voltage Programming Voltage on 
MCLR/VPP/RE3
VDD + 4.0
12.5
V
(Note 2)
D110A VIHL
Low-Voltage Programming Voltage on 
MCLR/VPP/RE3
2.00
5.50
V
(Note 2)
D111
Supply Voltage During Programming
2.00
5.50
V
Externally timed,
Row Erases and all writes
3.0
5.50
V
Self-timed,
Bulk Erases only (Note 3)
(Note 2)
D110
VDD
D112
IPP
Programming Current on MCLR/VPP/RE3
—
300
A
D113
IDDP
Supply Current During Programming
—
10
mA
D031
VIL
Input Low Voltage
VSS
0.2 VDD
V
D041
VIH
Input High Voltage
0.8 VDD
VDD
V
D080
VOL
Output Low Voltage
—
0.6
V
D090
VOH
Output High Voltage
VDD – 0.7
—
V
IOH = -3.0 mA @ 4.5V
D012
CIO
Capacitive Loading on I/O pin (PGD)
—
50
pF
To meet AC specifications
P1
TR
MCLR/VPP/RE3 Rise Time to Enter 
Program/Verify mode
—
1.0
s
(Notes 1, 2)
P2
TPGC
Serial Clock (PGC) Period
100
—
ns
VDD = 5.0V
P2A
TPGCL Serial Clock (PGC) Low Time
P2B
TPGCH Serial Clock (PGC) High Time
1
—
s
VDD = 2.0V
40
—
ns
VDD = 5.0V
400
—
ns
VDD = 2.0V
40
—
ns
VDD = 5.0V
400
—
ns
VDD = 2.0V
15
—
ns
P3
TSET1 Input Data Setup Time to Serial Clock 
P4
THLD1 Input Data Hold Time from PGC
15
—
ns
P5
TDLY1 Delay Between 4-Bit Command and Command
Operand
40
—
ns
P5A
TDLY1A Delay Between 4-Bit Command Operand and
Next 4-Bit Command
40
—
ns
P6
TDLY2 Delay Between Last PGC  of Command Byte to
First PGC  of Read of Data Word
20
—
ns
P9
TDLY5 PGC High Time (minimum programming time)
1
—
ms
P10
TDLY6 PGC Low Time After Programming
(high-voltage discharge time)
100
—
s
P11
TDLY7 Delay to Allow Self-Timed Data Write or 
Bulk Erase to Occur
5
—
ms
Note 1:
2:
3:
IOL = 8.5 mA @ 4.5V
Externally timed
Do not allow excess time when transitioning MCLR between VIL and VIHH. This can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For
specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.
When ICPRT = 1, this specification also applies to ICVPP.
At 0°C-50°C.
 2010-2015 Microchip Technology Inc.
DS30009622M-page 53
PIC18F2XXX/4XXX FAMILY
AC/DC CHARACTERISTICS TIMING REQUIREMENTS 
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
6.0
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Sym
Characteristic
Min
Max
Units
4
—
ms
P11A
TDRWT Data Write Polling Time
P12
THLD2 Input Data Hold Time from MCLR/VPP/RE3 
2
—
s
P13
TSET2 VDD Setup Time to MCLR/VPP/RE3 
100
—
ns
P14
TVALID Data Out Valid from PGC 
10
—
ns
P15
TSET3 PGM Setup Time to MCLR/VPP/RE3 
2
—
s
P16
TDLY8 Delay Between Last PGC  and MCLR/VPP/RE3 
0
—
s
P17
THLD3 MCLR/VPP/RE3 to VDD 
—
100
ns
P18
THLD4 MCLR/VPP/RE3 to PGM 
0
—
s
Note 1:
2:
3:
Conditions
(Note 2)
(Note 2)
Do not allow excess time when transitioning MCLR between VIL and VIHH. This can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For
specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.
When ICPRT = 1, this specification also applies to ICVPP.
At 0°C-50°C.
DS30009622M-page 54
 2010-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-856-7
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2010-2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS30009622M-page 55
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
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Technical Support:
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Web Address:
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Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS30009622M-page 56
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