Si2302CDS Datasheet

Si2302CDS
Vishay Siliconix
N-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
20
RDS(on) ()
ID (A)
0.057 at VGS = 4.5 V
2.9
0.075 at VGS = 2.5 V
2.6
Qg (Typ.)
3.5
• TrenchFET® Power MOSFET
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
APPLICATIONS
• Load Switching for Portable Devices
• DC/DC Converter
TO-236
(SOT-23)
G
1
3
S
D
2
Top View
Si2302CDS (N2)*
* Marking Code
Ordering Information: Si2302CDS-T1-E3 (Lead (Pb)-free)
Si2302CDS-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
5s
Steady State
Drain-Source Voltage
VDS
20
Gate-Source Voltage
VGS
±8
Continuous Drain Current (TJ = 150 °C)a
TA = 25 °C
TA = 70 °C
Pulsed Drain Currentb
ID
IS
TA = 25 °C
Power Dissipationa
TA = 70 °C
PD
2.6
2.3
2.1
10
0.72
0.6
0.86
0.71
0.55
0.46
TJ, Tstg
Operating Junction and Storage Temperature Range
V
2.9
IDM
Continuous Source Current (Diode Conduction)a
Unit
- 55 to 150
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Symbol
t5s
Maximum Junction-to-Ambienta
Steady State
Maximum Junction-to-Foot
Steady State
RthJA
RthJF
Typical
Maximum
120
145
140
175
62
78
Unit
°C/W
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Pulse width limited by maximum junction temperature.
Document Number: 68645
S12-2336-Rev. D, 01-Oct-12
For technical questions, contact: [email protected]
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2302CDS
Vishay Siliconix
SPECIFICATIONS (TA = 25 °C, unless otherwise noted)
Limits
Parameter
Symbol
Test Conditions
Min.
Typ.
Unit
Max.
Static
Drain-Source Breakdown Voltage
Gate-Threshold Voltage
Gate-Body Leakage
VDS
VGS = 0 V, ID = 250 µA
20
VGS(th)
VDS = VGS, ID = 250 µA
0.40
IGSS
VDS = 0 V, VGS = ± 8 V
± 100
VDS = 20 V, VGS = 0 V
0.1
VDS = 20 V, VGS = 0 V, TJ = 50 °C
4
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
VDS = 20 V, VGS = 0 V, TJ = 70 °C
Drain-Source On-Resistancea
Diode Forward Voltage
µA
6
A
VGS = 4.5 V, ID = 3.6 A
0.045
0.057
VGS = 2.5 V, ID = 3.1 A
0.056
0.075
gfs
VDS = 5 V, ID = 3.6 A
13
VSD
IS = 0.95 A, VGS = 0 V
0.7
1.2
3.5
5.5
Forward Transconductancea
nA
15
VDS 10 V, VGS = 4.5 V
RDS(on)
V
0.85

S
V
b
Dynamic
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
VDS = 10 V, VGS = 4.5 V, ID = 3.6 A
nC
0.6
0.45
f = 1 MHz
2
4
8
8
15
7
15

Switching
td(on)
Turn-On Delay Time
VDD = 10 V, RL = 2.78 
ID  3.6 A, VGEN = 4.5 V, Rg = 1 
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Source-Drain Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
IF = 3.6 A, dI/dt = 100 A/µs
30
45
7
15
8.5
15
2
4
ns
nC
Notes:
a. Pulse test: Pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10
10
VGS = 5 V thru 2 V
8
VGS = 1.5 V
I D - Drain Current (A)
I D - Drain Current (A)
8
6
4
2
6
4
TC = 25 °C
2
VGS = 1 V
TC = 125 °C
TC = - 55 °C
0
0.0
0.5
1.0
1.5
VDS - Drain-to-Source Voltage (V)
Output Characteristics
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2
2.0
0
0.0
0.4
0.8
1.2
1.6
2.0
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
For technical questions, contact: [email protected]
Document Number: 68645
S12-2336-Rev. D, 01-Oct-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2302CDS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.07
2.0
R DS(on) - On-Resistance (Ω)
I D - Drain Current (A)
1.6
1.2
0.8
TC = 25 °C
0.4
0.06
VGS = 2.5 V
0.05
VGS = 4.5 V
0.04
TC = 125 °C
TC = - 55 °C
0.0
0.0
0.3
0.6
0.9
1.2
0.03
0
1.5
2
4
6
ID - Drain Current (A)
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
10
On-Resistance vs. Drain Current
400
5
ID = 3.6 A
VGS - Gate-to-Source Voltage (V)
Ciss
320
C - Capacitance (pF)
8
240
160
Coss
80
VDS = 10 V
4
VDS = 5 V
3
VDS = 15 V
2
1
Crss
0
0
0
5
10
15
20
0
2
3
Qg - Total Gate Charge (nC)
Capacitance
Gate Charge
4
100
1.6
VGS = 2.5 V, ID = 3.1 A
1.4
10
1.2
VGS = 4.5 V, ID = 3.6 A
1.0
0.8
0.6
- 50
I S - Source Current (A)
R DS(on) - On-Resistance (Normalized)
1
VDS - Drain-to-Source Voltage (V)
TJ = 150 °C
1
0.1
TJ = 25 °C
0.01
- 25
0
25
50
75
100
125
150
0.001
0.0
TJ = - 55 °C
0.2
0.4
0.6
0.8
1.0
TJ - Junction Temperature (°C)
VSD - Source-to-Drain Voltage (V)
On-Resistance vs. Junction Temperature
Source-Drain Diode Forward Voltage
Document Number: 68645
S12-2336-Rev. D, 01-Oct-12
For technical questions, contact: [email protected]
1.2
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2302CDS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.2
0.1
0.10
VGS(th) Variance (V)
R DS(on) - On-Resistance (Ω)
0.12
0.08
TJ = 125 °C
0.0
- 0.1
ID = 1 mA
0.06
- 0.2
ID = 250 µA
TJ = 25 °C
- 0.3
- 50
0.04
0
1
2
3
4
VGS - Gate-to-Source Voltage (V)
5
- 25
0
25
50
75
100
125
150
TJ - Temperature (°C)
On-Resistance vs. Gate-to-Source Voltage
Threshold Voltage
10
10
Limited by RDS(on)*
100 µs
8
I D - Drain Current (A)
Power (W)
1 ms
6
4
1
10 ms
100 ms
0.1
1s
10 s
100 s, DC
TA = 25 °C
Single Pulse
2
TA = 25 °C
BVDSS Limited
0
0.01
0.1
1
10
100
1000
0.01
0.1
Time (s)
Single Pulse Power
100
1
10
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
Notes:
0.05
PDM
0.1
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 70 °C/W
3. TJM - TA = PDMZthJA(t)
Single Pulse
0.01
10 -4
10 -3
4. Surface Mounted
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68645.
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For technical questions, contact: [email protected]
Document Number: 68645
S12-2336-Rev. D, 01-Oct-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E1
1
E
2
e
S
e1
D
0.10 mm
C
0.004"
A2
A
C
q
Gauge Plane
Seating Plane
Seating Plane
C
A1
Dim
0.25 mm
L
L1
MILLIMETERS
Min
INCHES
Max
Min
Max
0.044
A
0.89
1.12
0.035
A1
0.01
0.10
0.0004
0.004
A2
0.88
1.02
0.0346
0.040
b
0.35
0.50
0.014
0.020
c
0.085
0.18
0.003
0.007
D
2.80
3.04
0.110
0.120
E
2.10
2.64
0.083
0.104
E1
1.20
1.40
0.047
e
0.95 BSC
e1
L
1.90 BSC
0.40
L1
q
0.0748 Ref
0.60
0.016
0.64 Ref
S
0.024
0.025 Ref
0.50 Ref
3°
0.055
0.0374 Ref
0.020 Ref
8°
3°
8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
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AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
Document Number: 70739
26-Nov-03
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
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Application Note 826
Vishay Siliconix
0.049
(1.245)
0.029
0.022
(0.559)
(0.724)
0.037
(0.950)
(2.692)
0.106
RECOMMENDED MINIMUM PADS FOR SOT-23
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index Return to Index
APPLICATION NOTE
Document Number: 72609
Revision: 21-Jan-08
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Revision: 02-Oct-12
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Document Number: 91000