Si2365EDS Datasheet

Si2365EDS
Vishay Siliconix
P-Channel 20 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
- 20
RDS(on) () Max.
ID (A)
0.0320 at VGS = - 4.5 V
- 5.9
0.0410 at VGS = - 2.5 V
- 5.2
0.0675 at VGS = - 1.8 V
- 4.3
a
Qg (Typ.)
13.8 nC
TO-236
(SOT-23)
G
APPLICATIONS
• Power Management for Portable and Consumer
- Load Switches
- DC/DC Converters
1
3
S
• TrenchFET® Power MOSFET
• 100 % Rg Tested
• Built-in ESD Protection
- Typical ESD Performance 3000 V
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
S
D
2
Top View
G
Si2365EDS (H5)*
* Marking Code
D
Ordering Information:
Si2365EDS-T1-GE3 (Lead (Pb)-free and Halogen-free)
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (TJ = 150 °C)
Symbol
VDS
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
Limit
- 20
±8
- 5.9
- 4.7
ID
Continuous Source-Drain Diode Current
- 3.6b, c
- 20
- 1.4
IDM
Maximum Power Dissipation
TC = 25 °C
TA = 25 °C
TC = 25 °C
TC = 70 °C
TA = 25 °C
IS
A
- 1b, c
1.7
1.1
PD
W
1b, c
0.6b, c
- 55 to 150
260
TA = 70 °C
TJ, Tstg
Operating Junction and Storage Temperature Range
V
- 4.5b, c
TA = 70 °C
Pulsed Drain Current (t = 300 µs)
Unit
Soldering Recommendations (Peak Temperature)d, e
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambientb, d
Maximum Junction-to-Foot (Drain)
t5s
Symbol
RthJA
Typical
100
Maximum
130
Steady State
RthJF
60
75
Unit
°C/W
Notes:
a. TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 175 °C/W.
Document Number: 63199
S13-1505-Rev. C, 01-Jul-13
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This document is subject to change without notice.
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Si2365EDS
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = - 250 µA
- 20
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
VDS/TJ
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
VGS(th)/TJ
Gate-Source Threshold Voltage
VGS(th)
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-State Resistancea
- 14
ID = - 250 µA
VDS = VGS, ID = - 250 µA
V
- 0.4
-1
VDS = 0 V, VGS = ± 8 V
± 10
VDS = 0 V, VGS = ± 4.5 V
±1
VDS = - 20 V, VGS = 0 V
-1
VDS = - 20 V, VGS = 0 V, TJ = 55 °C
VDS - 5 V, VGS = - 4.5 V
RDS(on)
mV/°C
2.5
V
µA
- 10
- 15
A
VGS = - 4.5 V, ID = - 4 A
0.0265
0.0320
VGS = - 2.5 V, ID = - 4 A
0.0340
0.0410
VGS = - 1.8 V, ID = - 2 A
0.0465
0.0675
VDS = - 10 V, VGS = - 8 V, ID = - 4.5 A
23.8
36
13.8
21

Dynamicb
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Gate Resistance
Rg
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
VDS = - 10 V, VGS = - 4.5 V, ID = - 4.5 A
1.9
nC
3
f = 1 MHz
td(on)
VDD = - 10 V, RL = 2.8 
ID  - 3.6 A, VGEN = - 4.5 V, Rg = 1 
tr
td(off)
2.2
11
22
22
33
21
32
62
93
tf
14
21
td(on)
9
18
6
12
VDD = - 10 V, RL = 2.8 
ID  - 3.6 A, VGEN = - 8 V, Rg = 1 
tr
td(off)
tf
65
98
15
23

ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
TC = 25 °C
IS
Pulse Diode Forward Current
ISM
Body Diode Voltage
VSD
- 1.4
- 20
IS = - 3.6 A, VGS = 0 V
- 0.8
- 1.2
A
V
Body Diode Reverse Recovery Time
trr
13
20
ns
Body Diode Reverse Recovery Charge
Qrr
5
10
nC
Reverse Recovery Fall Time
ta
Reverse Recovery Rise Time
tb
IF = - 3.6 A, dI/dt = 100 A/µs, TJ = 25 °C
8
5
ns
Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 63199
For technical questions, contact: [email protected]
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S13-1505-Rev. C, 01-Jul-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2365EDS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10-2
0.050
TJ = 25 °C
10-3
10-4
IGSS - Gate Current (A)
IGSS - Gate Current (mA)
0.040
0.030
0.020
TJ = 150 °C
10-5
10-6
TJ = 25 °C
10-7
0.010
10-8
0.000
0
3
6
9
12
10-9
15
0
VGS - Gate-Source Voltage (V)
4
8
12
16
20
VGS - Gate-to-Source Voltage (V)
Gate Current vs. Gate-Source Voltage
Gate Current vs. Gate-Source Voltage
15
0.5
VGS = 8 V thru 2 V
0.4
ID - Drain Current (A)
ID - Drain Current (A)
12
9
VGS = 1.5 V
6
3
0.3
TC = 25 °C
0.2
TC = 125 °C
0.1
VGS = 1 V
TC = - 55 °C
0
0
0
0.5
1
1.5
2
0
0.35
0.7
1.05
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.1
1.4
2000
1500
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
0.08
VGS = 1.8 V
0.06
VGS = 2.5 V
0.04
1000
500
VGS = 4.5 V
0.02
Ciss
Coss
0
Crss
0
0
5
10
15
ID - Drain Current (A)
On-Resistance vs. Drain Current
20
0
5
10
15
20
VDS - Drain-to-Source Voltage (V)
Capacitance
Document Number: 63199
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S13-1505-Rev. C, 01-Jul-13
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2365EDS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
8
1.5
ID = 4 A
6
RDS(on) - On-Resistance (Normalized)
VGS - Gate-to-Source Voltage (V)
ID = 4.5 A
VDS = 10 V
VDS = 5 V
4
VDS = 16 V
2
0
VGS = 4.5 V
1.3
VGS = 2.5 V
1.1
0.9
0.7
0
5
10
15
20
25
- 50
- 25
Qg - Total Gate Charge (nC)
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
30
0.7
ID = 250 μA
0.6
VGS(th) (V)
Power (W)
20
0.5
0.4
10
0.3
0
0.001
0.01
0.1
1
10
0.2
100
- 50
Time (s)
- 25
0
25
50
75
100
125
150
TJ - Temperature (°C)
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
0.080
RDS(on) - On-Resistance (Ω)
IS - Source Current (A)
ID = 4 A
10
TJ = 150 °C
1
TJ = 25 °C
0.1
0.060
0.040
TJ = 125 °C
TJ = 25 °C
0.020
0.000
0.0
0.3
0.6
0.9
1.2
VSD - Source-to-Drain Voltage (V)
Soure-Drain Diode Forward Voltage
1.5
0
2
4
6
8
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
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Document Number: 63199
For technical questions, contact: [email protected]
4
S13-1505-Rev. C, 01-Jul-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2365EDS
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
7
100
5.6
Limited by RDS(on)*
10
ID - Drain Current (A)
ID - Drain Current (A)
100 μs
1 ms
1
10 ms
100 ms
10 s,1 s
DC
0.1
0.01
4.2
2.8
1.4
TA = 25 °C
Single Pulse
BVDSS Limited
0.001
0
0.1
1
10
100
0
25
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
50
75
100
125
150
125
150
TC - Case Temperature (°C)
Current Derating*
Safe Operating Area, Junction-to-Ambient
2
0.9
0.7
Power (W)
Power (W)
1.5
1
0.5
0.5
0.4
0.2
0.0
0
0
25
50
75
100
TC - Case Temperature (°C)
Power Junction-to-Case
125
150
0
25
50
75
100
TA - Ambient Temperature (°C)
Power Junction-to-Ambient
* The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Document Number: 63199
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S13-1505-Rev. C, 01-Jul-13
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2365EDS
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
Notes:
0.02
PDM
t1
0.01
Single Pulse
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 175 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
0.001
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
10
100
1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10 -4
10 -3
10 -2
10 -1
1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63199.
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Document Number: 63199
For technical questions, contact: [email protected]
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S13-1505-Rev. C, 01-Jul-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E1
1
E
2
e
S
e1
D
0.10 mm
C
0.004"
A2
A
C
q
Gauge Plane
Seating Plane
Seating Plane
C
A1
Dim
0.25 mm
L
L1
MILLIMETERS
Min
INCHES
Max
Min
Max
0.044
A
0.89
1.12
0.035
A1
0.01
0.10
0.0004
0.004
A2
0.88
1.02
0.0346
0.040
b
0.35
0.50
0.014
0.020
c
0.085
0.18
0.003
0.007
D
2.80
3.04
0.110
0.120
E
2.10
2.64
0.083
0.104
E1
1.20
1.40
0.047
e
0.95 BSC
e1
L
1.90 BSC
0.40
L1
q
0.0748 Ref
0.60
0.016
0.64 Ref
S
0.024
0.025 Ref
0.50 Ref
3°
0.055
0.0374 Ref
0.020 Ref
8°
3°
8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
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1
AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
Document Number: 70739
26-Nov-03
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
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Application Note 826
Vishay Siliconix
0.049
(1.245)
0.029
0.022
(0.559)
(0.724)
0.037
(0.950)
(2.692)
0.106
RECOMMENDED MINIMUM PADS FOR SOT-23
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index Return to Index
APPLICATION NOTE
Document Number: 72609
Revision: 21-Jan-08
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25
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Revision: 02-Oct-12
1
Document Number: 91000