D2 PA K-7 BUK9C10-55BIT N-channel TrenchPLUS logic level FET 25 August 2014 Product data sheet 1. General description Logic level N-channel MOSFET in a D2PAK-7 package using TrenchPLUS MOSFET technology. The device includes TrenchPLUS current sensing and integrated diodes for temperature sensing. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits • • • • AEC-Q101 Compliant Enables temperature monitoring due to integrated temperature sensor Enables current sense measurement due to integrated current senseFET Suitable for thermally demanding environments due to 175 °C rating 3. Applications • • • 12 V Automotive systems Motors, lamps and solenoid control Powertrain, chassis and body applications 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VGS = 5 V; ID = 10 A; Tj = 25 °C; - 8.2 10 mΩ - 7.5 9 mΩ Static characteristics RDSon drain-source on-state resistance Fig. 16; Fig. 17 VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 16; Fig. 17 ID/Isense ratio of drain current to -55 °C < Tj < 175 °C; VGS = 5 V; Fig. 18 sense current 10000 11000 12000 A/A SF(TSD) temperature sense diode temperature coefficient IF = 250 µA; -55 °C ≤ Tj ≤ 175 °C; -5.7 -6 -6.3 mV/K V(BR)DSS drain-source breakdown voltage ID = 25 mA; VGS = 0 V; Tj = 25 °C 55 - - V VF(TSD) temperature sense diode forward voltage IF = 250 µA; Tj = 25 °C; Fig. 19 2.855 2.9 2.945 V Fig. 19 Scan or click this QR code to view the latest information for this product BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 5. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 IS current sense 3 A anode 4 D[1] drain Graphic symbol D mb A G IS 4 5 C cathode 6 KS Kelvin source 7 S source mb D mounting base [1] Simplified outline S KS C 003aad829 123 567 D2PAK-7 (SOT427) It is not possible to connect to pin 4 of the SOT427 package 6. Ordering information Table 3. Ordering information Type number Package BUK9C10-55BIT Name Description Version D2PAK-7 Plastic single-ended surface-mounted package (D2PAK-7); 7 leads (one lead cropped) SOT427 7. Marking Table 4. Marking codes Type number Marking code BUK9C10-55BIT 28083 576 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 55 V VDGR drain-gate voltage RGS = 20 kΩ; 25 °C ≤ Tj ≤ 175 °C - 55 V VGS gate-source voltage -15 15 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 194 W ID drain current VGS = 5 V; Tmb = 25 °C; Fig. 2; Fig. 3 - 75 A - 65 A VGS = 5 V; Tmb = 100 °C; Fig. 2 BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 [1] © NXP Semiconductors N.V. 2014. All rights reserved 2 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET Symbol Parameter Conditions Min Max Unit IDM peak drain current Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 3 - 401 A Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Visol(FET-TSD) FET to temperature sense diode isolation voltage - 100 V [2][3][4] - 215 mJ - 75 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 75 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C; unclamped; Fig. 4 Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 401 A HBM; C = 100 pF; R = 1.5 kΩ; all pins - 0.1 kV HBM; C = 100 pF; R = 1.5 kΩ; pin 4 to pin 7 - 4 kV [1] Electrostatic discharge VESD electrostatic discharge voltage [1] [2] [3] [4] Current is limited by package Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. Refer to application note AN10273 for further information. Repetitive rating defined in avalanche rating figure. 03na19 120 003aab885 100 ID (A) 80 Pder (%) (1) 80 60 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) Normalized total power dissipation as a function of mounting base temperature BUK9C10-55BIT Product data sheet 0 200 0 50 100 150 Tmb (°C) 200 (1) Capped at 75A due to package Fig. 2. Continuous drain current as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 3 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 003aab897 103 Limit RDSon = VDS / ID ID (A) tp = 10 µ s 102 100 µ s 1 ms DC 10 10 ms 100 ms 1 10-1 Fig. 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage IAL (A) 003aab922 102 (1) (2) 10 (3) 1 10-3 Fig. 4. 10-2 10-1 1 tAL (ms) 10 Avalanche rating; avalanche current as a function of avalanche time 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - 0.46 0.78 K/W Rth(j-a) thermal resistance from junction to ambient mounted on printed circuit board; Fig. 6; Fig. 7; Fig. 8; Fig. 9 - 61.4 - K/W BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 4 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 003aab901 1 δ = 0.5 Zth (j-mb) (K/W) 0.2 0.1 10-1 0.02 0.05 10-2 P δ= tp T single shot tp 10-3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 10-1 t T tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration 003aab972 80 R th(j-a) K/W 60 001aag966 40 20 Fig. 7. 0 200 A (mm2) PCB used for thermal tests; zero heat sink area 400 Zero airflow Fig. 6. Thermal resistance from junction to ambient as a function of printed-circuit board (PCB) heat sink area 001aag967 Fig. 8. 001aag968 PCB used for thermal tests; heat sink area 200 mm Fig. 9. 2 BUK9C10-55BIT Product data sheet PCB used for thermal tests; heat sink area 400 mm 2 All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 5 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 25 mA; VGS = 0 V; Tj = -55 °C 50 - - V ID = 25 mA; VGS = 0 V; Tj = 25 °C 55 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 47 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.1 1.5 2 V 0.5 - - V - - 2.3 V VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 40 V; VGS = 0 V; Tj = 175 °C - - 125 µA VDS = 0 V; VGS = -15 V; Tj = 25 °C - 2 100 nA VDS = 0 V; VGS = 15 V; Tj = 25 °C - 2 100 nA VGS = 4.5 V; ID = 10 A; Tj = 25 °C; - 8.4 15 mΩ - 8.2 10 mΩ - - 20 mΩ - 7.5 9 mΩ Static characteristics V(BR)DSS VGSth drain-source breakdown voltage gate-source threshold voltage Fig. 14; Fig. 15 ID = 1 mA; VDS = VGS; Tj = 175 °C; Fig. 14 ID = 1 mA; VDS = VGS; Tj = -55 °C; Fig. 14 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 16; Fig. 17 VGS = 5 V; ID = 10 A; Tj = 25 °C; Fig. 16; Fig. 17 VGS = 5 V; ID = 10 A; Tj = 175 °C; Fig. 16; Fig. 17 VGS = 10 V; ID = 10 A; Tj = 25 °C; Fig. 16; Fig. 17 ID/Isense ratio of drain current to VGS = 5 V; -55 °C < Tj < 175 °C; Fig. 18 sense current 10000 11000 12000 A/A SF(TSD) temperature sense diode temperature coefficient IF = 250 µA; -55 °C ≤ Tj ≤ 175 °C; -5.7 -6 -6.3 mV/K temperature sense diode forward voltage IF = 250 µA; Tj = 25 °C; Fig. 19 2.855 2.9 2.945 V total gate charge ID = 10 A; VDS = 44 V; VGS = 5 V; - 51 - nC QGS gate-source charge Fig. 20 - 8 - nC QGD gate-drain charge - 17 - nC Ciss input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz; - 3500 4667 pF output capacitance Tj = 25 °C; Fig. 21 - 526.7 635 pF VF(TSD) Fig. 19 Dynamic characteristics QG(tot) Coss BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 6 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET Symbol Parameter Conditions Min Typ Max Unit Crss reverse transfer capacitance - 246.2 348 pF td(on) turn-on delay time VDS = 30 V; RL = 3 Ω; VGS = 5 V; - 80 - ns RG(ext) = 10 Ω tr rise time - 32 - ns td(off) turn-off delay time - 100 - ns tf fall time - 170 - ns LD internal drain inductance from pin to center of die - 0.85 - nH LS internal source inductance from source lead to source bonding pad - 1.9 - nH Source-drain diode VSD source-drain voltage IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 22 - 0.85 1.2 V trr reverse recovery time IS = 5 A; dIS/dt = -100 A/µs; - 65.5 - ns Qr recovered charge VGS = -10 V; VDS = 30 V - 122 - nC ID (A) 003aab882 200 5 RDSon (mΩ) 10 14 4 150 12 3.5 100 003aab884 16 4.5 10 3 50 8 2.5 VGS (V) = 2 0 0 2 4 6 8 6 10 VDS (V) Tj = 25 °C; tp = 300 μs Fig. 10. Output characteristics; drain current as a function of drain-source voltage; typical values BUK9C10-55BIT Product data sheet 2 4 6 8 10 VGS (V) Fig. 11. Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 7 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET ID (A) 003aab883 80 003aab931 80 gfs (S) 60 60 40 40 20 20 Tj = 175 °C Tj = 25 °C 0 0 1 2 3 VGS (V) 0 4 VDS = 25 V 03ng52 2.5 ID (A) 30 Fig. 13. Forward transconductance as a function of drain current; typical values 03ng53 ID (A) 2.0 10- 2 max 1.5 min 10- 3 typ min 1.0 typ max 10- 4 10- 5 0.5 0 60 120 Tj (°C) 10- 6 180 Fig. 14. Gate-source threshold voltage as a function of junction temperature Product data sheet 20 10- 1 VGS(th) (V) BUK9C10-55BIT 10 Tj = 25 °C; VDS = 25 V Fig. 12. Transfer characteristics; drain current as a function of gate-source voltage; typical values 0 - 60 0 0 1 2 VGS (V) 3 Fig. 15. Sub-threshold drain current as a function of gate-source voltage All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 8 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 003aab918 25 RDSon (mΩ) 20 003aab993 2.5 a VGS (V) = 2.5 2 3 15 1.5 3.5 4 10 1 5 10 0.5 5 0 0 20 40 60 80 ID (A) 0 -60 100 Tj = 25 °C; tp = 300 μs Fig. 16. Drain-source on-state resistance as a function of drain current; typical values 20 60 100 140 180 Tj (°C) Fig. 17. Normalized drain-source on-state resistance factor as a function of junction temperature 003aab914 14000 -20 001aae485 3.0 VF(TSD) (V) ID/Isense 12000 2.5 10000 2.0 8000 2 4 6 8 VGS (V) 1.5 10 Tj = 25 °C; ID = 10 A Fig. 18. Ratio of drain current to sense current as a function of gate-source voltage; typical values BUK9C10-55BIT Product data sheet 0 40 80 120 Tj (°C) 160 Fig. 19. Temperature sense diode forward voltage as a function of junction temperature; typical values All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 9 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 003aab930 5 C (pF) VGS (V) 4 5000 Ciss VDS = 14 V 3 003aab909 6000 4000 VDS = 44 V 3000 2 1 2000 Coss 1000 Crss 0 0 20 40 Q G (nC) 0 10-1 60 Tj = 25 °C; ID = 10 A 1 10 V DS (V) 102 VGS = 0 V; f = 1 MHz Fig. 20. Gate-source voltage as a function of gate charge; typical values Fig. 21. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aab881 100 ID (A) 80 60 40 20 Tj = 175 °C 0 0.0 Tj = 25 °C 0.5 1.0 V SD (V) 1.5 VGS = 0 V Fig. 22. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 10 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 11. Package outline Plastic single-ended surface-mounted package (D2PAK-7); 7 leads (one lead cropped) SOT427 A A1 E D1 mounting base D HD 4 1 Lp 7 b e e e e e c e Q 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit(1) max nom min mm A A1 b c 4.5 1.40 0.85 0.64 4.1 1.27 0.60 0.46 D D1 E e 11 1.6 10.3 1.2 9.7 1.27 Lp HD Q 2.90 15.8 2.6 2.10 14.8 2.2 sot427_po Outline version References IEC JEDEC JEITA European projection Issue date 06-03-16 12-10-16 SOT427 Fig. 23. Package outline D2PAK-7 (SOT427) BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 11 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 12. 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BUK9C10-55BIT Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 12 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, ICODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP Semiconductors N.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 13 / 14 BUK9C10-55BIT NXP Semiconductors N-channel TrenchPLUS logic level FET 13. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ............................................. 2 7 Marking ................................................................... 2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics ....................................................... 6 11 Package outline ................................................... 11 12 12.1 12.2 12.3 12.4 Legal information .................................................12 Data sheet status ............................................... 12 Definitions ...........................................................12 Disclaimers .........................................................12 Trademarks ........................................................ 13 © NXP Semiconductors N.V. 2014. All rights reserved For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 August 2014 BUK9C10-55BIT Product data sheet All information provided in this document is subject to legal disclaimers. 25 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved 14 / 14