X9317
Low Noise, Low Power, 100 Taps
®
Data Sheet
Digitally Controlled Potentiometer
(XDCP™)
The Intersil X9317 is a digitally controlled potentiometer
(XDCP™). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
December 16, 2009
FN8183.6
Features
• Solid-State Potentiometer
• 3-Wire Serial Up/Down Interface
• 100 Wiper Tap Points
- Wiper Position Stored in Nonvolatile Memory and
Recalled on Power-up
• 99 Resistive Elements
- Temperature Compensated
- End-to-end Resistance Range ±20%
• Low Power CMOS
- VCC = 2.7V to 5.5V, and 5V ±10%
- Standby Current <5µA
• High Reliability
- Endurance, 100,000 Data Changes per Bit
- Register Data Retention, 100 years
• RTOTAL Values = 1kΩ, 10kΩ, 50kΩ, 100kΩ
Pinouts
• Packages
- 8 Ld SOIC, PDIP, TSSOP, and MSOP
X9317
(8 LD TSSOP)
TOP VIEW
• Pb-Free Available (RoHS Compliant)
Applications
8
RL
7
RW
3
6
VSS
• DC Bias Adjustment
4
5
RH
• Gain and Offset Trim
CS
1
VCC
2
INC
U/D
X9317
• LCD Bias Control
• Laser Diode Bias Control
X9317
(8 LD PDIP, 8 LD SOIC, 8 LD MSOP)
TOP VIEW
8
VCC
7
CS
3
6
RL
4
5
RW
INC
1
U/D
2
RH
VSS
X9317
1
• Voltage Regulator Output Control
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004-2005, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9317
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMPERATURE
RANGE (°C)
5 ±10%
1
0 to +70
8 Ld MSOP
M8.118
8 Ld MSOP (Pb-free)
M8.118
PACKAGE
PKG.
DWG. #
X9317ZM8* (Note 2)
AFG
X9317ZM8Z* (Note 1)
DDA
0 to +70
X9317ZM8I* (Note 2)
AFI
-40 to +85
8 Ld MSOP
M8.118
X9317ZM8IZ* (Note 1)
DCY
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317ZP (Note 2)
X9317ZP
0 to +70
8 Ld PDIP
MDP0031
X9317ZS8* (Note 2)
X9317Z
0 to +70
8 Ld SOIC
M8.15E
X9317ZS8Z* (Note 1)
X9317Z Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317ZS8I* (Note 2)
9317W F
-40 to +85
8 Ld SOIC
M8.15E
X9317ZS8IZ* (Note 1)
X9317Z Z I
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
X9317ZV8* (Note 2)
9317Z
0 to +70
8 Ld TSSOP
M8.173
X9317ZV8Z* (Note 1)
9317Z Z
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
X9317ZV8I* (Note 2)
317Z I
-40 to +85
8 Ld TSSOP
M8.173
X9317ZV8IZ* (Note 1)
9317Z IZ
-40 to +85
8 Ld TSSOP (Pb-free)
M8.173
X9317WM8T1 (Note 2)
ABF
0 to +70
8 Ld MSOP
M8.118
X9317WM8Z* (Note 1)
DCW
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9317WM8I*
ADS
-40 to +85
8 Ld MSOP
M8.118
X9317WM8 (Note 2)
ABF
-40 to +85
8 Ld MSOP
M8.118
X9317WM8IZ* (Note 1)
DCT
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317WP
X9317WP
0 to +70
8 Ld PDIP
MDP0031
X9317WPI (Note 2)
X9317WP I
-40 to +85
8 Ld PDIP
MDP0031
X9317WS8*
X9317W
0 to +70
8 Ld SOIC
M8.15E
X9317WS8Z* (Note 1)
X9317W Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317WS8I
X9317W I
-40 to +85
8 Ld SOIC
M8.15E
X9317WS8IT1 (Note 2)
X9317W I
-40 to +85
8 Ld SOIC
M8.15E
X9317WS8IZ* (Note 1)
X9317W ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
X9317WV8
9317W
0 to +70
8 Ld TSSOP
M8.173
X9317WV8T1 (Note 2)
9317W
0 to +70
8 Ld TSSOP
M8.173
10
X9317WV8T2 (Note 2)
9317W
0 to +70
8 Ld TSSOP
M8.173
X9317WV8Z* (Note 1)
9317W Z
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
X9317WV8I
317W I
-40 to +85
8 Ld TSSOP
M8.173
X9317WV8IT1 (Note 2)
317W I
-40 to +85
8 Ld TSSOP
M8.173
X9317WV8IZ* (Note 1)
9317W IZ
-40 to +85
8 Ld TSSOP (Pb-free)
M8.173
X9317UM8* (Note 2)
AEC
0 to +70
8 Ld MSOP
M8.118
X9317UM8Z* (Note 1)
DCS
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9317UM8I* (Note 2)
AFE
-40 to +85
8 Ld MSOP
M8.118
X9317UM8IZ* (Note 1)
DCR
-40 to +85
X9317UP (Note 2)
X9317UP
X9317UPI (Note 2)
X9317UP I
X9317US8* (Note 2)
X9317U
X9317US8Z* (Note 1)
X9317US8I* (Note 2)
X9317US8IZ* (Note 1)
8 Ld MSOP (Pb-free)
M8.118
0 to +70
8 Ld PDIP
MDP0031
-40 to +85
8 Ld PDIP
MDP0031
0 to +70
8 Ld SOIC
M8.15E
X9317U Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317U I
-40 to +85
8 Ld SOIC
M8.15E
X9317U ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
2
50
FN8183.6
December 16, 2009
X9317
Ordering Information (Continued)
PART NUMBER
PART MARKING
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMPERATURE
RANGE (°C)
5 ±10%
50
0 to +70
8 Ld TSSOP
0 to +70
PACKAGE
PKG.
DWG. #
X9317UV8* (Note 2)
9317U
X9317UV8Z* (Note 1)
9317U Z
8 Ld TSSOP (Pb-free)
M8.173
X9317UV8I* (Note 2)
317U I
-40 to +85
8 Ld TSSOP
M8.173
X9317UV8IZ* (Note 1)
9317U IZ
-40 to +85
8 Ld TSSOP (Pb-free)
M8.173
X9317TM8*, ** (Note 2)
AGD
0 to +70
8 Ld MSOP
M8.118
X9317TM8Z* (Note 1)
DCN
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9317TM8I*, ** (Note 2)
AGF
-40 to +85
8 Ld MSOP
M8.118
X9317TM8IZ* (Note 1)
DCL
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317TP (Note 2)
X9317TP
0 to +70
8 Ld PDIP
MDP0031
X9317TPI (Note 2)
X9317TP I
-40 to +85
8 Ld PDIP
MDP0031
X9317TS8 (Note 2)
X9317T
0 to +70
8 Ld SOIC
M8.15E
X9317TS8Z (Note 1)
X9317T Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317TS8I (Note 2)
X9317T I
-40 to +85
8 Ld SOIC
M8.15E
X9317TS8IZ (Note 1)
X9317T ZI
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
X9317TV8*, ** (Note 2)
9317T
0 to +70
8 Ld TSSOP
M8.173
X9317TV8Z* (Note 1)
9317T Z
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
X9317TV8I*, ** (Note 2)
317T I
-40 to +85
8 Ld TSSOP
M8.173
X9317TV8IZ* (Note 1)
9317T IZ
-40 to +85
X9317ZM8-2.7* (Note 2)
AFH
X9317ZM8Z-2.7* (Note 1)
X9317ZM8I-2.7* (Note 2)
100
M8.173
8 Ld TSSOP (Pb-free)
M8.173
0 to +70
8 Ld MSOP
M8.118
AOA
0 to +70
8 Ld MSOP (Pb-free)
M8.118
AFJ
-40 to +85
8 Ld MSOP
M8.118
X9317ZM8IZ-2.7* (Note 1)
DCZ
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317ZS8-2.7* (Note 2)
X9317Z F
0 to +70
8 Ld SOIC
M8.15E
X9317ZS8Z-2.7* (Note 1)
X9317Z ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317ZS8I-2.7* (Note 2)
X9317Z G
-40 to +85
8 Ld SOIC
M8.15E
X9317ZS8IZ-2.7* (Note 1)
X9317Z ZG
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
X9317ZV8-2.7* (Note 2)
317Z F
0 to +70
8 Ld TSSOP
M8.173
X9317ZV8Z-2.7* (Note 1)
9317Z FZ
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
X9317ZV8I-2.7*, ** (Note 2)
317Z G
-40 to +85
8 Ld TSSOP
M8.173
X9317ZV8IZ-2.7* (Note 1)
9317Z GZ
-40 to +85
X9317WM8-2.7* (Note 2)
ACZ
X9317WM8Z-2.7* (Note 1)
X9317WM8I-2.7
2.7 to 5.5
1
8 Ld TSSOP (Pb-free)
M8.173
0 to +70
8 Ld MSOP
M8.118
DCX
0 to +70
8 Ld MSOP (Pb-free)
M8.118
ADT
-40 to +85
8 Ld MSOP
M8.118
10
X9317WM8I-2.7T1 (Note 2)
ADT
-40 to +85
8 Ld MSOP
M8.118
X9317WM8IZ-2.7* (Note 2)
DCU
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317WP-2.7 (Note 2)
X9317WP F
0 to +70
8 Ld PDIP
MDP0031
X9317WPI-2.7 (Note 2)
X9317WP G
-40 to +85
8 Ld PDIP
MDP0031
X9317WS8-2.7
X9317W F
0 to +70
8 Ld SOIC
M8.15E
X9317WS8-2.7T1 (Note 2)
X9317W F
0 to +70
8 Ld SOIC
M8.15E
X9317WS8Z-2.7* (Note 1)
X9317W ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317WS8I-2.7** (Note 2)
X9317W G
-40 to +85
8 Ld SOIC
M8.15E
X9317WS8I-2.7T1
X9317W G
-40 to +85
8 Ld SOIC
M8.15E
3
FN8183.6
December 16, 2009
X9317
Ordering Information (Continued)
PART NUMBER
PART MARKING
X9317WS8IZ-2.7* (Note 1)
X9317W ZG
X9317WV8-2.7* (Note 2)
317W F
X9317WV8Z-2.7* (Note 1)
9317W FZ
X9317WV8I-2.7*, ** (Note 2)
317W G
X9317WV8IZ-2.7* (Note)
VCC LIMITS
(V)
RTOTAL
(kΩ)
TEMPERATURE
RANGE (°C)
2.7 to 5.5
10
-40 to +85
PACKAGE
PKG.
DWG. #
8 Ld SOIC (Pb-free)
M8.15E
0 to +70
8 Ld TSSOP
M8.173
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
-40 to +85
8 Ld TSSOP
M8.173
AKZ
-40 to +85
8 Ld TSSOP (Pb-free)
M8.173
X9317UM8-2.7* (Note 2)
AED
0 to +70
8 Ld MSOP
M8.118
X9317UM8Z-2.7* (Note 1)
AOB
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9317UM8I-2.7*, ** (Note 2)
AFF
-40 to +85
8 Ld MSOP
M8.118
X9317UM8IZ-2.7* (Note 1)
AOH
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317US8-2.7* (Note 2)
X9317U F
0 to +70
8 Ld SOIC
M8.15E
X9317UP-2.7 (Note 2)
X9317UP F
50
0 to +70
8 Ld PDIP
MDP0031
X9317UPI-2.7 (Note 2)
X9317UP G
-40 to +85
8 Ld PDIP
MDP0031
X9317US8Z-2.7* (Note 1)
X9317U ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317US8I-2.7*, ** (Note 2)
X9317U G
-40 to +85
8 Ld SOIC
M8.15E
X9317US8IZ-2.7* (Note 1)
X9317U ZG
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
X9317UV8-2.7* (Note 2)
317U F
0 to +70
8 Ld TSSOP
M8.173
X9317UV8Z-2.7* (Note 1)
9317U FZ
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
X9317UV8I-2.7*, ** (Note 2)
317U G
-40 to +85
8 Ld TSSOP
M8.173
X9317UV8IZ-2.7* (Note 1)
9317U GZ
-40 to +85
8 Ld TSSOP (Pb-free)
M8.173
X9317TM8-2.7*, ** (Note 2)
AGE
0 to +70
8 Ld MSOP
M8.118
X9317TM8Z-2.7* (Note 1)
DCP
0 to +70
8 Ld MSOP (Pb-free)
M8.118
100
X9317TM8I-2.7*, ** (Note 2)
AGG
-40 to +85
8 Ld MSOP
M8.118
X9317TM8IZ-2.7* (Note 1)
DCM
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9317TP-2.7 (Note 2)
X9317TP F
0 to +70
8 Ld PDIP
MDP0031
X9317TPI-2.7 (Note 2)
X9317TP G
-40 to +85
8 Ld PDIP
MDP0031
X9317TS8-2.7*, ** (Note 2)
X9317T F
0 to +70
8 Ld SOIC
M8.15E
X9317TS8Z-2.7* (Note 1)
X9317T ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15E
X9317TS8I-2.7*, ** (Note 2)
X9317T G
-40 to +85
8 Ld SOIC
M8.15E
X9317TS8IZ-2.7* (Note 1)
X9317T ZG
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
X9317TV8-2.7*, ** (Note 2)
317T F
0 to +70
8 Ld TSSOP
M8.173
X9317TV8Z-2.7* (Note 1)
9317T FZ
0 to +70
8 Ld TSSOP (Pb-free)
M8.173
X9317TV8I-2.7*, ** (Note 2)
317T G
-40 to +85
8 Ld TSSOP
M8.173
X9317TV8IZ-2.7* (Note 1)
9317T GZ
-40 to +85
8 Ld TSSOP (Pb-free)
M8.173
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Not recommended for new designs.
4
FN8183.6
December 16, 2009
X9317
Block Diagram
U/D
INC
CS
VCC (SUPPLY VOLTAGE)
CONTROL
AND
MEMORY
97
7-BIT
NONVOLATILE
MEMORY
RW
DEVICE SELECT
(CS)
RH
99
98
RH
UP/DOWN
(U/D)
INCREMENT
(INC)
UP/DOWN
COUNTER
96
ONE
OF
ONE
HUNDRED
DECODER
WIPER
SWITCHES
RESISTOR
ARRAY
RL
2
VSS (GROUND)
VCC
VSS
GENERAL
STORE AND
RECALL
CONTROL
CIRCUITRY
1
0
RL
RW
DETAILED
Pin Descriptions
PDIP/SOIC/MSOP
TSSOP
SYMBOL
1
3
INC
Increment Toggling INC while CS is low moves the wiper either up or down.
2
4
U/D
Up/Down The U/D input controls the direction of the wiper movement.
3
5
RH
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
4
6
VSS
Ground
5
7
R
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
6
8
RL
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
7
1
CS
Chip Select The device is selected when the CS input is LOW, and de-selected when CS is
high.
8
2
VCC
Supply Voltage
W
5
BRIEF DESCRIPTION
FN8183.6
December 16, 2009
X9317
Absolute Maximum Ratings
Thermal Information
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
RH, RW, RL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
Voltage on CS, INC, U/D and VCC
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Junction Temperature Under Bias . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Potentiometer Specifications
SYMBOL
VCC = Full Range, TA = Full Operating Temperature Range, unless otherwise stated.
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX
(Note 8) (Note 4) (Note 8)
UNIT
RTOTAL
End-to-end Resistance Tolerance
See “Ordering Information” beginning on
page 2 for values
-20
+20
%
VRH/RL
RH/RL Terminal Voltage
VSS = 0V
VSS
VCC
V
Power Rating
RTOTAL ≥ 10kΩ
10
mW
RTOTAL = 1kΩ
25
mW
RW
IW
Wiper Resistance
IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 5V
200
400
Ω
IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 2.7V
400
1000
Ω
+4.4
mA
Wiper Current (Note 5)
See “Test Circuit” on page 7
Noise (Note 7)
Ref: 1kHz
-4.4
Resolution
CH/CL/CW
(Note 5)
VCC
dBV
1
%
Absolute Linearity (Note 1)
V(RH) = VCC, V(RL) = 0V
-1
+1
MI
(Note 3)
Relative Linearity (Note 2)
V(RH) = VCC, V(RL) = 0V
-0.2
+0.2
MI
(Note 3)
RTOTAL Temperature Coefficient (Note 5) V(RH) = VCC, V(RL) = 0V
±300
ppm/°C
Ratiometric Temperature Coefficient
(Notes 5, 6)
±20
ppm/°C
10/10/25
pF
Potentiometer Capacitances
See “Equivalent Circuit” on page 7
Supply Voltage
X9317
4.5
5.5
V
X9317-2.7
2.7
5.5
V
MAX
(Note 8)
UNIT
DC Electrical Specifications
SYMBOL
-120
VCC = 5V ±10%, TA = Full Operating Temperature Range, unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
(Note 8)
TYP
(Note 4)
ICC1
VCC Active Current (Increment)
CS = VIL, U/D = VIL or VIH and
INC = VIL/VIH @ min. tCYC
RL, RH, RW not connected
80
µA
ICC2
VCC Active Current (Store)
(non-volatile write)
CS = VIH, U/D = VIL or VIH and INC = VIL
or VIH. RL, RH, RW not connected
400
µA
ISB
Standby Supply Current
CS ≥ VIH, U/D and INC = VIL
RL, RH, RW not connected
5
µA
ILI
CS, INC, U/D Input Leakage Current
VIN = VSS to VCC
-10
+10
µA
VIH
CS, INC, U/D Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D Input LOW Voltage
-0.5
VCC x 0.1
V
CIN (Note 5)
CS, INC, U/D Input Capacitance
6
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz
10
pF
FN8183.6
December 16, 2009
X9317
Endurance and Data Retention VCC = 5V ±10%, TA = Full Operating Temperature Range.
PARAMETER
MIN
UNIT
Minimum Endurance
100,000
Data changes per bit
Data Retention
100
Years
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI
V(RW(n)(expected)) = n(V(RH)-V(RL))/99 + V(RL), with n from 0 to 99.
2. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) - MI)]/MI.
3. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/99.
4. Typical values are for TA = +25°C and nominal supply voltage.
5. This parameter is not 100% tested.
6. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2) x 106], with T1 and T2 being 2 temperatures, and n from 0
to 99.
7. Measured with wiper at tap position 99, RL grounded, using test circuit.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Test Circuit
Equivalent Circuit
TEST POINT
AC Conditions of Test
RTOTAL
RH
CH
RW
FORCE
CURRENT
CL
CW
10pF
RL
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
25pF
10pF
RW
AC Electrical Specifications
VCC = 5V ±10%, TA = Full Operating Temperature Range, unless otherwise stated.
SYMBOL
tCl
PARAMETER
MIN
(Note 8)
TYP
(Note 4)
MAX
(Note 8)
UNIT
CS to INC Setup
50
ns
tlD (Note 5)
INC HIGH to U/D Change
100
ns
tDI (Note 5)
U/D to INC Setup
1
µs
tlL
INC LOW Period
960
ns
tlH
INC HIGH Period
960
ns
tlC
INC Inactive to CS Inactive
1
µs
tCPHS
CS Deselect Time (STORE)
10
ms
CS Deselect Time (NO STORE)
100
ns
tCPHNS
(Note 5)
tIW
tCYC
tR, tF
(Note 5)
tPU (Note 5)
tR VCC
(Note 5)
tWR
INC to RW Change
INC Cycle Time
1
2
Power-up to Wiper Stable
Store Cycle
7
µs
µs
INC Input Rise and Fall Time
VCC Power-up Rate
5
0.2
5
500
µs
5
µs
50
V/ms
10
ms
FN8183.6
December 16, 2009
X9317
Power-up and Down Requirements
The recommended power-up sequence is to apply VCC/VSS
first, then the potentiometer voltages. During power-up, the
data sheet parameters for the DCP do not fully apply until
1ms after VCC reaches its final value. The VCC ramp spec is
always in effect. In order to prevent unwanted tap position
changes, or an inadvertent store, bring the CS and INC high
before or concurrently with the VCC pin on power-up.
AC Timing
CS
tCYC
tCI
tIL
tIH
tCPHNS
tCPHS
tIC
90%
90%
10%
INC
tID
tDI
tF
tR
U/D
tIW
MI
RW
(3)
Typical Performance Characteristic
0
-50
PPM
-100
-150
-200
-250
-300
-350
-55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105115 125
TEMPERATURE (°C)
FIGURE 1. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
8
FN8183.6
December 16, 2009
X9317
Pin Descriptions
Pin Names
RH AND RL
SYMBOL
The high (RH) and low (RL) terminals of the X9317 are
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of RL and RH references the
relative position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
RW
Rw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω.
UP/DOWN (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
INCREMENT (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
CHIP SELECT (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete, the X9317 will be placed in
the low power standby mode until the device is selected
once again.
Pin Configuration
DIP/SOIC/MSOP
8
VCC
7
CS
3
6
RL
4
5
RW
INC
1
U/D
2
RH
VSS
X9317
DESCRIPTION
RH
High terminal
RW
Wiper terminal
RL
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
INC
Increment control input
CS
Chip select control input
Principles of Operation
There are three sections of the X9317: the control section,
the nonvolatile memory, and the resistor array. The control
section operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
The contents of the counter can be stored in nonvolatile
memory and retained for future use. The resistor array is
comprised of 99 individual resistors connected in series.
Electronic switches at either end of the array and between
each resistor provide an electrical connection to the wiper
pin, RW.
The wiper acts like its mechanical equivalent and does not
move beyond the first or last position. That is, the counter
does not wrap around when clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by
a significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
Instructions and Programming
TSSOP
CS
1
8
RL
VCC
2
7
RW
INC
3
6
VSS
U/D
4
5
RH
X9317
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW, the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a 7-bit
counter. The output of this counter is decoded to select one
of one hundred wiper positions along the resistive array.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
9
FN8183.6
December 16, 2009
X9317
The system may select the X9317, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC LOW while
taking CS HIGH. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle
recalls the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position to nonvolatile
memory
X
X
Standby
L
X
No store, return to standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down (not recommended)
H
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:
1. the variability and reliability of a solid-state potentiometer,
2. the flexibility of computer-based digital controls, and
3. the retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data.
10
FN8183.6
December 16, 2009
X9317
Basic Configurations of Electronic Potentiometers
VREF
VREF
RH
RW
RL
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
BUFFERED REFERENCE VOLTAGE
SINGLE SUPPLY INVERTING AMPLIFIER
CASCADING TECHNIQUES
R1
+V
+V
+V
R1
+5V
RW
VREF
+
VS
LMC7101
VOUT
-
+5V
R2
X
RW
-
100k
+V
VO
+
+5V
LMC7101
(a)
VOLTAGE REGULATOR
VIN
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
R1
LT311A
+5V
100kΩ
VO
+
+
Iadj
10kΩ
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
+5V
10kΩ
}
LMC7101
10kΩ
VO
}
R2
11
VO = (R2/R1)VS
(b)
OFFSET VOLTAGE ADJUSTMENT
VO (REG)
317
100k
RW
VOUT = VW/RW
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
FN8183.6
December 16, 2009
X9317
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L1
SEATING
PLANE
C
0.20 (0.008)
C
a
CL
E1
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
-B-
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.20 (0.008)
MIN
A
L1
-A-
SIDE VIEW
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
12
FN8183.6
December 16, 2009
X9317
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
SYMBOL
3
0.05(0.002)
-A-
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
GAUGE
PLANE
-B1
M8.173
B M
SEATING PLANE
L
A
D
-C-
α
e
A1
b
0.10(0.004) M
0.25
0.010
A2
c
0.10(0.004)
C A M
B S
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
α
8
0o
8
7
8o
Rev. 1 12/00
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
13
FN8183.6
December 16, 2009
X9317
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
14
FN8183.6
December 16, 2009
X9317
Plastic Dual-In-Line Packages (PDIP)
E
D
A2
SEATING
PLANE
L
N
A
PIN #1
INDEX
E1
c
e
b
A1
NOTE 5
1
eA
eB
2
N/2
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
TOLERANCE
A
0.210
0.210
0.210
0.210
0.210
MAX
A1
0.015
0.015
0.015
0.015
0.015
MIN
A2
0.130
0.130
0.130
0.130
0.130
±0.005
b
0.018
0.018
0.018
0.018
0.018
±0.002
b2
0.060
0.060
0.060
0.060
0.060
+0.010/-0.015
c
0.010
0.010
0.010
0.010
0.010
+0.004/-0.002
D
0.375
0.750
0.750
0.890
1.020
±0.010
E
0.310
0.310
0.310
0.310
0.310
+0.015/-0.010
E1
0.250
0.250
0.250
0.250
0.250
±0.005
e
0.100
0.100
0.100
0.100
0.100
Basic
eA
0.300
0.300
0.300
0.300
0.300
Basic
eB
0.345
0.345
0.345
0.345
0.345
±0.025
L
0.125
0.125
0.125
0.125
0.125
±0.010
N
8
14
16
18
20
Reference
NOTES
1
2
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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15
FN8183.6
December 16, 2009