X9015
®
Low Noise, Low Power, Volatile
Data Sheet
August 31, 2006
Single Digitally Controlled (XDCP™)
Potentiometer
FN8157.5
Features
• 32 taps
The Intersil X9015 is a 32 tap potentiometer that is volatile.
The device consists of a string of 31 resistors that can be
programmed to connect the RW/VW wiper output with any of
the nodes between the connecting resistors. The connection
point of the wiper is determined by information
communicated to the device on the 3-wire port. The 3-wire
port changes the tap position by a falling edge on the
increment pin. The direction the wiper moves is determined by
the state of the up/down pin. The wiper position at power up is
Tap #15.
• Three-wire up/down serial interface
• VCC = 2.7V–5V
• Operating ICC = 50µA max.
• Standby current = 1µA max.
• RTOTAL = 10kΩ, 50kΩ
• Packages 8 Ld SOIC, 8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
The X9015 can be used in a wide variety of applications that
require a digitally controlled variable resistor to set analog
values.
Pinout
SOIC/MSOP
INC
1
8
VCC
U/D
2
7
CS
RH/VH
3
6
RL/VL
VSS
4
5
RW/VW
X9015
Block Diagram
U/D
INC
CS
VCC (Supply Voltage)
Control
29
One 28
of
Thirty
Two
Decoder
RW/VW
Device Select
(CS)
RH/VH
31
30
RH/VH
Up/Down
(U/D)
Increment
(INC)
5-Bit
Up/Down
Counter
RL/VL
Transfer
Gates
Resistor
Array
2
VSS (Ground)
General
VCC
VSS
Control
Circuitry
1
0
RL/VL
RW/VW
Detailed
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9015
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS (V)
RTOTAL (kΩ)
TEMPERATURE
RANGE (°C)
5 ±10%
10
0 to +70
8 Ld SOIC
Tape and Reel
M8.15
0 to +70
8 Ld SOIC (Pb-free)
Tape and Reel
M8.15
0 to +70
8 Ld MSOP
M8.118
8 Ld MSOP (Pb-free)
M8.118
PACKAGE
PKG.
DWG. #
X9015WS8T1
X9015W
X9015WS8ZT1 (Note)
X9015W Z
X9015UM8
ABB
X9015UM8Z (Note)
DCF
0 to +70
X9015UM8I*
ABD
-40 to +85
8 Ld MSOP
M8.118
X9015UM8IZ* (Note)
DCD
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9015US8*
X9015U
0 to +70
8 Ld SOIC
M8.15
X9015US8Z* (Note)
X9015U Z
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9015US8I*
X9015U I
-40 to +85
8 Ld SOIC
M8.15
X9015US8IZ* (Note)
X9015U Z I
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
X9015WS8-2.7*
X9015W F
0 to +70
8 Ld SOIC
M8.15
X9015WS8Z-2.7* (Note)
X9015W ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9015UM8-2.7*
ABC
0 to +70
8 Ld MSOP
M8.118
X9015UM8Z-2.7* (Note)
DCF
0 to +70
8 Ld MSOP (Pb-free)
M8.118
X9015UM8I-2.7*
ABE
-40 to +85
8 Ld MSOP
M8.118
X9015UM8IZ-2.7* (Note)
DCE
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
X9015US8-2.7*
X9015U F
0 to +70
8 Ld SOIC
M8.15
X9015US8Z-2.7* (Note)
X9015U ZF
0 to +70
8 Ld SOIC (Pb-free)
M8.15
X9015US8I-2.7*
X9015U G
-40 to +85
8 Ld SOIC
M8.15
X9015US8IZ-2.7* (Note)
X9015U ZG
-40 to +85
8 Ld SOIC (Pb-free)
M8.15
50
2.7-5.5
10
50
* Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN8157.5
August 31, 2006
X9015
Pin Descriptions
RH/VH and RL/VL
The high (RH/VH) and low (RL/VL) terminals of the X9015 are
equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is VSS and the
maximum is VCC. The terminology of RL/VL and RH/VH
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input, and not
the voltage potential on the terminal.
RW/VW
RW/Vw is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω at
VCC=5V. At power up the wiper position is at Tap #15.
(VL/RL=Tap #0).
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the tap position is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the U/D
input.
Chip Select (CS)
The device is selected when the CS input is LOW. When CS
is returned HIGH while the INC input is also HIGH the X9015
will be placed in the low power standby mode until the device
is selected once again.
Pin Names
SYMBOL
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
connected to the wiper for tIW (INC to VW change). The
RTOTAL value for the device can temporarily be reduced by a
significant amount if the wiper is moved several positions.
When the device is powered-down, the wiper position is lost.
When power is restored, the wiper is set to Tap #15.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a five bit counter.
The output of this counter is decoded to select one of thirty
two wiper positions along the resistive array.
The system may select the X9015, move the wiper and
deselect the device. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle.
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Mode Selection
CS
High terminal
RW/VW
Wiper terminal
Low terminal
VSS
Ground
VCC
Supply voltage
U/D
Up/Down control input
INC
Increment control input
CS
Chip select control input
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Standby mode
H
X
X
Standby mode
L
L
X
Normal mode
L
H
Wiper Up (not recommended)
L
L
Wiper Down (not recommended)
DESCRIPTION
RH/VH
RL/VL
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
Principles Of Operation
There are two sections of the X9015: the input control,
counter and decode section; and the resistor array. The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a single electronic
switch connecting a point on the resistor array to the wiper
output. The resistor array is comprised of 31 individual
resistors connected in series.
3
FN8157.5
August 31, 2006
X9015
Absolute Maximum Ratings
Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, VH, VL and
VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
ΔV = |VH–VL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . +300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7.5mA
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (VCC)
X9015. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9015-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
)
Potentiometer Specifications Over recommended operating conditions unless otherwise stated
SYMBOL
RTOTAL
PARAMETER
TEST CONDITIONS/NOTES
End to End Resistance Variation
MIN.
TYP.
MAX.
UNIT
–20
+20
%
VVH
VH/RH Terminal Voltage
0
VCC
V
VVL
VL/RL Terminal Voltage
0
VCC
V
10
mW
Power Rating
RTOTAL ≤1kΩ
RW
Wiper Resistance
IW = 1mA, VCC = 5V
200
400
Ω
RW
Wiper Resistance
IW = 1mA, VCC = 2.7V
400
1000
Ω
IW
Wiper Current
3.75
mA
-3.75
Noise
Ref: 1kHz
Resolution
Absolute Linearity (Note 1)
Vw(n)(actual)–Vw(n)(expected)
Relative Linearity (Note 2)
Vw(n+1)–[Vw(n)+MI]
RTOTAL Temperature Coefficient
-120
dBV
3
%
-1
+1
MI (Note 3)
-0.2
+0.2
MI (Note 3)
±300
Ratiometric Temperature Coefficient
CH/CL/CW
Potentiometer Capacitances
ppm/°C
±20
See circuit #3
10/10/25
ppm/°C
pF
Power Up and Down Requirements
The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins
provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate spec is
always in effect.
NOTES:
1. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual)–Vw(n)(expected)) = ±1 Ml Maximum.
2. Relative Linearity is a measure of the error in step size between
taps = VW(n+1) – [Vw(n) + Ml] = ±0.2 Ml.
3. 1 Ml = Minimum Increment = RTOT/31.
4. Typical values are for TA = +25°C and nominal supply voltage.
5. This parameter is periodically sampled and not 100% tested.
4
FN8157.5
August 31, 2006
X9015
)
D.C. Operating Specifications Over recommended operating conditions unless otherwise specified
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(Note 4)
MAX.
UNITS
ICC1
VCC active current (increment)
CS = VIL, U/D = VIL or VIH and
INC = 0.4V @ max. tCYC
50
µA
ICC2
VCC active current (Store) (EEPROM
Store)
CS = VIH, U/D = VIL or VIH and
INC = VIH @ max. tWR
400
µA
ISB
Standby supply current
CS = VCC – 0.3V, U/D and
INC = VSS or VCC – 0.3V
1
µA
ILI
CS, INC, U/D input leakage current
VIN = VSS to VCC
±10
µA
VIH
CS, INC, U/D input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D input LOW voltage
-0.5
VCC x 0.1
V
CIN (Note 5)
CS, INC, U/D input capacitance
10
pF
TEST CIRCUIT #1
VCC = 5V, VIN = VSS, TA = 25°C,
f = 1MHz
TEST CIRCUIT #2
CIRCUIT #3 SPICE MACRO MODEL
RTOTAL
VH/RH
VH/RH
Test Point
RH
CW
CH
VS
Test Point
VW/RW
V
VL
L/RL
VL/RL
VW/RW
VW
Force
Current
CL
RL
10pF
25pF
10pF
RW
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
A.C. Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
5
FN8157.5
August 31, 2006
X9015
A.C. Operating Specifications Over recommended operating conditions unless otherwise specified
SYMBOL
PARAMETER
MIN.
TYP. (Note 6)
MAX.
UNIT
tCl
CS to INC setup
100
ns
tlD
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
2.9
µs
tlL
INC LOW period
1
µs
tlH
INC HIGH period
1
µs
tlC
INC inactive to CS inactive
1
µs
tCPH
CS deselect time (NO STORE)
100
ns
tCPH
CS deselect time (STORE)
10
ms
tIW
INC to Vw change
tCYC
1
INC cycle time
tR, tF (Note 7)
tPU(Note 7)
5
4
µs
INC input rise and fall time
Power up to wiper stable
tR VCC(Note 7) VCC power-up rate
tWR
µs
0.2
Store cycle
5
500
µs
5
µs
50
V/ms
10
ms
A.C. Timing
CS
tCYC
tCI
tIL
tIH
(store)
tCPH
tIC
90%
INC
90%
10%
tID
tDI
tF
tR
U/D
tIW
MI
VW
(8)
NOTES:
6. Typical values are for TA = +25°C and nominal supply voltage.
7. This parameter is periodically sampled and not 100% tested.
8. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.
6
FN8157.5
August 31, 2006
X9015
Performance Characteristics (Typical)
0
-10
-20
-30
NOISE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
10
20
30
40
50
60
70
80
90
100
110 120
130 140
FREQUENCY (kHz)
150 160
170 180
190 200
FIGURE 1. TYPICAL NOISE
10000
9800
9600
RTOTAL
9400
9200
9000
8800
8600
8400
8200
8000
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
TEMPERATURE
75
85
105 115 125 C
95
FIGURE 2. TYPICAL RTOTAL VS. TEMPERATURE
0
-50
-100
-150
PPM
-200
-250
-300
-350
-55
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
TEMPERATURE
75
85
95
105
115
125
C
FIGURE 3. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
7
FN8157.5
August 31, 2006
X9015
Performance Characteristics (Typical) (Continued)
800
700
600
400
300
200
100
0
0
2
4
6
8
10
12
14
18
16
TAP
20
22
24
26
28
30
32
VCC = 2.7V
FIGURE 4. TYPICAL WIPER RESISTANCE
40.0%
ABSOLUTE% ERROR
30.0%
20.0%
10.0%
0.0%
-10.0%
-20.0%
-30.0%
-40.0%
0
3
6
9
12
15
18
21
24
27
30
Tap
FIGURE 5. TYPICAL ABSOLUTE% ERROR PER TAP POSITION
20.0%
15.0%
RELATIVE% ERROR
RW (Ω)
500
10.0%
5.0%
0.0%
-5.0%
-10.0%
-15.0%
-20.0%
0
3
6
9
12
15
18
21
24
27
30
TAP
FIGURE 6. TYPICAL RELATIVE% ERROR PER TAP POSITION
8
FN8157.5
August 31, 2006
X9015
Applications Information
Electronic digitally controlled potentiometers provide two powerful application advantages: (1) the variability and reliability of a
solid-state potentiometer, and (2) the flexibility of computer-based digital controls.
Basic Configurations of Electronic Potentiometers
VR
VR
VH/RH
VW/RW
VL/RL
I
THREE-TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO-TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
Buffered Reference Voltage
Noninverting Amplifier
Cascading Techniques
R1
+V
+5V
+V
+V
VS
+5V
VW/RW
VREF
VOUT
–
VO
–
OP-07
+
LM308A
+
–5V
X
VW/RW
R2
+V
–5V
R1
VW/RW
VOUT = VW
(a)
VOLTAGE REGULATOR
VIN
VO = (1+R2/R1)VS
OFFSET VOLTAGE ADJUSTMENT
VO (REG)
317
(b)
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
R1
LT311A
–
100kΩ
+
–
VO
+
Iadj
10kΩ
10kΩ
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
+12V
}
10kΩ
}
TL072
R2
VO
R1
R2
VUL = {R1/(R1+R2)} VO(max)
VLL = {R1/(R1+R2)} VO(min)
-12V
(FOR ADDITIONAL CIRCUITS, SEE AN115.)
9
FN8157.5
August 31, 2006
X9015
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
α
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
1.27 BSC
H
N
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
10
FN8157.5
August 31, 2006
X9015
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X θ
0.25
(0.010)
R1
R
GAUGE
PLANE
A
SEATING
PLANE -C-
A2
A1
b
-He
D
0.10 (0.004)
4X θ
L1
SEATING
PLANE
C
0.20 (0.008)
C
a
CL
E1
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
0.20 (0.008)
MIN
A
L1
-A-
SIDE VIEW
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
α
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
-B-
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN8157.5
August 31, 2006