LOGIC LF3338

LF3338
LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
8-Bit Vertical Digital Image Filter
DEVICES INCORPORATED
FEATURES
❑
❑
❑
❑
❑
DESCRIPTION
83 MHz Data Rate
8-bit Data and 12-bit Coefficients
Supports Interleaved Data Streams
Cascadable for More Filter Taps
Seven 3K x 8-bit, Dynamic Programmable Two-Mode Line Buffers
❑ On-board Memory for 256
Coefficient Sets
❑ LF InterfaceTM Allows All 256
Coefficient Sets to be Updated
Within Vertical Blanking
❑ Selectable 16-bit Data Output with
User-Defined Rounding and
Limiting
❑ Separate Input Port for Odd and
Even Field Filtering
❑
❑
❑
❑
8 Filter Taps
3.3 Volt Power Supply
5 Volt Tolerant I/O
Purchase Description
The LF3338 is a lower cost version of
the 12-bit LF3330 and is suited for
multimedia and special effects systems,
projectors, plasma display panels, scan
converters, set-top boxes, and other
consumer applications.
This device filters digital images in
the vertical dimension at real-time
video rates. Input data is 8 bits and
coefficient data is 12 bits and both are
in two’s complement format. The
output is also in two’s complement
format and may be rounded to 16 bits.
The filter is an 8-tap FIR filter with all
required line buffers contained onchip. The line buffers can store video
lines with lengths from 4 to 3076
pixels. Multiple LF3338s can be
cascaded together to create larger
vertical filters.
Due to the length of the line buffers,
interleaved data can be fed directly
into the device and filtered without
separating the data into individual
data streams. The number of interleaved data sets that the device can
handle is limited only by the length of
the on-chip line buffers. If the interleaved video line has 3076 data values
or less, the filter can handle it.
The LF3338 contains enough on-board
memory to store 256 coefficient sets.
The LF InterfaceTM allows all 256
coefficient sets to be updated within
vertical blanking.
Selectable 16-bit data output with
user-defined rounding and limiting
minimizes the constraints put on
coefficient sets for various filter
implementations.
LF3338 BLOCK DIAGRAM
8
DIN7-0
3K LINE BUFFER
3K LINE BUFFER
8
3K LINE BUFFER
VB7-0
3K LINE BUFFER
8-TAP VERTICAL FILTER
256 COEFFICIENT SET STORAGE
3K LINE BUFFER
32
ROUND
SELECT
LIMIT
CIRCUITRY
16
DOUT15-0
OED
3K LINE BUFFER
3K LINE BUFFER
8
COUT7-0
OEC
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2
CLK
PAUSE
LD
CF11-0
COUT7-0
12
8
8
8
CONFIGURATION AND
CONTROL REGISTERS
LF
INTERFACE
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
3K Line Buffer
8
8
8
8
8
8
8
8
Coef Bank 0
12
12
Coef Bank 7
Coef Bank 1
12
12
Coef Bank 6
Coef Bank 2
12
12
Coef Bank 5
Coef Bank 3
12
12
Coef Bank 4
20
20
20
20
20
20
20
20
22
22
ACC
32
"0"
4
RSL3-0
16
OED
16
DOUT15-0
DEVICES INCORPORATED
OEC
VB7-0
DIN7-0
SHEN
8
ROUND
CA7-0
LIMIT
FIGURE 1.
SELECT
CEN
LF3338
8-Bit Vertical Digital Image Filter
LF3338 FUNCTIONAL BLOCK DIAGRAM
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LF3338
DEVICES INCORPORATED
SIGNAL DEFINITIONS
8-Bit Vertical Digital Image Filter
FIGURE 2.
INPUT FORMATS
Power
Input Data
VCC and GND
7 6 5
–27 26 25
+3.3 V power supply. All pins must be
connected.
Coefficient Data
2 1 0
22 21 20
11 10 9
–20 2–1 2–2
(Sign)
2 1 0
2–9 2–10 2–11
(Sign)
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
TABLE 1. OUTPUT FORMATS
SLCT4-0
S15 S14 S13
00000
F15 F14 F13
Inputs
00001
F16 F15 F14
DIN7-0 — Data Input
00010
F17 F16 F15
DIN7-0 is the 8-bit registered data input
port. Data is latched on the rising edge
of CLK.
VB7-0 — Field Filtering Data Input
VB7-0 is the 8-bit registered data input
port used only when implementing
Odd and Even Field Filtering (see
Functional Description section for a full
discussion). Data is latched on the
rising edge of CLK.
CF11-0 — Coefficient Input
CF11-0 is used to load data into the
coefficient banks and configuration/
control registers. Data present on
CF11-0 is latched into the LF InterfaceTM
on the rising edge of CLK when LD is
LOW (see the LF InterfaceTM section for
a full discussion).
CA7-0 — Coefficient Address
CA7-0 determines which row of data in
the coefficient banks is fed to the
multipliers. CA7-0 is latched into the
Coefficient Address Register on the
rising edge of CLK when CEN is LOW.
Outputs
DOUT15-0 — Data Output
DOUT15-0 is the 16-bit registered data
output port.
·
·
·
·
·
·
·
·
·
···
···
···
···
·
·
·
01110
F29 F28 F27
01111
F30 F29 F28
10000
F31 F30 F29
···
···
···
COUT 7-0 — Cascade Data Output
COUT 7-0 is a 8-bit cascade output
port. COUT 7-0 on one device
should be connected to DIN 7-0 of
another LF3338.
S8
S7
F8
F7
F9
F8
F10
F9
·
·
·
·
·
·
···
···
···
···
F22 F21
F23 F22
F24 F23
···
···
···
S2
S1
S0
F2
F1
F0
F3
F2
F1
F4
F3
F2
·
·
·
·
·
·
·
·
·
F16 F15 F14
F17 F16 F15
F18 F17 F16
FIGURE 3. ACCUMULATOR FORMAT
Accumulator Output
31 30 29
–216 215 214
2 1 0
2–13 2–14 2–15
(Sign)
Controls
LD — Coefficient Load
When LD is LOW, data on CF 11-0
is latched into the LF Interface TM
on the rising edge of CLK. When
LD is HIGH, data can not be
latched into the LF Interface TM.
When enabling the LF Interface TM
for data input, a HIGH to LOW
transition of LD is required in
order for the input circuitry to
function properly. Therefore, LD
must be set HIGH immediately
after power up to ensure proper
operation of the input circuitry
(see the LF Interface TM section for
a full discussion).
PAUSE — LF InterfaceTM Pause
When PAUSE is HIGH, the LF
InterfaceTM loading sequence is halted
until PAUSE is returned to a LOW
state. This effectively allows the user
to load coefficients and control
registers at a slower rate than the
master clock (see the LF InterfaceTM
section for a full discussion).
CEN — Coefficient Address Enable
When CEN is LOW, data on CA7-0 is
latched into the Coefficient Address
Register on the rising edge of CLK.
When CEN is HIGH, data on CA7-0 is
not latched and the register’s contents
will not be changed.
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LF3338
DEVICES INCORPORATED
CONFIGURATION REGISTER 0 – ADDRESS 200H
BITS
FUNCTION
DESCRIPTION
11-0
Line Buffer Length
See Line Buffer Description Section
1
2
3
11-4
TABLE 4.
32
FUNCTION
DESCRIPTION
Line Buffer Mode
0 : Delay Mode
1 : Recirculate Mode
Line Buffer Load
R0
CONFIGURATION REGISTER 1 – ADDRESS 201H
32
RND
0 : Normal Load
1 : Parallel Load
Odd and Even Field
0 : VB Port Disabled
Filtering Port Enable
1 : VB Port Enabled
Odd and Even Field
0 : VB Line Buffer Disabled
Filtering Line Buffer Enable
1 : VB Line Buffer Enabled
Reserved
Must be set to “0”
32
5
SELECT
CONFIGURATION REGISTER 2 – ADDRESS 202H
BITS
FUNCTION
DESCRIPTION
0
Limit Enable
0 : Limiting Disabled
1 : Limiting Enabled
Reserved
16
32
LIMIT
Must be set to “0”
L15
11-1
4
R15
0
DATA IN
S15
BITS
RSL3-0
L0
TABLE 3.
FIGURE 4. RSL CIRCUITRY
S0
TABLE 2.
8-Bit Vertical Digital Image Filter
TABLE 5.
BITS
CONFIGURATION REGISTER 3 – ADDRESS 203H
FUNCTION
DESCRIPTION
Cascade Mode
0 : First Device
1 : Cascaded Device
Reserved
Must be set to “0”
RSL CIRCUITRY
0
11-1
ACC — Accumulator Control
When ACC is HIGH, the accumulator
is enabled for accumulation and the
accumulator output register is
disabled for loading. When ACC is
LOW, no accumulation is performed
and the accumulator output register
is enabled for loading. ACC is
latched on the rising edge of CLK.
SHEN — Shift Enable
SHEN enables or disables the
loading of data into the input/
cascade registers and the line
buffers. When SHEN is LOW, data
is loaded into the input/cascade
16
DATA OUT
registers and shifted through the
line buffers on the rising edge of
CLK. When SHEN is HIGH, data
can not be loaded into the input/
cascade registers or shifted through
the line buffers and their contents
will not be changed.
RSL3-0 — Round/Select/Limit Control
RSL3-0 determines which of the
sixteen user-programmable round/
select/limit registers are used in the
round/select/limit circuitry. A
value of 0 on RSL3-0 selects round/
select/limit register 0. A value of 1
selects round/select/limit register 1
and so on. RSL3-0 is latched on the
rising edge of CLK (see the round,
select, and limit sections for a
complete discussion).
OED — DOUT Output Enable
When OED is LOW, DOUT15-0 is
enabled for output. When OED is
HIGH, DOUT15-0 is placed in a
high-impedance state.
OEC — COUT Output Enable
When OEC is LOW, COUT7-0 is
enabled for output. When OEC is
HIGH, COUT 7-0 is placed in a highimpedance state.
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
FUNCTIONAL DESCRIPTION
Line Buffers
The maximum delay length of each line
buffer is 3076 cycles and the minimum
is 4 cycles. Configuration Register 0
(CR0) determines the delay length of
the line buffers. The line buffer length
is equal to the value of CR0 plus 4. A
value of 0 for CR0 sets the line buffer
length to 4. A value of 3072 for CR0
sets the line buffer length to 3076. Any
values for CR0 greater than 3072 are not
valid.
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register 1
determines which mode the line buffers
are in. In delay mode, the data input to
the line buffer is delayed by an amount
determined by CR0. In recirculate
mode, the output of the line buffer is
routed back to the input of the line
buffer allowing the line buffer contents
to be read multiple times.
Bit 1 of Configuration Register 1 allows
the line buffers to be loaded in parallel.
When Bit 1 is “1”, the input register
(DIN7-0) loads all seven line buffers in
FIGURE 5.
Odd and Even Field Filtering
The LF3338 is capable of odd and even
field filtering. Bit 2 of Configuration
Register 1 enables the VB Data Input
port required for odd and even field
filtering. Bit 3 of the same configuration register enables the line buffer in
the VB Data path. Line buffer length is
set to the length written to Configuration Register 0. If line buffer parallel
load is enabled and odd and even field
filtering is enabled, the data for the VB
line buffer comes from the VB Data
Input port.
Interleaved Data
The LF3338 is capable of handling
interleaved data. The number of data
sets it can handle is determined by the
number of data values contained in a
video line. If the interleaved video line
has 3076 data values or less, the LF3338
can handle it no matter how many data
sets are interleaved together.
Cascading
A cascade port is provided to allow
cascading of multiple devices for
more filter taps (see Figure 5).
COUT7-0 of one device should be
connected to DIN 7-0 of another
device. As many LF3338s as desired
may be cascaded together. However, the outputs of the LF3338s
must be added together with external adders.
The first line buffer on a cascaded
device must have its length shortened by two delays. This is to
account for the added delays of the
input register on the device and the
cascade output register from the
previous LF3338. If Bit 0 of Configuration Register 3 is set to “1”,
the length of the first line buffer will
be reduced by two. This will make
its effective length the same as the
other line buffers on the device. If
Bit 0 of Configuration Register 3 is
set to “0”, the length of the first line
buffer will be the same as the other
line buffers. When cascading
devices, the first LF3338 should
have Bit 0 of Configuration Register
MULTIPLE LF3338S CASCADED TOGETHER
LF3338
8
DIN
parallel. This allows all the line buffers
to be preloaded with data in the
amount of time it normally takes to
load a single line buffer.
LINE BUFFERS
LF3338
COUT
DIN
LINE BUFFERS
LF3338
COUT
DIN
LINE BUFFERS
LF3338
COUT
DIN
LINE BUFFERS
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
VERTICAL FILTER
RSL
CIRCUIT
RSL
CIRCUIT
RSL
CIRCUIT
RSL
CIRCUIT
LF3347
25
25
RSL
CIRCUIT
16
DATA OUT
29 TAP RESULT
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
3 set to “0”. Any LF3338s cascaded
after the first LF3338 should have
Bit 0 of Configuration Register 3 set
to “1”. When not cascading, Bit 0 of
Configuration Register 3 should be
set to “0”.
It is important to note that the first
multiplier on all cascaded devices
should not be used. This is because
the first multiplier does not have a
line buffer in front of it. The coefficient value sent to the first multiplier on a cascaded device should be
“0”.
Rounding
The filter output may be rounded by
adding the contents of one of the
sixteen round registers to the filter
output (see Figure 4). Each round
register is 32 bits wide and user-
programmable. This allows the filter’s
output to be rounded to any precision
required. Since any 32-bit value may
be programmed into the round
registers, the device can support
complex rounding algorithms as well
as standard half-LSB rounding. RSL3-0
determines which of the sixteen round
registers are used in the rounding
operation. A value of 0 on RSL3-0
selects round register 0. A value of 1
selects round register 1 and so on.
RSL3-0 may be changed every clock
cycle if desired. This allows the
rounding algorithm to be changed
every clock cycle. This is useful when
filtering interleaved data. If rounding
is not desired, a round register should
be loaded with 0 and selected as the
register used for rounding. Round
register loading is discussed in the
LF Interface TM section.
Output Select
The word width of the filter output
is 32 bits. However, only 16 bits
may be sent to DOUT15-0. The select
circuitry determines which 16 bits
are passed (see Table 1). There are
sixteen select registers which control
the select circuitry. Each select
register is 5 bits wide and userprogrammable. RSL3-0 determines
which of the sixteen select registers
are used in the select circuitry.
Select register 0 is chosen by loading
a 0 on RSL3-0. Select register 1 is
chosen by loading a 1 on RSL3-0 and
so on. RSL3-0 may be changed every
clock cycle if desired. This allows
the 16-bit window to be changed
every clock cycle. This is useful
when filtering interleaved data.
Select register loading is discussed
in the LF Interface TM section.
FIGURE 6. COEFFICIENT BANK LOADING SEQUENCE
COEFFICIENT SET 1
COEFFICIENT SET 2
COEFFICIENT SET 3
CLK
W1
W2
W3
LD
CF11-0
ADDR1
COEF0
COEF7
ADDR2
COEF0
COEF7
ADDR3
COEF0
COEF7
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
FIGURE 7. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE
CONFIG REG
SELECT REG
ROUND REGISTER
LIMIT REGISTER
CLK
W1
W2
W3
W4
LD
CF11-0
ADDR1
DATA1
ADDR2
DATA1
ADDR3
DATA1
DATA2
DATA3
DATA4
ADDR4
DATA1
DATA2
DATA3
DATA4
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
Limiting
An output limiting function is
provided for the output of the
filter. The limit registers determine the valid range of output
values when limiting is enabled
(Bit 0 in Configuration Register 2).
There are sixteen 32-bit limit
registers. RSL 3-0 determines
which limit register is used during
the limit operation. A value of 0
on RSL 3-0 selects limit register 0.
A value of 1 selects limit register 1
and so on. Each limit register
contains both an upper and lower
limit value. If the value fed to the
limiting circuitry is less than the
lower limit, the lower limit value
is passed as the filter output. If
the value fed to the limiting
circuitry is greater than the upper
limit, the upper limit value is
passed as the filter output. RSL 3-0
may be changed every clock cycle
if desired. This allows the limit
range to be changed every clock
cycle. This is useful when filtering
interleaved data. When loading
limit values into the device, the
upper limit must be greater than
the lower limit. Limit register
loading is discussed in the LF
Interface TM section.
Configuration and Control Registers
Coefficient Banks
There are sixteen select registers.
Each select register is 5 bits wide.
RSL3-0 determines which select
register is used for the select circuitry.
The coefficient banks store the
coefficients which feed into the
multipliers in the filter. There is a
separate bank for each multiplier.
Each bank can hold 256 12-bit
coefficients. The banks are loaded
using the LF InterfaceTM. Coefficient
bank loading is discussed in the
LF Interface TM section.
The configuration registers determine how the LF3338 operates.
Tables 2 through 5 show the formats
of the four configuration registers.
There are three types of control
registers: round, select, and limit.
There are sixteen round registers.
Each round register is 32 bits wide.
RSL3-0 determines which round
register is used for rounding.
There are sixteen limit registers.
Each limit register is 32 bits wide
and stores both an upper and lower
limit value. The lower limit is
stored in bits 15-0 and the upper
FIGURE 8. COEFFICIENT BANK LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
COEFFICIENT SET 1
CLK
W1
PAUSE
LD
CF11-0
ADDR1
COEF0
COEF1
COEF7
W1: Configuration Register loaded with new data on this rising clock edge.
FIGURE 9. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
CONFIGURATION REGISTER
SELECT REGISTER
CLK
W2
W1
PAUSE
LD
CF11-0
ADDR1
DATA1
ADDR2
DATA1
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
limit is stored in bits 31-16. RSL3-0
determines which limit register is
used for limiting when limiting is
enabled. Configuration and control
register loading is discussed in the
LF Interface TM section.
LF InterfaceTM
The LF InterfaceTM is used to load
data into the coefficient banks and
configuration/control registers. LD
is used to enable and disable the
LF InterfaceTM. When LD goes LOW,
the LF InterfaceTM is enabled for data
input. The first value fed into the
interface on CF11-0 is an address
which determines what the interface
is going to load. The three most
FIGURE 10. ROUND REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
ROUND REGISTER
CLK
W1
PAUSE
LD
ADDR1
CF11-0
DATA1
DATA2
DATA3
DATA4
W1: Round Register loaded with new data on this rising clock edge.
FIGURE 11. LIMIT REGISTER LOADING SEQUENCE WITH PAUSE IMPLEMENTATION
LIMIT REGISTER
CLK
W1
PAUSE
LD
CF11-0
ADDR1
DATA1
DATA2
DATA3
DATA4
W1: Limit Register loaded with new data on this rising clock edge.
TABLE 10.
COEFFICIENT BANK LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1st Word - Address
0
0
0
0
0
0
0
0
1
0
1
0
2nd Word - Bank 0
0
0
1
0
0
0
0
1
0
0
0
0
3rd Word - Bank 1
0
1
0
1
0
1
0
0
0
0
1
1
4th Word - Bank 2
1
1
0
0
0
1
1
1
0
1
1
0
5th Word - Bank 3
1
0
0
1
1
1
1
0
0
0
1
1
6th Word - Bank 4
0
1
1
1
0
0
0
0
0
0
0
1
7th Word - Bank 5
1
0
0
0
0
0
1
1
0
0
1
0
8th Word - Bank 6
1
1
1
1
0
0
1
0
0
0
0
0
9th Word - Bank 7
0
0
0
1
0
1
0
0
0
0
1
1
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
significant bits (CF11-9) determine if
the LF InterfaceTM will load coefficient
banks or configuration/control
registers (see Table 6). The nine least
significant bits (CF8-0) are the address
for whatever is to be loaded (see
Tables 7 through 9). For example, to
load address 15 of the coefficient
banks, the first data value into the
LF InterfaceTM should be 00FH. To
load limit register 10, the first data
value should be E0AH. The first
address value should be loaded into
the interface on the same clock cycle
that latches the HIGH to LOW
transition of LD (see Figures 6 and 7).
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the interface
will expect eight values to be loaded
into the device after the address value.
The eight values are coefficients 0
through 7. When loading configuration or select registers, the interface
will expect one value after the address
value. When loading round or limit
registers, the interface will expect four
TABLE 11.
TABLE 6. CF11-9 DECODE
TABLE 7. ROUND REGISTERS
11 10 9 DESCRIPTION
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
REGISTER
ADDRESS (HEX)
0
1
A00
A01
14
15
A0E
A0F
Coefficient Banks
Configuration Registers
Select Registers
Round Registers
Limit Registers
values after the address value. Figures 6 and 7 show the data loading
sequences for the coefficient banks
and configuration/control registers.
PAUSE allows the user to effectively
slow the rate of data loading through
the LF InterfaceTM. When PAUSE is
HIGH, the LF InterfaceTM is held until
PAUSE is returned to a LOW. Figures
8 through 11 display the effects of
PAUSE while leading coefficient and
control data.
Table 10 shows an example of
loading data into the coefficient
banks. The following data values
are written into address 10 of
coefficient banks 0 through 7: 210H,
543H, C76H, 9E3H, 701H, 832H,
F20H, 143H. Table 11 shows an
example of loading data into a
TABLE 8. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0
1
600
601
14
15
60E
60F
TABLE 9. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0
1
E00
E01
14
15
E0E
E0F
CONFIGURATION REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1st Word - Address
0
0
1
0
0
0
0
0
0
0
1
0
2nd Word - Data
0
0
0
0
0
0
0
0
0
0
1
1
TABLE 12.
ROUND REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1st Word - Address
1
0
1
0
0
0
0
0
1
1
0
0
2nd Word - Data
R
R
R
R
1
0
1
0
0
0
1
0*
3rd Word - Data
R
R
R
R
1
1
1
1
0
1
0
0
4th Word - Data
R
R
R
R
1
0
0
0
0
0
1
1
5th Word - Data
R
R
R
R
0**
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
Video Imaging Products
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
configuration register. Data value
003H is written into Configuration
Register 2. Table 12 shows an
example of loading data into a
round register. Data value
7683F4A2H is written into round
register 12. Table 13 shows an
example of loading data into a select
register. Data value 00FH is loaded
into select register 2. Table 14
shows an example of loading data
into limit register 7. Data value
3B60H is loaded as the lower limit
and 72A4H is loaded as the upper
limit.
It takes 9S clock cycles to load S
coefficient sets into the device. Therefore, it takes 2304 clock cycles to load
all 256 coefficient sets. Assuming an
83 MHz clock rate, all 256 coefficient
sets can be updated in less than 27.7 µs,
which is well within vertical blanking
time. It takes 5S clock cycles to load S
round or limit registers. Therefore, it
takes 160 clock cycles to update all
round and limit registers. Assuming an
83 MHz clock rate, all round/limit
registers can be updated in 1.92 µs.
The coefficient banks and configuration/control registers are not loaded
with data until all data values for
the specified address are loaded into
the LF InterfaceTM. In other words,
the coefficient banks are not written
to until all eight coefficients have
been loaded into the LF InterfaceTM.
A round register is not written to
until all four data values are loaded.
After the last data value is loaded,
the interface will expect a new
address value on the next clock
cycle. After the next address value
is loaded, data loading will begin
again as previously discussed. As
long as data is loaded into the
interface, LD must remain LOW.
After all desired coefficient banks
and configuration/control registers
are loaded with data, the LF
InterfaceTM must be disabled. This is
done by setting LD HIGH on the clock
cycle after the clock cycle which
latches the last data value. It is
important that the LF InterfaceTM
remain disabled when not loading
data into it.
TABLE 13. SELECT REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1st Word - Address
0
1
1
0
0
0
0
0
0
0
1
0
2nd Word - Data
0
0
0
0
0
0
0
0
1
1
1
1
TABLE 14. LIMIT REGISTER LOADING FORMAT
CF11
CF10
CF9
CF8
CF7
CF6
CF5
CF4
CF3
CF2
CF1
CF0
1st Word - Address
1
1
1
0
0
0
0
0
0
1
1
1
2nd Word - Data
R
R
R
R
0
1
1
0
0
0
0
0
3rd Word - Data
R
R
R
R
0*
0
1
1
1
0
1
1
4th Word - Data
R
R
R
R
1
0
1
0
0
1
0
0
5th Word - Data
R
R
R
R
0**
1
1
1
0
0
1
0
R = Reserved. Must be set to “0”.
* This bit represents the MSB of the Lower Limit.
** This bit represents the MSB of the Upper Limit.
Video Imaging Products
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V
Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
3.00 V ≤ VCC ≤ 3.60 V
–55°C to +125°C
3.00 V ≤ VCC ≤ 3.60 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –4 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
Unit
V
0.4
V
2.0
5.5
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±10
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±10
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
120
mA
ICC2
VCC Current, Quiescent
(Note 7)
1
mA
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
10
pF
COUT
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
Video Imaging Products
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LF3338–
12
Symbol
Parameter
tCYC
Clock Cycle Time
Min
12
Max
tPW
Clock Pulse Width
5
tS
Input Setup Time
4
tH
Input Hold Time
tDD
Data Output Delay
8
tDC
Cascade Data Output Delay
9
tDIS
Three-State Output Disable Delay (Note 11)
10
tENA
Three-State Output Enable Delay (Note 11)
10
0.5
SWITCHING WAVEFORMS:
DATA I/O
1
2
3
4
5
6
7
CLK
tH
tS
DIN7-0
tPW
DINN
DINN+1
CA7-0
CAN
CAN+1
VB7-0
VBN
VBN+1
tPW
tCYC
CONTROLS
(Except OE)
OE
tDIS
DOUT15-0
tENA
tDD
HIGH IMPEDANCE
DOUTN-1
DOUTN
tDC
COUT7-0
HIGH IMPEDANCE
COUTN-1
COUTN
Video Imaging Products
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) VALUES NOT VALID
LF3338–
12
Symbol
Parameter
tCFS
Coefficient Input Setup Time
Min
5
tCFH
Coefficient Input Hold Time
0
tLS
Load Setup Time
4
tLH
Load Hold Time
0
tPS
PAUSE Setup Time
4
tPH
PAUSE Hold Time
SWITCHING WAVEFORMS:
Max
0.5
LF INTERFACETM
1
2
3
4
5
6
CLK
tLS
tPW
tLH
tPW
tCYC
LD
tPS
tPH
PAUSE
tCFS
CF11–0
tCFH
ADDRESS
CF0
CF1
CF2
Video Imaging Products
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LF3338
DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of IOH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Never- used. Parasitic capacitance is 30 pF
theless, conventional precautions minimum, and may be distributed.
should be observed during storage,
handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current
electrical stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping testing of this device. The following
of transient undershoot. Input levels measures are recommended:
below ground will be clamped beginning at –0.6 V. The device can with- a. A 0.1 µF ceramic capacitor should be
stand indefinite operation with inputs installed between VCC and Ground
or outputs in the range of –0.5 V to leads as close to the Device Under Test
+5.5 V. Device operation will not be (DUT) as possible. Similar capacitors
adversely affected, however, input cur- should be installed between device VCC
rent levels will be well in excess of 100 and the tester common, and device
mA.
ground and tester common.
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.0 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.0V Vth
0
1.5 V
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
socket or contactor fingers.
anteed as specified.
5. Supply current for a given application can be accurately approximated
by:
NCV2 F
4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with outputs changing every
cycle and no load, at a 40 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
c. Input voltages on a test fixture
should be adjusted to compensate for
inductive ground and VCC noise to maintain required DUT input levels relative
to the DUT ground pin.
1.5 V
Z
1
VOL*
VOH*
0.2 V
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
Video Imaging Products
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DEVICES INCORPORATED
8-Bit Vertical Digital Image Filter
ORDERING INFORMATION
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
GND
VCC
DOUT15
DOUT14
DOUT13
DOUT12
DOUT11
DOUT10
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
VCC
GND
100-pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top
View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
OED
VCC
CF0
CF1
CF2
CF3
CF4
CF5
CF6
CF7
CF8
CF9
CF10
CF11
LD
PAUSE
VCC
GND
NC
NC
NC
NC
COUT0
COUT1
COUT2
COUT3
COUT4
COUT5
COUT6
COUT7
GND
VCC
GND
GND
GND
GND
VB0
VB1
VCC
CLK
GND
VB2
VB3
VB4
VB5
VB6
VB7
OEC
VCC
GND
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
ACC
RSL0
RSL1
RSL2
RSL3
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CEN
VCC
GND
SHEN
GND
GND
GND
GND
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
Plastic Quad Flatpack
(Q2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
LF3338QC12
12 ns
25
18
15
12
ns
ns
ns
ns
–55°C to +125°C — COMMERCIAL SCREENING
25
18
15
12
ns
ns
ns
ns
–55°C to +125°C — MIL-STD-883 COMPLIANT
Video Imaging Products
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