TPH3212PS PRODUCT SUMMARY (TYPICAL) VDS (V) 650 RDS(on) (m) 72 Qrr (nC) 90 GaN Power Low-loss Switch S Features Low Qrr Free-wheeling diode not required Low-side Quiet Tab™ for reduced EMI GSD pin layout improves high speed design RoHS compliant High frequency operation G S D Applications TO-220 Package Compact DC-DC converters AC motor drives Battery chargers Switch mode power supplies ry Symbol Parameter Continuous Drain Current @TC=25 °C ID100°C Continuous Drain Current @TC=100 °C Limit Value Unit 28 A 19 A Pulsed Drain Current (pulse width:100 s) 120 A VDSS Drain to Source Voltage 650 V VTDS Transient Drain to Source Voltage a 800 V VGSS Gate to Source Voltage ±18 V PD25°C Maximum Power Dissipation 136 W Case -55 to 150 °C Junction -55 to 175 °C -55 to 150 °C 260 °C TC TJ TS TCsold eli Pr IDM mi ID25°C na Absolute Maximum Ratings (TC=25 °C unless otherwise stated) Operating Temperature Storage Temperature Soldering peak Temperature b Thermal Resistance Symbol Parameter Typical Unit RΘJC Junction-to-Case 1.1 °C /W RΘJA Junction-to-Ambient 62 °C /W Notes a: In off state, spike duty cycle D<0.1, duration <1us b: For 10 sec, 1.6mm from the case Jan. 20, 2016, YFW TPH3212PS www.transphormusa.com 1 TPH3212PS Electrical Characteristics Symbol (TC=25 °C unless otherwise stated) Parameter Min Typical Max Unit Test Conditions 650 - - V VGS=0 V 1.6 2.1 2.6 V VDS=VGS, ID=0.4mA - 72 85 mΩ VGS=8V, ID =18A, TJ = 25 °C - 173 - Ω VGS=8V, ID =18A,TJ = 175 °C - 4 40 µA VDS=650V, VGS=0V, TJ = 25 °C - 9 - µA VDS=650V, VGS=0V, TJ = 150 °C - - 100 Static VGS(th) RDS(on) RDS(on) IDSS IDSS IGSS Maximum Drain-Source Voltage Gate Threshold Voltage Drain-Source On-Resistance (TJ = 25 °C) Drain-Source On-Resistance (TJ = 175 °C) Drain-to-Source Leakage Current, TJ = 25 °C Drain-to-Source Leakage Current, TJ = 150 °C Gate-to-Source Forward Leakage Current Gate-to-Source Reverse Leakage Current VGS= 18 V nA - - -100 na Dynamic ry VDSS-MAX Input Capacitance - 2150 - COSS Output Capacitance - TBD - CRSS Reverse Transfer Capacitance - TBD CO(er) Output Capacitance, energy related a - TBD - CO(tr) Output Capacitance, time related b Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) tr Td(off) tf Turn-On Delay Rise Time Turn-Off Delay Fall Time - - 255 - - 14 20 - TBD - - TBD - - TBD TBD TBD TBD Pr eli mi CISS VGS= -18 V VGS=0 V, VDS=400 V, f =1 MHz pF VGS=0 V, VDS=0 V to 400 V nC VDS =400 V, VGS= 0-8 V, ID = 18 A - ns VDS =400 V , VGS= 0-10 V, ID = 18 A, RG= 2 Ω Reverse operation IS Reverse Current - - TBD A VGS=0 V, TJ=100 oC VSD Reverse Voltage - TBD TBD V VGS=0 V, IS=18 A, TJ=25 oC VSD Reverse Voltage - TBD TBD V VGS=0 V, IS=9 A, TJ=25 oC trr Reverse Recovery Time - TBD - ns Qrr Reverse Recovery Charge - 90 - nC IS=18 A, VDD=400 V, di/dt =1000 A/ s, TJ=25 oC Notes a: Equivalent capacitance to give same stored energy from 0 to 400V b: Equivalent capacitance to give same charging time from 0 to 400V Jan. 20, 2016, YFW TPH3212PS www.transphormusa.com 2 TPH3212PS Test Circuits and Waveforms VDS SiC Diode (C3D06060A) VGS 90% 10% td(on) tr td(off) ton Fig. 13. Switching Time Test Circuit 750V 3M D.U.T. tf toff Fig. 14. Switching Time Waveform Tpulse + VDS Tpulse ≥ 1 uS 750V 750V - 900V MOSFET 0V ≥ 1 uS Duty Ratio = 0.1 0V 10Tpulse Fig. 16. Spike Voltage Waveform Fig. 15. Spike Voltage Test Circuit i, V diF/dt trr IF tF tS t 10% IRRM IRRM QS QF dirr/dt 90% IRRM VRRM trr = tS + tF Qrr = QS +QF Fig. 17. Test Circuit for Reverse Diode Characteristics Jan. 20, 2016, YFW TPH3212PS Fig. 18. Diode Recovery Waveform www.transphormusa.com 3 TPH3212PS MECHANICAL TO-220 Package TO-220 Package Pin 1: Gate, Pin 2: Source, Pin 3: Drain, Tab: Source Jan. 20, 2016, YFW TPH3212PS www.transphormusa.com 4 TPH3212PS Important Notice Transphorm Gallium Nitride (GaN) Switches provide significant advantages over silicon (Si) Superjunction MOSFETs with lower gate charge, faster switching speeds and smaller reverse recovery charge. GaN Switches exhibit in-circuit switching speeds in excess of 150 V/ns and can be even pushed up to 500V/ns, compared to current silicon technology usually switching at rates less than 50V/ns. The fast switching of GaN devices reduces current-voltage cross-over losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN Switches requires adherence to specific PCB layout guidelines and probing techniques . Transphorm suggests visiting application note “Printed Circuit Board Layout and Probing for GaN Power Switches” before evaluating Transphorm GaN switches. Below are some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Switches DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Minimize lead length of TO-220 and TO247 package when mounting to the PCB Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Use shortest sense loop for probing. Attach the probe and its ground connection directly to the test points Use differential mode probe, or probe ground clip with long wire Jan. 20, 2016, YFW Use long traces in drive circuit, long lead length of the devices TPH3212PS www.transphormusa.com 5