INTERSIL HI2302

HI2302
8-Bit, 50 MSPS, Video
A/D Converter with Clamp Function
November 1997
Features
Description
• Resolution . . . . . . . . . . . . . . . . . . 8-Bit ±0.5 LSB (DNL)
The HI2302 is an 8-bit CMOS A/D Converter for video with
synchronizing clamp function. The adoption of two-step
parallel method achieves low power consumption and a
maximum conversion rate of 50 MSPS . For pin compatible
lower sample rate converters refer to HI21429 (35 MSPS) or
HI21426 (20 MSPS) data sheets.
• Maximum Sampling Frequency . . . . . . . . . . . 50 MSPS
• Low Power Consumption . . . . . . . . . . . . . . . . . .125mW
(Reference Current Excluded)
• Built-In Input Clamp Function (DC Restore)
• Clamp ON/OFF Function
Ordering Information
• Internal Voltage Reference
PART
NUMBER
• Input CMOS/TTL Compatible
• Three-State TTL Compatible Output
HI2302JCQ
• Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single
TEMP.
RANGE (oC)
-40 to 85
PACKAGE
32 Ld MQFP
PKG. NO.
Q32.7x7-S
or +5V/3.3V Dual
• Direct Replacement for HI31466JCQ
Applications
• Video Digitizing
• Wireless Receivers
• LCD Projectors/Panels
• Cable Modems
• RGB Graphics Processing
• Camcorders
• Instrumentation
Pinout
VREF
VRBS
CCP
DVSS
CLE
OE
DVSS
NC
HI2302 (MQFP)
TOP VIEW
AVSS
21
VIN
D4
5
20
AVDD
D5
6
19
AVDD
D6
7
18
VRT
D7
8
17
9 10 11 12 13 14 15 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
4-1
VRB
VRTS
AVDD
TEST
CLP
22
4
NC
3
D3
NC
D2
CLK
AVSS
TEST
32 31 30 29 28 27 26 25
1
24
2
23
DVDD
D1
D0
File Number
4105.1
HI2302
Functional Block Diagram
DVSS
28
OE 30
REFERENCE
SUPPLY
25 VRBS
DVSS 31
24 VRB
D0 (LSB) 1
23 AVSS
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7 (MSB)
8
LOWER
DATA
LATCH
LOWER
ENCODER
(4-BIT)
LOWER
SAMPLING COMPARATOR
(4-BIT)
22 AVSS
21 VIN
LOWER
ENCODER
(4-BIT)
LOWER
SAMPLING COMPARATOR
(4-BIT)
20 AVDD
19 AVDD
UPPER
DATA
LATCH
UPPER
ENCODER
(4-BIT)
18 VRT
UPPER
SAMPLING COMPARATOR
(4-BIT)
17 VRTS
16 AVDD
DVDD 10
TEST (OPEN) 11
CLK 12
CLOCK GENERATOR
-+
TEST (OPEN)
15 CLP
9
NC 32
D-FF
14 NC
13 NC
29
27
26
CLE
CCP
VREF
4-2
HI2302
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Reference Voltage (VRT, VRB) . . . . . . . . . . . VDD +0.5 to VSS -0.5V
Input Voltage (Analog) (VIN) . . . . . . . . . . . . . VDD +0.5 to VSS -0.5V
Input Voltage (Digital) (VI). . . . . . . . . . . . . . . VDD +0.5 to VSS -0.5V
Output Voltage (Digital) (VO) . . . . . . . . . . . . VDD +0.5 to VSS -0.5V
Operating Conditions
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-55oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Supply Voltage
(AVDD , AVSS). . . . . . . . . . . . . . . . . . 4.75 to 5.25V
(DVDD , DVSS) . . . . . . . . . . . . . . . . . . . 3.0 to 5.5V
(DVSS-AVSS) . . . . . . . . . . . . . . . . . 0 to 100mV
Reference Input Voltage
(VRB) . . . . . . . . . . . . . . . . . . . . . . . 0 and Above V
(VRT) . . . . . . . . . . . . . . . . . . . . . 2.7 and Below V
Analog Input
(VIN) . . . . . . . . . . . . . . . . . . . . . . . 1.7VP-P Above
Clock Pulse Width (tPW1 , tPW0). . . . . . . . . . . . . . . . . . . . 10ns (Min)
Ambient Temperature (TOPR). . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
fC = 50 MSPS, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
NOTES
MIN
TYP
MAX
UNITS
50
65
-
MSPS
-
-
0.5
MSPS
ANALOG CHARACTERISTICS
Maximum Conversion Rate
fC Max
Minimum Conversion Rate
fC Min
Input Bandwidth Full Scale
BW
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Voltage
ED
AVDD = 4.75 to 5.25V, TA = 20 to 75oC, VIN
= 0.5 to 2.5V,
fIN = 1kHz Triangular Wave
Envelope
RIN = 33Ω
60
-
MHz
-
100
-
MHz
-
±0.3
0.5
LSB
EL
EOT
Potential Difference to VRT
EOB
Potential Difference to VRB
DG
Differential Phase Error
DP
NTSC 40 IRE Mod Ramp
fC = 14.3 MSPS
Sampling Delay
tSD
Clamp Offset Voltage
EOC
Spurious Free Dynamic
-
-3dB
End Point
Differential Gain Error
Signal-To-Noise Ratio
-1dB
SNR
SFDR
VIN = DC, CIN = 10µF
tPCW = 2.75µs,
fC = 14.3 MSPS,
fCLP = 15.75kHz
fIN = 100kHz
Note 2
-
+0.7
1.5
LSB
-70
-50
-30
mV
20
40
60
mV
-
3
-
%
-
1.5
-
Degrees
-
0
-
ns
VREF = 0.5V
0
20
40
mV
VREF = 2.5V
0
20
40
mV
-
45
-
dB
fIN = 500kHz
-
44
-
dB
fIN = 1MHz
-
44
-
dB
fIN = 3MHz
-
43
-
dB
fIN = 10MHz
-
38
-
dB
fIN = 25MHz
-
32
-
dB
fIN = 100kHz
-
51
-
dB
fIN = 500kHz
-
46
-
dB
fIN = 1MHz
-
49
-
dB
fIN = 3MHz
-
46
-
dB
fIN = 10MHz
-
45
-
dB
fIN = 25MHz
-
45
-
dB
4-3
HI2302
Electrical Specifications
PARAMETER
DC CHARACTERISTICS
Supply Current
fC = 50 MSPS, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Continued)
SYMBOL
TEST CONDITIONS
NOTES
MIN
TYP
MAX
UNITS
fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC
IAD + IDD
Analog
IAD
Digital
IDD
NTSC Ramp,
Wave Input,
CLE = 0V
DVDD = 5V
-
25
36
mA
DVDD = 3.3V
-
23
33
mA
-
2
3
mA
Reference Current
IREF
4.1
5.4
7.7
mA
Reference Resistance
(VRT - VRB)
RREF
260
370
480
Ω
0.52
0.56
0.60
V
1.80
1.92
2.04
V
Self-Bias Voltage
VRB
VRT - VRB
Input Capacitance
Output Capacitance
Digital Input Voltage
CAI1
VIN , VIN = 1.5V + 0.07VRMS
-
15
-
pF
CAI2
VRTS , VRT , VRB , VRBS , VREF
-
-
11
pF
CDIN
TEST, CLK, CLP, CLE, OE
-
-
11
pF
CAO
CCP
-
-
11
pF
CDO
D0 to D7, TEST
-
-
11
pF
VIH
AVDD = 4.75 to 5.25V,
DVDD = 3 to 5.5V, TA = -20oC to 75oC
VIL
Digital Input Current
Digital Output Current
Shorts VRTS and AVDD
Shorts VRBS and AVSS
IIH
IIL
IOH
IOL
IOH
IOL
IOZH
IOZL
VI = 0V to AVDD ,
TA = 20oC to 75oC
OE = 0V, DVDD = 5V
TA = 20oC to 75oC
2.2
-
-
V
-
-
0.8
V
CLK
-240
-
240
µA
TEST, CLP, CLE
-240
-
40
µA
OE
-40
-
240
µA
VOH = DVDD - 0.8V
-
-
-2
mA
VOL = 0.4V
4
-
-
mA
OE = 0V
DVDD = 3.3V
TA = -20oC to 75oC
VOH = DVDD - 0.8V
-
-
-1.2
mA
VOL = 0.4V
2.4
-
-
mA
OE = 3V
DVDD = 3 to 5.5V
TA = -20oC to 75oC
VOH = DVDD
-40
-
40
µA
VOL = 0V
-40
-
40
µA
5.5
9.5
12.0
ns
TIMING fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC
Output Data Delay
tPZH
tPHL
CL = 15pF
OE = 0V
tPLH
DVDD = 5V
8.5
DVDD = 3.3V
4.3
tPZH
tPZL
RL = 1kΩ
CL = 15pF
OE = 3V➝0V
tPZH
DVDD = 5V
2.5
Clamp Pulse Width
8.0
DVDD = 3.3V
3.0
7.0
DVDD = 5V
3.5
5.5
DVDD = 3.3V
fC = 14.3MHz, CIN = 10µF for NTSC Wave
Note 4
ns
ns
9.0
ns
7.5
ns
5.0
tPHZ , tPLZ RL = 1kΩ, CL = 15pF
OE = 3V➝0V
tPZH , tPZL
tCPW
4.5
ns
ns
6.0
tPZL
Three-State Output Enable
Time
16.3
7.6
tPHL
Three-State Output Enable
Time
11.8
ns
ns
2.5
5.5
8.0
ns
1.75
2.75
3.75
µs
NOTES:
2. The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of
the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential
point where the voltage rises equivalent to 1/2 LSB of the voltage when the output data changes from “11111111” to “11111110”.
3. The voltage of up to (AVDD + 0.5V) can be input when DVDD = 3.3V. But the output pin voltage is less than the DVDD voltage. When the
digital output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DVDD + 0.5V)
voltage to the digital output.
4. The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing
systems to equal the values for NTSC.
4-4
HI2302
Timing Diagrams
tPW1
tPW0
CLOCK 1.3V
ANALOG INPUT
N
N-3
DATA OUTPUT
N+1
N+2
N+3
N+4
N-2
N-1
N
N+1
= ANALOG SIGNAL SAMPLING POINT
FIGURE 1A. TIMING CHART
tr
4ns
tf
4ns
3V
90%
1.3V
CLOCK
10%
0V
DATA OUTPUT
0.7 DVDD
0.3 DVDD
tPLH,
tPHL
FIGURE 1B. TIMING CHART
tr = 4.5ns
tf = 4.5ns
3V
90%
OE INPUT
1.3V
10%
tPZL
tPLZ
0V
VOH
1.3V
OUTPUT 1
10%
VOL (≠DVSS)
tPHZ
tPZH
VOH (≠DVDD)
90%
1.3V
OUTPUT 2
VOL
FIGURE 1C. TIMING CHART
4-5
HI2302
Timing Diagrams
(Continued)
VI (1)
VI (2)
VI (3)
VI (4)
ANALOG INPUT
EXTERNAL CLOCK
(1)
UPPER COMPARATORS BLOCK
(2)
S (1)
UPPER DATA
C (1)
S (2)
MD (0)
LOWER REFERENCE VOLTAGE
(3)
H (1)
C (3)
C (1)
H (0)
LOWER DATA B
C (0)
S (2)
S (3)
H (3)
H (2)
C (2)
LD (0)
OUT (-2)
RV (3)
C (3)
LD (1)
LD (-2)
DIGITAL OUTPUT
C (4)
MD (3)
RV (2)
LD (-1)
LOWER COMPARATORS B BLOCK
S (4)
MD (2)
RV (1)
S (1)
LOWER DATA A
S (3)
MD (1)
RV (0)
LOWER COMPARATORS A BLOCK
C (2)
(4)
OUT (-1)
S (4)
H (4)
LD (2)
OUT (0)
OUT (1)
FIGURE 1D. TIMING CHART II
Pin Descriptions
PIN NO.
SYMBOL
1 to 8
D0 to D7
EQUIVALENT CIRCUIT
DESCRIPTION
D0 (LSB) to D7 (MSB) Output.
DVDD
DI
DVSS
4-6
HI2302
Pin Descriptions
PIN NO.
SYMBOL
9
TEST
(Continued)
EQUIVALENT CIRCUIT
DESCRIPTION
Leave open for normal use.
DVDD
9
DVSS
10
DVDD
11
TEST
15
Digital Power Supply +5V or +3.3V.
Leave open for normal use. Pull-up resistor is
built in.
AVDD
CLP
Input for the clamp pulse. Clamps the signal
voltage during low interval. Pull-up resistor is
built in.
11
15
29
29
CLE
The clamp function is enabled when CLE =
Low. The clamp function is off and the device
functions as a normal A/D converter when
CLE = High. Pull-up resistor is built in.
AVSS
12
CLK
Clock Input. Set to Low level when no clock is
input.
AVDD
12
AVSS
13, 14, 32
NC
16, 19, 20
AVDD
17
VRTS
18
VRT
24
VRB
25
VRBS
Analog Power Supply +5V.
Generates approximately
shorted with AVDD .
AVDD
when
+0.6V
when
Reference Voltage (Top).
Reference Voltage (Bottom).
17
RT
18
24
RREF
25
Generates approximately
shorted with AVSS .
RB
AVSS
21
+2.5V
VIN
Analog Input.
AVDD
21
AVSS
4-7
HI2302
Pin Descriptions
PIN NO.
SYMBOL
22, 23
AVSS
26
VREF
(Continued)
EQUIVALENT CIRCUIT
DESCRIPTION
Analog Ground.
Clamp Reference Voltage Input. Clamps so
that the reference voltage and the input signal
during clamp interval are equal.
AVDD
26
AVSS
27
CCP
Integrates the clamp control voltage. The
relationship between the changes in CCP
voltage and in VIN voltage is positive phase.
AVDD
27
AVSS
28, 31
DVSS
30
OE
Digital Ground.
Data is output when OE = Low. Pins D0 to D7
are at high impedance when OE = High. Pulldown resistor is built in.
AVDD
30
AVSS
Digital Output
The following table shows the relationship between analog input voltage and digital output code.
INPUT SIGNAL
VOLTAGE
VRT
•
•
•
•
•
•
•
•
VRB
STEP
0
•
•
•
127
128
•
•
•
255
DIGITAL OUTPUT CODE
MSB
LSB
1
1
1
1
1
1
1
1
•
•
•
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
•
•
•
0
0
0
0
0
0
0
0
4-8
HI2302
Electrical Specifications Measurement Circuits
MEASUREMENT
POINT
RL
MEASUREMENT
POINT
TO OUTPUT PIN
DVDD
TO OUTPUT PIN
CL
CL
RL
NOTE: CL includes capacitance of probes.
FIGURE 2. OUTPUT DATA DELAY MEASUREMENT CIRCUIT
FIGURE 3. THREE-STATE OUTPUT MEASUREMENT CIRCUIT
+V
S2
S1: ON IF A < B
S2: ON IF B > A
+
S1
-V
VIN
A<BA>B
COMPARATOR
A8
B8
8
DUT
HI2302
.
.
.
.
.
.
A1
A0
BUFFER
B1
B0
“0”
8
“1”
000 . . . 00
TO
111 . . . 10
DVM
8
CLK (50 MSPS)
CONTROLLER
FIGURE 4. INTEGRAL NONLINEARITY ERROR/DIFFERENTIAL NONLINEARITY ERROR/OFFSET VOLTAGE TEST CIRCUIT
HI90313
8
VIN
NTSC
SIGNAL
SOURCE
TTL
8
10-BIT
D/A
HI2302
100
40 IRE
MODULATION
ECL
2.5V
IAE
620
-5.2V
BURST
VECTOR
SCOPE
CLK
D.G.
D.P.
0
-40
S.G.
(CW)
SYNC
0.5V
620
TTL
fC
-5.2V
ECL
FIGURE 5. DIFFERENTIAL GAIN ERROR, DIFFERENTIAL PHASE ERROR TEST CIRCUIT
4-9
HI2302
Electrical Specifications Measurement Circuits
2.5V
0.5V
VDD
VRT
VIN
VRB
CLK
OE
GND
(Continued)
2.5V
IOL
0.5V
+
VOL
VDD
VRT
VIN
VRB
CLK
OE
GND
-
IOH
VOH
+
-
FIGURE 6. DIGITAL OUTPUT CURRENT TEST CIRCUIT
Operation
Notes On Operation
(See Block diagram and Timing Chart II)
• The HI2302 is a two-step parallel system A/D converter
featuring a 4-bit upper comparator block and two lower
comparator blocks of 4-bit each. The reference voltage
that is equal to the voltage between VRT - VRB/16 is
constantly applied to the upper 4-bit comparator block.
Voltage that corresponded to the upper data is fed through
the reference supply to the lower 4-bit comparator block.
Voltage that corresponded to the upper data is fed through
the reference supply to the lower 4-bit comparator block.
VRTS and VRBS pins serve for the self generation of VRT
(reference voltage top) and VRB (reference voltage bottom), and they are also used as the sense pins as shown
in the Application Circuit examples Figures 10 and 11.
• This IC uses an offset cancel type comparator which
operates synchronously with an external clock. It features
the following operating modes which are respectively indicated on the Timing Chart II with S, H, C symbols. That is
input sampling (auto zero) mode, input hold mode and
comparison mode.
• The operation of respective parts is as indicated in the
Timing Chart II. For instance, input voltage VI (1) is sampled with the falling edge of the external clock (1) by
means of the upper comparator block and the lower
comparator A block.
The upper comparator block finalizes comparison data MD
(1) with the rising edge of the external clock (2).
Simultaneously the reference supply generates the lower
reference voltage RV (1) that corresponded to the upper
results. The lower comparator A Block finalizes comparison data LD (1) with the rising edge of the external clock
(3). MD (1) and LD (1) are combined and output as Out (1)
with the rising edge of the external clock (4). Accordingly
there is a 2.5 clock delay from the analog input sampling
point to the digital data output.
• VDD , VSS
To reduce noise effects, separate the analog and digital
systems close to the device. For both the digital and analog
VDD pins, use a ceramic capacitor of about 0.1µF set as
close as possible to the pin to bypass to the respective
GNDs.
• Analog Input
Compared with the flash type A/D converter, the input
capacitance of the analog input is rather small. However, it
is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with
an amplifier of low output impedance, parasitic oscillation
may occur. That may be prevented by insetting a resistance of about 33Ω in series between the amplifier output
and A/D input. When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no
effect on the characteristics of A/D conversion.
• Clock Input
The clock line wiring should be as short as possible also,
to avoid any interference with other signals, separate it
from other circuits.
• Reference Input
Voltage VRT to VRB is compatible with the dynamic range
of the analog input. Bypassing VRT and VRB pins to GND,
by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VDD and VRTS , VSS and
VRBS respectively, the self-bias function that generates
VRT = about 2.5V and VRB = about 0.6V, is activated.
• Timing
Analog input is sampled with the falling edge of CLK and
output as digital data synchronized with a delay of 2.5
clocks and with the following rising edge. The delay from
the clock rising edge to the data output is about 9ns
(DVDD = 5V).
• OE Pin
Pins 1 to 8 (D0 to D7) are in the output mode by leaving
OE open or connecting it to DVSS , and they are in the high
impedance mode by connecting it to DVDD .
4-10
HI2302
Application Circuits
ACO4
+5V (DIGITAL)
CLOCK IN
0.1µ
OPEN
16
CLAMP PULSE IN
0.01µ
+5V (ANALOG)
VIDEO IN
10µ
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
33Ω
+
0.1µ
10P
+5V (ANALOG)
0.01µ
25
26
27
28
29
30
31
32
VREF
0.01µ
20K
GND (DIGITAL)
GND (ANALOG)
FIGURE 7. SINGLE +5V POWER SUPPLY WHEN CLAMP IS USED (SELF-BIAS USED)
ACO4
+5V (DIGITAL)
CLOCK IN
16
0.01µ
+5V (ANALOG)
VIDEO IN
0.1µ
OPEN
10µ
15
14
13
12
11
10
9
17
8
18
7
19
6
20
5
21
4
22
3
23
2
24
1
33Ω
+
10p
0.1µ
0.01µ
25
26
27
28
29
30
31
CLAMP LEVEL
SETTING DATA
SUBTRACTER
•
COMPARATOR
•
ETC.
32
GND (DIGITAL)
DAC
•
PWM
•
ETC.
GND (ANALOG)
INFORMATION OTHER
THAN THAT FOR CLAMP
INTERVAL IS AT HIGH
IMPEDANCE
NOTES:
5. The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase.
6. ∆ VIN / ∆ VCCP = 3.0 (fS = 20 MSPS).
FIGURE 8. SINGLE +5V POWER SUPPLY DIGITAL CLAMP (SELF-BIAS USED)
4-11
HI2302
Application Circuits
(Continued)
+5V (DIGITAL)
ACO4
0.1µ
CLOCK IN
OPEN
16
+5V (ANALOG) 0.01µ
VIDEO IN
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
33Ω
0.1µ
10p
0.01µ
25
26
27
28
29
30
31
32
GND (DIGITAL)
GND (ANALOG)
FIGURE 9. SINGLE +5V POWER SUPPLY WHEN CLAMP IS NOT USED (SELF-BIAS USED)
+5V (DIGITAL)
ACO4
0.1µ
CLOCK IN
OPEN
16
CLAMP PULSE IN
VRT
+
0.01µ
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
+5V (ANALOG)
VIDEO IN
10µ
33Ω
10p
0.1µ
0.01µ
VRB
+
25
+5V (ANALOG)
26
VREF
27
28
29
30
31
32
0.01µ
20K
GND (DIGITAL)
GND (ANALOG)
FIGURE 10. WHEN CLAMP IS USED (SELF-BIAS NOT USED)
4-12
HI2302
Application Circuits
(Continued)
+5V (DIGITAL)
ACO4
0.1µ
CLOCK IN
OPEN
16
-
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
+
VRT
0.01µ
+5V (ANALOG)
VIDEO IN
33Ω
0.1µ
10p
0.01µ
-
VRB
+
25
26
27
28
29
30
31
32
GND (DIGITAL)
GND (ANALOG)
FIGURE 11. SINGLE +5V POWER SUPPLY WHEN CLAMP IS NOT USED (SELF-BIAS NOT USED)
+3.3V (DIGITAL)
ACO4
0.1µ
CLOCK IN
OPEN
16
CLAMP PULSE IN
0.01µ
+5V (ANALOG)
VIDEO IN
10µ
15
14
13
12
11
10
9
17
8
D7
18
7
D6
19
6
D5
20
5
D4
21
4
D3
22
3
D2
23
2
D1
24
1
D0
33Ω
+
10p
0.1µ
+5V (ANALOG) 0.01µ
25
26
VREF
27
28
29
30
31
32
0.01µ
20K
GND DIGITAL
GND (ANALOG)
FIGURE 12. DUAL +5V/+3.3V POWER SUPPLY WHEN CLAMP IS USED (SELF-BIAS USED)
4-13
HI2302
Typical Performance Curves
fC = 50 MSPS
NTSC RAMP WAVE INPUT
AVDD = DVDD = 5V
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (mA)
fC = 50 MSPS
26
25
24
-20
0
25
50
NTSC RAMP WAVE INPUT
AVDD = DVDD
27
TA = 25oC
25
23
75
4.75
5
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (oC)
FIGURE 14. SUPPLY VOLTAGE vs SUPPLY CURRENT
25
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
FIGURE 13. AMBIENT TEMPERATURE vs SUPPLY CURRENT
20
NTSC RAMP WAVE INPUT
AVDD = DVDD = 5V
15
5.25
fC = 50 MSPS
SINE WAVE 1.9VP-P
AVDD = DVDD = 5V
35
TA = 25oC
30
25
TA = 25oC
10
20
30
40
0.01
50
0.1
fC = 50 MSPS
fIN = 1kHz, TRIANGULAR WAVE INPUT
AVDD = DVDD = 5V
65
60
-20
0
25
50
10
25
FIGURE 16. INPUT FREQUENCY vs SUPPLY CURRENT
MAXIMUM OPERATING RATE (MSPS)
MAXIMUM OPERATING RATE (MSPS)
FIGURE 15. SAMPLING FREQUENCY vs SUPPLY CURRENT
70
1
INPUT FREQUENCY (MHz)
SAMPLING FREQUENCY (MSPS)
75
65
63
4.75
AMBIENT TEMPERATURE (oC)
FIGURE 17. AMBIENT TEMPERATURE vs MAXIMUM
OPERATING FREQUENCY
67
fC = 50 MSPS
NTSC RAMP WAVE INPUT
AVDD = DVDD
5
5.25
SUPPLY VOLTAGE (V)
FIGURE 18. SUPPLY VOLTAGE vs MAXIMUM OPERATING
FREQUENCY
4-14
HI2302
Typical Performance Curves
(Continued)
1
0
OUTPUT LEVEL (dB)
SAMPLING DELAY (ns)
fC = 50 MSPS
AVDD = DVDD = 5V
0
-1
-1
fC = 50 MSPS
SINE WAVE 1VP-P INPUT
AVDD = DVDD = 5V
-3
TA = 25oC
-20
0
25
50
75
0.1
1
AMBIENT TEMPERATURE (oC)
10
100
ANALOG INPUT FREQUENCY (MHz)
FIGURE 19. AMBIENT TEMPERATURE vs SAMPLING DELAY
FIGURE 20. FULL SCALE INPUT BANDWIDTH
60
fC = 50 MSPS
AVDD = DVDD = 5V
VIN = 2VP-P
TA = 25oC
8
50
40
6
SFDR (dB)
7
ENOB
SNR (dB)
50
fC = 50 MSPS
AVDD = DVDD = 5V
VIN = 2VP-P
TA = 25oC
40
5
30
30
0.01
0.1
1
0.01
10
0.1
1
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FIGURE 22. ANALOG INPUT FREQUENCY vs SFDR
FIGURE 21. ANALOG INPUT FREQUENCY vs SNR, EFFECTIVE
NUMBER OF BITS (ENOB)
12
10
fC = 10 MSPS
12
CL = 15pF
OUTPUT DATA DELAY (ns)
OUTPUT DATA DELAY (ns)
fC = 10 MSPS
AVDD = DVDD = 5V
tPLH
8
tPHL
6
AVDD = 5V
DVDD = 3.3V
CL = 15pF
tPLH
10
8
tPHL
6
-20
0
25
50
75
-20
AMBIENT TEMPERATURE (oC)
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 23. AMBIENT TEMPERATURE vs OUTPUT DATA DELAY
FIGURE 24. AMBIENT TEMPERATURE vs OUTPUT DATA DELAY
4-15
HI2302
Typical Performance Curves
(Continued)
14
TA = 25oC
12
OUTPUT DATA DELAY (ns)
OUTPUT DATA DELAY (ns)
fC = 10 MSPS
AVDD = DVDD = 5V
tPLH
10
tPHL
8
6
fC = 10 MSPS
AVDD = 5V
DVDD = 3.3V
12
TA = 25oC
tPLH
10
8
tPHL
6
0
5
10
15
20
25
0
5
10
LOAD CAPACITANCE (pF)
OUTPUT DATA DELAY (ns)
20
25
LOAD CAPACITANCE (pF)
FIGURE 25. LOAD CAPACITANCE vs OUTPUT DATA DELAY
FIGURE 26. LOAD CAPACITANCE vs OUTPUT DATA DELAY
fC = 10 MSPS
AVDD = 5V
CL = pF
TA = 25oC
12
tPLH
10
8
tPHL
6
3
15
3.5
4.5
5
5.5
DVDD SUPPLY VOLTAGE (V)
FIGURE 27. DVDD SUPPLY VOLTAGE vs OUTPUT DATA DELAY
4-16
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4-17