ISL12022MR5421 Features The ISL12022MR5421 device is a low power real time clock (RTC) with an embedded temperature sensor and crystal. Device functions include oscillator compensation, clock/calendar, power fail and low battery monitors, brownout indicator, one-time, periodic or polled alarms, intelligent battery backup switching, Battery Reseal™ function and 128 bytes of battery-backed user SRAM. The device is offered in a 20 Ld SOIC module that contains the RTC and an embedded 32.768kHz quartz crystal. The calibrated oscillator provides less than ±5ppm drift over the full -40°C to +85°C temperature range. • Embedded 32.768kHz Quartz Crystal in the Package The RTC tracks time with separate registers for hours, minutes, and seconds. The calendar registers track date, month, year and day of the week and are accurate through 2099, with automatic leap year correction. • 20 Ld SOIC Package (for DFN version, refer to the ISL12020M) • Calendar • On-chip Oscillator Temperature Compensation • 10-bit Digital Temperature Sensor Output • 15 Selectable Frequency Outputs • Interrupt for Alarm or 15 Selectable Frequency Outputs • Automatic Backup to Battery or Supercapacitor • VDD and Battery Status Monitors • Battery Reseal™ Function to Extend Battery Shelf Life • Power Status Brownout Monitor Daylight Savings time adjustment is done automatically, using parameters entered by the user. Power fail and battery monitors offer user-selectable trip levels. The time stamp function records the time and date of switchover from VDD to VBAT power, and also from VBAT to VDD power. • Time Stamp for Battery Switchover The ISL12022MR5421 has redesign package to increase Contact and Air Discharge ESD performance. • Utility Meters Related Literature • See AN1549 “Addressing Power Issues in Real Time Clock Applications” 1 SCHOTTKY DIODE BAT54 BATTERY 3.0V C2 0.1µF GND 2 GND 3 GND 4 NC 5 NC 6 GND 7 VBAT 8 GND 9 NC 10 NC GND GND GND 19 NC 17 NC 16 GND 3.3V C1 15 0.1µF 14 VDD IRQ/FOUT 13 SCL 12 R1 R2 R3 10k 10k 10k VDO MCU SCL INTERFACE SDA SDA 11 ISL12022MR5421 GND IRQ/FOUT June 4, 2010 FN7576.1 1 • RoHS Compliant Applications • POS Equipment • Printers and Copiers • Digital Cameras Performance Curve 20 18 • I2C-Bus™ FOUT FREQUENCY ERROR (ppm) Typical Application Circuit • 128 Bytes Battery-Backed User SRAM 5 OSCILLATOR ERROR vs TEMPERATURE 4 3 2 1 0 VBAT = 5.5V -1 VDD = 2.7V -2 -3 VDD = 3.3V -4 -5 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. I2C Bus is a registered trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas Inc. 2010. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL12022MR5421 Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Compensation and Auto Daylight Saving ISL12022MR5421 Block Diagram SDA SDA BUFFER SCL SCL BUFFER SECONDS I2C INTERFACE CONTROL LOGIC REGISTERS MINUTES HOURS DAY OF WEEK CRYSTAL OSCILLATOR RTC DIVIDER DATE MONTH VDD POR FREQUENCY OUT ALARM VTRIP + - TEMPERATURE SENSOR GND CONTROL REGISTERS USER SRAM SWITCH INTERNAL SUPPLY VBAT YEAR IRQ/FOUT FREQUENCY CONTROL Pin Configuration ISL12022MR5421 (20 LD SOIC) TOP VIEW GND 1 20 GND GND 2 19 GND GND 3 18 GND NC 4 17 NC NC 5 16 NC GND 6 15 GND VBAT 7 14 VDD GND 8 13 IRQ/FOUT NC 9 12 SCL NC 10 11 SDA Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 4, 5, 9, 10, 16, 17 NC No Connection. Do not connect to a signal or supply voltage. 7 VBAT Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a supercapacitor or tied to ground if not used. See the Battery Monitor parameter in the “DC Operating Characteristics-RTC” table on page 5. This pin should be tied to ground if not used. 11 SDA Serial Data. SDA is a bi-directional pin used to transfer data into and out of the device. It has an open drain output and may be OR’ed with other open drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. 12 SCL Serial Clock. The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. 2 FN7576.1 June 4, 2010 ISL12022MR5421 Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 13 IRQ/FOUT Interrupt Output/Frequency Output (Default 32.768kHz frequency output). This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open drain active low output. Frequency Output Mode. The pin outputs a clock signal, which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain output. The output is open drain and requires a pull-up resistor. 14 VDD Power Supply. Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. 1, 2, 3, 6, 8, 15, 18, 19, 20 GND Ground Pin. Ordering Information PART MARKING VDD RANGE (V) TEMP RANGE (°C) ISL12022MIBZ R5421 2.7 to 5.5 -40 to +85 20 Ld SOIC ISL12022MIBZ-TR5421 ISL12022MIBZ R5421 (Notes 1, 2) 2.7 to 5.5 -40 to +85 20 Ld SOIC (Tape and Reel) M20.3 PART NUMBER ISL12022MIBZR5421 (Note 2) PACKAGE (RoHS Compliant) PKG. DWG. # M20.3 1. Please refer to TB347 for details on reel specifications. 2. These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (lead in high melt temp solder for internal connections) and exemption 5 (lead in piezoelectric elements). These Intersil RoHS compliant products are compatible with both SnPb and Pb free soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN7576.1 June 4, 2010 ISL12022MR5421 Table of Contents Control and Status Registers (CSR)................. 15 Related Literature ............................................. 1 Typical Application Circuit ................................. 1 Performance Curve ............................................ 1 Block Diagram ................................................... 2 Pin Descriptions ................................................ 2 Absolute Maximum Ratings .............................. 5 Thermal Information ........................................ 5 Electrical Specifications .................................... 5 I2C Interface Specifications .............................. 6 SDA vs SCL Timing............................................. 8 Symbol Table ..................................................... 8 Addresses [07h to 0Fh] .................................. 15 Interrupt Control Register (INT) ...................... 16 Power Supply Control Register (PWR_VDD) ....... 17 Battery Voltage Trip Voltage Register (PWR_VBAT)......17 Initial AT and DT Setting Register (ITRO).......... 17 ALPHA Register (ALPHA)................................. 19 BETA Register (BETA) ................................... 19 Final Analog Trimming Register (FATR)............. 20 Final Digital Trimming Register (FDTR) ............. 20 ALARM Registers (10h to 15h)......................... 20 Time Stamp VDD to Battery Registers (TSV2B).. 21 Time Stamp Battery to VDD Registers (TSB2V).. 21 DST Control Registers (DSTCR) ....................... 22 TEMP Registers (TEMP)................................... 23 NPPM Registers (NPPM) .................................. 23 XT0 Registers (XT0)....................................... 23 ALPHA Hot Register (ALPHAH) ......................... 24 Typical Performance Curves ............................. 9 User Registers (Accessed by Using Slave Address 1010111x) ................................................... 24 General Description ......................................... 10 Addresses [00h to 7Fh] .................................. 24 Functional Description..................................... 11 I2C Serial Interface ......................................... 24 Power Control Operation .................................. 11 Normal Mode (VDD) to Battery Backup Mode (VBAT).... 11 Battery Backup Mode (VBAT) to Normal Mode (VDD).... 11 Power Failure Detection .................................. 11 Brownout Detection ........................................ 11 Battery Level Monitor...................................... 11 Real Time Clock Operation............................... 12 Single Event and Interrupt .............................. Frequency Output Mode .................................. General Purpose User SRAM ............................ I2C Serial Interface ........................................ Oscillator Compensation.................................. 12 12 12 12 12 Protocol Conventions ..................................... 24 Device Addressing........................................... 25 Write Operation .............................................. 26 Read Operation ............................................... 26 Application Section ......................................... 26 Battery Backup Details ................................... Layout Considerations .................................... Measuring Oscillator Accuracy ......................... Temperature Compensation Operation.............. Daylight Savings Time (DST) Example.............. 26 26 27 27 28 Register Descriptions ...................................... 12 Revision History .............................................. 28 Real Time Clock Registers ............................... 14 Products.......................................................... 28 Addresses [00h to 06h]................................... 14 M20.3 ............................................................. 29 4 FN7576.1 June 4, 2010 ISL12022MR5421 Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT and IRQ/FOUT pins (Respect to Ground) . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on SCL and SDA pins (Respect to Ground) . . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Rating Human Body Model (Per MIL-STD-883 Method 3014) . . . . . . . . . . . . . >3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >300V Charge Discharge Model . . . . . . . . . . . . . . . . . . . >2200V Latch-up . . . . . . . . . . . . . . . . . . . . . . . . Class II Level A, passed at +85°C ambient with the Level A latch-up criteria of 100mA or 1.5*VMAX input Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 20 Lead SOIC (Notes 3, 4) . . . . . . 70 35 Storage Temperature . . . . . . . . . . . . . . . . . -40°C to +85°C Pb-Free Reflow Profile (Note 5) . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For θJC, the “case temp” location is on top of the package and measured in the center of the package between Pins 6 and 15. 5. The ISL12022MR5421 Oscillator Initial Accuracy can change after solder reflow attachment. The amount of change will depend on the reflow temperature and length of exposure. A general rule is to use only one reflow cycle and keep the temperature and time as short as possible. Changes on the order of ±1ppm to ±3ppm can be expected with typical reflow profiles. DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX (Note 6) (Note 7) (Note 6) UNITS NOTES VDD Main Power Supply (Note 14) 2.7 5.5 V VBAT Battery Supply Voltage (Note 14) 1.8 5.5 V 8 IDD1 Supply Current. (I2C Not Active, VDD = 5V 4.1 7 µA 9, 10 VDD = 3V 3.5 6 µA 9, 10 Temperature Conversion Not Active, FOUT Not Active) IDD2 Supply Current. (I2C Active, Temperature Conversion Not Active, Fout Not Active) VDD = 5V 200 500 µA 9, 10 IDD3 Supply Current. (I2C Not Active, Temperature Conversion Active, FOUT Not Active) VDD = 5V 120 400 µA 9, 10 IBAT Battery Supply Current VDD = 0V, VBAT = 3V, TA = +25°C 1.0 1.6 µA 9 VDD = 0V, VBAT = 3V 1.0 5.0 µA 9 100 nA IBATLKG Battery Input Leakage VDD = 5.5V, VBAT = 1.8V ILI Input Leakage Current on SCL VIL = 0V, VIH = VDD -1.0 ±0.1 1.0 µA ILO I/O Leakage Current on SDA VIL = 0V, VIH = VDD -1.0 ±0.1 1.0 µA VBATM Battery Level Monitor Threshold -100 +100 mV VPBM Brownout Level Monitor Threshold -100 +100 mV VTRIP VBAT Mode Threshold 2.4 V (Note 14) 2.0 2.2 VTRIPHYS VTRIP Hysteresis 30 mV 12 VBATHYS VBAT Hysteresis 50 mV 12 5 ΔFoutT Oscillator Stability vs Temperature VDD = 3.3V -5 +5 ppm ΔFoutV Oscillator Stability vs Voltage 2.7V ≤ VDD ≤ 5.5V -3 +3 ppm 5 FN7576.1 June 4, 2010 ISL12022MR5421 DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER CONDITIONS ΔFoutI Oscillator Initial Accuracy VDD = 3.3V Temp Temperature Sensor Accuracy VDD = VBAT = 3.3V MIN TYP MAX (Note 6) (Note 7) (Note 6) UNITS NOTES -3 +3 ppm 5 °C 12 ±2 IRQ/FOUT (OPEN DRAIN OUTPUT) VOL Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V VDD = 2.7V, IOL = 1mA 0.4 V Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL VDDSR- PARAMETER CONDITIONS MIN TYP MAX (Note 6) (Note 7) (Note 6) UNITS VDD Negative Slew Rate 10 V/ms NOTES 11 I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 7) (Note 6) UNITS VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x VDD VOL SDA Output Buffer LOW Voltage, Sinking 3mA CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD = 5V, VIN = 0V, VOUT = 0V fSCL SCL Frequency VDD = 5V, IOL = 3mA 0 0.02 V 0.4 V 10 pF 400 kHz tIN Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VDD, until SDA exits the 30% to 70% of VDD window. 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VDD during a STOP condition, to SDA crossing 70% of VDD during the following START condition. 1300 ns tLOW Clock LOW Time Measured at the 30% of VDD crossing. 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VDD crossing. 600 ns START Condition Setup Time SCL rising edge to SDA falling edge. Both crossing 70% of VDD. 600 ns tSU:STA 6 NOTES 12, 13 12, 13 FN7576.1 June 4, 2010 ISL12022MR5421 I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 7) (Note 6) UNITS NOTES tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VDD to SCL falling edge crossing 70% of VDD. 600 ns tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VDD window, to SCL rising edge crossing 30% of VDD. 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. 20 tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. 600 ns tHD:STO STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both crossing 70% of VDD. 600 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. 0 ns tR SDA and SCL Rise Time From 30% to 70% of VDD. 20 + 0.1 x Cb 300 ns 12, 13 tF SDA and SCL Fall Time From 70% to 30% of VDD. 20 + 0.1 x Cb 300 ns 12, 13 Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 12, 13 RPU SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ kΩ 12, 13 900 1 ns NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Specified at +25°C. 8. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT <1.8V. 9. IRQ/FOUT inactive. 10. VDD > VBAT +VBATHYS 11. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 12. Limits should be considered typical and are not production tested. 13. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 14. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested. 7 FN7576.1 June 4, 2010 ISL12022MR5421 SDA vs SCL Timing tHIGH tF SCL tSU:STA SDA (INPUT TIMING) tLOW tR tSU:DAT tHD:DAT tHD:STA tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V 1533Ω SDA AND IRQ/FOUT INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance FOR VOL= 0.4V AND IOL = 3mA 100pF FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V 8 WAVEFORM FN7576.1 June 4, 2010 ISL12022MR5421 Temperature is +25°C unless otherwise specified. 1050 1600 1000 1400 IBAT (nA) VBAT CURRENT (nA) Typical Performance Curves 950 900 1200 VBAT = 5.5V 1000 VBAT = 3.0V 800 850 800 1.8 2.3 2.8 3.3 3.8 4.3 4.8 600 -40 5.3 VBAT = 1.8V -20 0 VBAT VOLTAGE (V) 20 40 60 80 TEMPERATURE (°C) FIGURE 3. IBAT vs TEMPERATURE (VDD = 0V) FIGURE 2. IBAT vs VBAT (VDD = 0V) 6 4.4 4.2 4.0 VDD = 5.5V IDD1 (µA) IDD1 (µA) 5 4 VDD = 2.7V 3 3.8 3.6 3.4 VDD = 3.3V 3.2 2 -40 -20 0 20 40 60 3.0 2.7 80 3.2 3.7 TEMPERATURE (°C) FIGURE 4. IDD1 vs TEMPERATURE 4.7 5.2 FIGURE 5. IDD1 vs VDD 5 6 4 3 1 0 VBAT = 5.5V 5 2 VBAT = 5.5V -1 VDD = 2.7V -2 -3 IDD (µA) FOUT FREQUENCY ERROR (ppm) 4.2 VDD (V) VDD = 3.3V 4 VDD = 2.7V 3 VDD = 3.3V -4 -5 -40 -20 0 20 40 TEMPERATURE (°C) 60 80 FIGURE 6. OSCILLATOR ERROR vs TEMPERATURE 9 2 0.01 0.1 1 10 100 1k 10k 1M FREQUENCY OUTPUT (Hz) FIGURE 7. FOUT vs IDD FN7576.1 June 4, 2010 ISL12022MR5421 Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued) 110 100 5.0 80 4.5 4.0 FOUT = 64Hz 3.5 70 60 50 VDD = 3.0V 40 FOUT = 1Hz 3.0 2.5 -40 VBAT = 5.5V 90 FOUT = 32kHz IBAT (µA) SUPPLY CURRENT (µA) 5.5 VDD = 1.8V 30 -20 0 20 40 60 20 -40 80 -20 TEMPERATURE (°C) 60 80 80 VBAT = 5.5V 90 VDD = 3.3V 80 70 60 VDD = 2.7V -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 10. IDD WITH TSE = 1 vs TEMPERATURE General Description The ISL12022MR5421 device is a low power real time clock (RTC) with embedded temperature sensor and crystal. It contains crystal frequency compensation circuitry over the operating temperature range good to ±5ppm accuracy. It also contains a clock/calendar with Daylight Savings Time (DST) adjustment, power fail and low battery monitors, brownout indicator, 1 periodic or polled alarm, intelligent battery backup switching and 128 Bytes of battery-backed user SRAM. The oscillator uses an internal 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes and seconds. The device has calendar registers for date, month, year and day of the week. The calendar is accurate through 2099, with automatic leap year correction. In addition, the ISL12022MR5421 can be programmed for automatic Daylight Saving Time (DST) adjustment by entering local DST information. The ISL12022MR5421’s alarm can be set to any clock/calendar value for a match. For example, every minute, every Tuesday or at 5:23 AM on March 21. The 10 FREQUENCY CHANGE (ppm) 100 IDD (µA) 40 FIGURE 9. IBAT WITH TSE = 1, BTSE = 1 vs TEMPERATURE 110 40 -40 20 TEMPERATURE (°C) FIGURE 8. IDD vs TEMPERATURE, 3 DIFFERENT FOUT 50 0 60 32ppm 40 20 62.5ppm 0ppm 0 -20 -40 -61.5ppm -31ppm -60 -80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 11. OSCILLATOR CHANGE vs TEMPERATURE AT DIFFERENT AGING SETTINGS (IATR) (BETA SET FOR 1ppm STEPS) alarm status is available by checking the Status Register, or the device can be configured to provide a hardware interrupt via the IRQ/FOUT pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. The device also offers a backup power input pin. This VBAT pin allows the device to be backed up by battery or supercapacitor with automatic switchover from VDD to VBAT. The ISL12022MR5421 device is specified for VDD = 2.7V to 5.5V and the clock/calendar portion of the device remains fully operational in battery backup mode down to 1.8V (Standby Mode). The VBAT level is monitored and reported against preselected levels. The first report is registered when the VBAT level falls below 85% of nominal level; the second level is set for 75%. Battery levels are stored in PWR_VBAT registers. The ISL12022MR5421 offers a “Brownout” alarm once the VDD falls below a pre-selected trip level. This allows system Micro to save vital information to memory before complete power loss. There are six VDD levels that could be selected for initiation of the Brownout alarm. FN7576.1 June 4, 2010 ISL12022MR5421 Functional Description Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12022MR5421 for up to 10 years. Another option is to use a supercapacitor for applications where VDD is interrupted for up to a month. See the “Application Section” on page 26 for more information. Normal Mode (VDD) to Battery Backup Mode (VBAT) To transition from the VDD to VBAT mode, both of the following conditions must be met: Condition 1: VDD < VBAT - VBATHYS where VBATHYS ≈ 50mV VBAT 3.0V VTRIP 2.2V VTRIP VTRIP + VTRIPHYS FIGURE 13. BATTERY SWITCHOVER WHEN VBAT > VTRIP The device Time Stamps the switchover from VDD to VBAT and VBAT to VDD, and the time is stored in tSV2B and tSB2V registers respectively. If multiple VDD power-down sequences occur before the status is read, the earliest VDD to VBAT power-down time is stored and the most recent VBAT to VDD time is stored. Temperature conversion and compensation can be enabled in battery backup mode. Bit BTSE in the BETA register controls this operation, as described in “BETA Register (BETA)” on page 19. Condition 2: VDD < VTRIP where VTRIP ≈ 2.2V Power Failure Detection Battery Backup Mode (VBAT) to Normal Mode (VDD) The ISL12022MR5421 device will switch from the VBAT to VDD mode when one of the following conditions occurs: Condition 1: Condition 2: VDD > VTRIP + VTRIPHYS where VTRIPHYS ≈ 30mV These power control situations are illustrated in Figures 12 and 13. The I2C bus is deactivated in battery backup mode to reduce power consumption. Aside from this, all RTC functions are operational during battery backup mode. Except for SCL and SDA, all the inputs and outputs of the ISL12022MR5421 are active during battery backup mode unless disabled via the control register. BATTERY BACKUP MODE VTRIP 2.2V VBAT 1.8V VBAT + VBATHYS VBAT - VBATHYS FIGURE 12. BATTERY SWITCHOVER WHEN VBAT < VTRIP 11 The ISL12022MR5421 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the device has powered up after having lost all power to the device (both VDD and VBAT). Brownout Detection The ISL12022MR5421 monitors the VDD level continuously and provides warning if the VDD level drops below prescribed levels. There are six (6) levels that can be selected for the trip level. These values are 85% below popular VDD levels. The LVDD bit in the Status Register will be set to “1” when brownout is detected. Note that the I2C serial bus remains active unless the Battery VTRIP levels are reached. VDD > VBAT + VBATHYS where VBATHYS ≈ 50mV VDD BATTERY BACKUP MODE VDD Battery Level Monitor The ISL12022MR5421 has a built-in warning feature once the backup battery level drops first to 85% and then to 75% of the battery’s nominal VBAT level. When the battery voltage drops to between 85% and 75%, the LBAT85 bit is set in the status register. When the level drops below 75%, both LBAT85 and LBAT75 bits are set in the status register. The battery level monitor is not functional in battery backup mode. In order to read the monitor bits after powering up VDD, instigate a battery level measurement by setting the TSE bit to "1" (BETA register), and then read the bits. There is a Battery Time Stamp Function available. Once the VDD is low enough to enable switchover to the battery, the RTC time/date are written into the TSV2B register. This information can be read from the TSV2B registers to discover the point in time of the VDD power-down. If there are multiple power-down cycles before reading these registers, the first values stored in FN7576.1 June 4, 2010 ISL12022MR5421 these registers will be retained. These registers will hold the original power-down value until they are cleared by setting CLRTS = 1 to clear the registers. The normal power switching of the ISL12022MR5421 is designed to switch into battery backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. Frequency Output Mode The ISL12022MR5421 has the option to provide a clock output signal using the IRQ/FOUT open drain output pin. The frequency output mode is set by using the FO bits to select 15 possible output frequency values from 1/32Hz to 32kHz. The frequency output can be enabled/disabled during Battery Backup mode using the FOBATB bit. General Purpose User SRAM Note that the ISL12022MR5421 is not guaranteed to operate with VBAT < 1.8V. If the battery voltage is expected to drop lower than this minimum, correct operation of the device, (especially after a VDD power-down cycle) is not guaranteed. The ISL12022MR5421 provides 128 bytes of user SRAM. The SRAM will continue to operate in battery backup mode. However, it should be noted that the I2C bus is disabled in battery backup mode. The minimum VBAT to insure SRAM is stable is 1.0V. Below that, the SRAM may be corrupted when VDD power resumes. The ISL12022MR5421 has an I2C serial bus interface that provides access to the control and status registers and the user SRAM. The I2C serial interface is compatible with other industry I2C serial bus protocols using a bi-directional data signal (SDA) and a clock signal (SCL). Real Time Clock Operation The Real Time Clock (RTC) uses an integrated 32.768kHz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, month, and year. The RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24-hour or AM/PM format. When the ISL12022MR5421 powers up after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock register. Single Event and Interrupt The alarm mode is enabled via the MSB bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that when the frequency output function is enabled, the alarm function is disabled. The standard alarm allows for alarms of time, date, day of the week, month, and year. When a time alarm occurs in single event mode, the IRQ/FOUT pin will be pulled low and the alarm status bit (ALM) will be set to “1”. The pulsed interrupt mode allows for repetitive or recurring alarm functionality. Hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). During pulsed interrupt mode, the IRQ/FOUT pin will be pulled low for 250ms and the alarm status bit (ALM) will be set to “1”. The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery backup mode using the FOBATB bit. For more information on the alarm, please see “ALARM Registers (10h to 15h)” on page 20. I2C Serial Interface Oscillator Compensation The ISL12022MR5421 provides both initial timing correction and temperature correction due to variation of the crystal oscillator. Analog and digital trimming control is provided for initial adjustment, and a temperature compensation function is provided to automatically correct for temperature drift of the crystal. Initial values for the initial AT and DT settings (ITR0), temperature coefficient (ALPHA), crystal capacitance (BETA), as well as the crystal turn-over temperature (XTO), are preset internally and recalled to RAM registers on power-up. These values can be overwritten by the user although this is not suggested as the resulting temperature compensation performance will be compromised. The compensation function can be enabled/disabled at any time and can be used in battery mode as well. Register Descriptions The battery-backed registers are accessible following a slave byte of “1101111x” and reads or writes to addresses [00h:2Fh]. The defined addresses and default values are described in the Table 1. The battery backed general purpose SRAM has a different slave address (1010111x), so it is not possible to read/write that section of memory while accessing the registers. REGISTER ACCESS The contents of the registers can be modified by performing a byte or a page write operation directly to any register address. The registers are divided into 8 sections. They are: 1. Real Time Clock (7 bytes): Address 00h to 06h. 2. Control and Status (9 bytes): Address 07h to 0Fh. 3. Alarm (6 bytes): Address 10h to 15h. 4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah. 12 FN7576.1 June 4, 2010 ISL12022MR5421 A register can be read by performing a random read at any address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. At the end of a read, the master supplies a stop condition to end the operation and free the bus. After a read, the address remains at the previous address +1 so the user can execute a current address read and continue reading the next register. When the previous address is 2Fh, the next address will wrap around to 00h. 5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh. 6. Day Light Saving Time (8 bytes): 20h to 27h. 7. TEMP (2 bytes): 28h to 29h. 8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh 9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch 10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh 11. Scratch Pad (2 bytes): Address 2Eh and 2Fh Write capability is allowable into the RTC registers (00h to 06h) only when the WRTC bit (bit 6 of address 08h) is set to “1”. A multi-byte read or write operation should be limited to one section per operation for best RTC time keeping performance. It is not necessary to set the WRTC bit prior to writing into the control and status, alarm, and user SRAM registers. TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS) SECTIO ADDR. N BIT REG NAME 7 6 5 4 3 2 1 0 00h SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h 01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 00h 02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 01h 04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 01h 05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h 06h DW 0 0 0 0 0 DW2 DW1 DW0 0 to 6 00h 07h SR BUSY OSCF DSTADJ ALM LVDD LBAT85 LBAT75 RTCF N/A 01h 08h INT ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 N/A 01h 09h PWR_VDD CLRTS D D D D VDDTrip2 VDDTrip1 VDDTrip0 N/A 00h 0Ah PWR_VBAT D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 N/A 00h ITRO IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 N/A XXh 0Ch ALPHA D ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 N/A XXh 0Dh BETA TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 N/A XXh 0Eh FATR 0 0 FFATR5 FATR4 FATR3 FATR2 FATR1 FATR0 N/A 00h 0Fh FDTR 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 N/A 00h 10h SCA0 ESCA0 SCA022 SCA021 SCA020 SCA013 SCA012 SCA011 SCA010 00 to 59 00h 11h MNA0 EMNA0 MNA022 MNA021 MNA020 MNA013 MNA012 MNA011 MNA010 00 to 59 00h HRA0 EHRA0 D HRA021 HRA020 HRA013 HRA012 HRA011 HRA010 0 to 23 00h DTA0 EDTA0 D DTA021 DTA020 DTA013 DTA012 DTA011 DTA010 01 to 31 00h 14h MOA0 EMOA00 D D MOA020 MOA013 MOA012 MOA011 MOA010 01 to 12 00h 15h DWA0 EDWA0 D D D D DWA02 DWA01 DWA00 0 to 6 00h 03h 0Bh 12h 13h RTC CSR ALARM 13 RANGE DEFAULT FN7576.1 June 4, 2010 ISL12022MR5421 TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS) (Continued) SECTIO ADDR. N BIT REG NAME 7 6 5 4 3 2 1 0 16h VSC 0 VSC22 VSC21 VSC20 VSC13 VSC12 VSC11 VSC10 0 to 59 00h 17h VMN 0 VMN22 VMN21 VMN20 VMN13 VMN12 VMN11 VMN10 0 to 59 00h VHR VMIL 0 VHR21 VHR20 VHR13 VHR12 VHR11 VHR10 0 to 23 00h 19h VDT 0 0 VDT21 VDT20 VDT13 VDT12 VDT11 VDT10 1 to 31 00h 1Ah VMO 0 0 0 VMO20 VMO13 VMO12 VMO11 VMO10 1 to 12 00h 1Bh BSC 0 BSC22 BSC21 BSC20 BSC13 BSC12 BSC11 BSC10 0 to 59 00h 1Ch BMN 0 BMN22 BMN21 BMN20 BMN13 BMN12 BMN11 BMN10 0 to 59 00h BHR BMIL 0 BHR21 BHR20 BHR13 BHR12 BHR11 BHR10 0 to 23 00h 1Eh BDT 0 0 BDT21 BDT20 BDT13 BDT12 BDT11 BDT10 1 to 31 00h 1Fh BMO 0 0 0 BMO20 BMO13 BMO12 BMO11 BMO10 1 to 12 00h 20h DstMoFd DSTE D D DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10 1 to 12 00h 21h DstDwFd D DstDwFdE DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10 0 to 6 00h 22h DstDtFd D D DstDtFd21 DstDtFd20 DstDtFd13 DstDtFd12 DstDtFd11 DstDtFd10 1 to 31 00h DstHrFd D D DstHrFd21 DstHrFd20 DstHrFd13 DstHrFd12 DstHrFd11 DstHrFd10 0 to 23 00h DstMoRv D D D DstMoRv20 DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10 01 to 12 00h 25h DstDwRv D DstDwRvE 0 to 6 00h 26h DstDtRv D D DstDtRv21 DstDtRv20 DstDtRv13 DstDtRv12 DstDtRv11 DstDtRv10 01 to 31 00h 27h DstHrRv D D DstHrRv21 DstHrRv20 DstHrRv13 DstHrRv12 DstHrRv11 DstHrRv10 0 to 23 00h TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 00 to FF 00h TK0M 0 0 0 0 0 0 TK09 TK08 00 to 03 00h NPPML NPPM7 NPPM6 NPPM5 NPPM4 NPPM3 NPPM2 NPPM1 NPPM0 00 to FF 00h NPPMH 0 0 0 0 0 NPPM10 NPPM9 NPPM8 00 to 07 00h 18h 1Dh 23h 24h 28h 29h 2Ah 2Bh TSV2B TSB2V DSTCR TEMP NPPM DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10 RANGE DEFAULT 2Ch XT0 XT0 D D D XT4 XT3 XT2 XT1 XT0 00 to FF XXh 2Dh ALPHAH ALPHAH D ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0 00 to 7F XXh 2Eh GPM GPM1 GPM17 GPM16 GPM15 GPM14 GPM13 GPM12 GPM11 GPM10 00 to FF 00h GPM2 GPM27 GPM26 GPM25 GPM24 GPM23 GPM22 GPM21 GPM20 00 to FF 00h 2Fh Real Time Clock Registers Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the Week) is 0 to 6. The DW register provides a Day of the Week status and uses three bits (DW2 to DW0) to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical value to a specific day of the week is arbitrary and may 14 be decided by the system software designer. The default value is defined as “0”. 24-HOUR TIME If the MIL bit of the HR register is “1”, the RTC uses a 24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour format and HR21 bit functions as an AM/PM indicator with a “1” representing PM. The clock defaults to 12-hour format time with HR21 = “0”. LEAP YEARS Leap years add the day February 29 and are defined as those years that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 is a leap year and the year 2100 is not. The ISL12022MR5421 does not correct for the leap year in the year 2100. FN7576.1 June 4, 2010 ISL12022MR5421 Control and Status Registers (CSR) Addresses [07h to 0Fh] The Control and Status Registers consist of the Status Register, Interrupt and Alarm Register, Analog Trimming and Digital Trimming Registers. STATUS REGISTER (SR) The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or status of RTC failure (RTCF), Battery Level Monitor (LBAT85, LBAT75), alarm trigger, Daylight Saving Time, crystal oscillator enable and temperature conversion in progress bit. TABLE 2. STATUS REGISTER (SR) ADDR 7 6 5 4 3 07h BUSY OSCF DSTDJ ALM LVDD 2 1 0 LBAT85 LBAT75 RTCF BUSY BIT (BUSY) Busy Bit indicates temperature sensing is in progress. In this mode, Alpha, Beta and ITRO registers are disabled and cannot be accessed. OSCILLATOR FAIL BIT (OSCF) Oscillator Fail Bit indicates that the oscillator has stopped. DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ) DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the daylight saving time forward adjustment has happened. If a DST Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit will stay high when DSTFD event happens, and will be reset to “0” when the DST Reverse event happens. DSTADJ can be set to “1” for instances where the RTC device is initialized during the DST Forward period. The DSTE bit must be enabled when the RTC time is more than one hour before the DST Forward or DST Reverse event time setting, or the DST event correction will not happen. DSTADJ is reset to “0” upon power-up. It will reset to “0” when the DSTE bit in Register 15h is set to “0” (DST disabled), but no time adjustment will happen. ALARM BIT (ALM) This bit announces if the alarm matches the real time clock. If there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by enabling the auto-reset bit (see ARST bit). A write to this bit in the SR can only set it to “0”, not “1”. An alarm bit that is set by an alarm occurring during an SR read operation will remain set after the read operation is complete. LOW VDD INDICATOR BIT (LVDD) This bit indicates when VDD has dropped below the pre-selected trip level (Brownout Mode). The trip points 15 for the brownout levels are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in PWR_ VDD registers. The LVDD detection is only enabled in VDD mode and the detection happens in real time. The LVDD bit is set whenever the VDD has dropped below the pre-selected trip level, and self clears whenever the VDD is above the pre-selected trip level. LOW BATTERY INDICATOR 85% BIT (LBAT85) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the PWR_VBAT registers. The LBAT85 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to “1”. The LBAT85 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register reaches x9h or x0h minutes. Example - When the LBAT85 is Set To “1” In Battery Mode The minute the register changes to 19h when the device is in battery mode, the LBAT85 is set to “1” the next time the device switches back to Normal Mode. Example - When the LBAT85 Remains at “0” In Battery Mode If the device enters into battery mode after the minute register reaches 20h and switches back to Normal Mode before the minute register reaches 29h, then the LBAT85 bit will remain at “0” the next time the device switches back to Normal Mode. LOW BATTERY INDICATOR 75% BIT (LBAT75) In Normal Mode (VDD), this bit indicates when the battery level has dropped below the pre-selected trip levels. The trip points are selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the PWR_VBAT registers. The LBAT75 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to “1”. The LBAT75 bit is set when the VBAT has dropped below the pre-selected trip level, and will self clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register reaches x9h or x0h minutes. FN7576.1 June 4, 2010 ISL12022MR5421 Example - When the LBAT75 is Set to “1” in Battery Mode The minute register changes to 30h when the device is in battery mode, the LBAT75 is set to “1” the next time the device switches back to Normal Mode. Example - When the LBAT75 Remains at “0” in Battery Mode If the device enters into battery mode after the minute register reaches 49h and switches back to Normal Mode before minute register reaches 50h, then the LBAT75 bit will remain at “0” the next time the device switches back to Normal Mode. REAL TIME CLOCK FAIL BIT (RTCF) This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (ISL12022MR5421 internally) when the device powers up after having lost all power (defined as VDD = 0V and VBAT = 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. The first valid write to the RTC section after a complete power failure resets the RTCF bit to “0” (writing one byte is sufficient). Interrupt Control Register (INT) TABLE 3. INTERRUPT CONTROL REGISTER (INT) ADDR 7 6 5 4 08h ARST WRTC IM 3 2 1 0 FOBATB FO3 FO2 FO1 FO0 AUTOMATIC RESET BIT (ARST) This bit enables/disables the automatic reset of the ALM, LVDD, LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the ARST is cleared to “0”, the user must manually reset the ALM, LVDD, LBAT85, and LBAT75 bits. TABLE 4. IM BIT INTERRUPT/ALARM FREQUENCY 0 Single Time Event Set By Alarm 1 Repetitive/Recurring Time Event Set By Alarm FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) This bit enables/disables the IRQ/FOUT pin during battery backup mode (i.e. VBAT power source active). When the FOBATB is set to “1”, the IRQ/FOUT pin is disabled during battery backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is cleared to “0”, the IRQ/FOUT pin is enabled during battery backup mode. Note that the open drain IRQ/FOUT pin will need a pull-up to the battery voltage to operate in battery backup mode. FREQUENCY OUT CONTROL BITS (FO <3:0>) These bits enable/disable the frequency output function and select the output frequency at the IRQ/FOUT pin. See Table 5 for frequency selection. Default for the ISL12022MR5421 is FO<3:0> = 1h, or 32.768kHz output (FOUT is ON). When the frequency mode is enabled, it will override the alarm mode at the IRQ/FOUT pin. TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN FREQUENCY FOUT UNITS FO3 FO2 FO1 FO0 0 Hz 0 0 0 0 32768 Hz 0 0 0 1 4096 Hz 0 0 1 0 1024 Hz 0 0 1 1 64 Hz 0 1 0 0 WRITE RTC ENABLE BIT (WRTC) 32 Hz 0 1 0 1 The WRTC bit enables or disables write capability into the RTC Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to enable the RTC. Upon the completion of a valid write (STOP), the RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. 16 Hz 0 1 1 0 8 Hz 0 1 1 1 4 Hz 1 0 0 0 2 Hz 1 0 0 1 1 Hz 1 0 1 0 INTERRUPT/ALARM MODE BIT (IM) 1/2 Hz 1 0 1 1 This bit enables/disables the interrupt mode of the alarm function. When the IM bit is set to “1”, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ/FOUT pin when the RTC is triggered by the alarm, as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to “0”, the alarm will operate in standard mode, where the IRQ/FOUT pin will be set low until the ALM status bit is cleared to “0”. 1/4 Hz 1 1 0 0 1/8 Hz 1 1 0 1 1/16 Hz 1 1 1 0 1/32 Hz 1 1 1 1 16 FN7576.1 June 4, 2010 ISL12022MR5421 Power Supply Control Register (PWR_VDD) CLEAR TIME STAMP BIT (CLRTS) ADDR 09h 7 6 5 4 3 2 CLRTS 0 0 0 0 VDDTrip2 1 0 VDDTrip1 VDDTrip0 This bit clears Time Stamp VDD to Battery (TSV2B) and Time Stamp Battery to VDD Registers (TSB2V). The default setting is 0 (CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1). VDD BROWNOUT TRIP VOLTAGE BITS (VDDTRIP<2:0>) These bits set the trip level for the VDD alarm, indicating that VDD has dropped below a preset level. In this event, the LVDD bit in the Status Register is set to “1”. See Table 6. TABLE 6. VDD TRIP LEVELS VDDTrip2 VDDTrip1 VDDTrip0 TRIP VOLTAGE (V) 0 0 0 2.295 0 0 1 2.550 0 1 0 2.805 0 1 1 3.060 1 0 0 4.250 1 0 1 4.675 BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>) Three bits select the first alarm (85% of Nominal VBAT) level for the battery voltage monitor. There are a total of 7 levels that could be selected for the first alarm. Any of the of levels could be selected as the first alarm with no reference as to nominal Battery voltage level. See Table 8. TABLE 8. VB85T ALARM LEVEL VB85Tp2 VB85Tp1 VB85Tp0 BATTERY ALARM TRIP LEVEL (V) 0 0 0 2.125 0 0 1 2.295 0 1 0 2.550 0 1 1 2.805 1 0 0 3.060 1 0 1 4.250 1 1 0 4.675 BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>) Three bits select the second alarm (75% of Nominal VBAT) level for the battery voltage monitor. There are a total of 7 levels that could be selected for the second alarm. Any of the of levels could be selected as the second alarm with no reference as to nominal Battery voltage level. See Table 9. TABLE 9. BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>) Battery Voltage Trip Voltage Register (PWR_VBAT) This register controls the trip points for the two VBAT alarms, with levels set to approximately 85% and 75% of the nominal battery level. VB75Tp2 VB75Tp1 VB75Tp0 BATTERY ALARM TRIP LEVEL (V) 0 0 0 1.875 TABLE 7. 0 0 1 2.025 0 1 0 2.250 0 1 1 2.475 1 0 0 2.700 1 0 1 3.750 1 1 0 4.125 ADDR 0Ah 7 6 5 4 3 2 1 0 D RESEALB VB85 VB85 VB85 VB75 VB75 VB75 Tp2 Tp1 Tp0 Tp2 Tp1 Tp0 RESEAL BIT (RESEALB) This is the Reseal bit for actively disconnecting the VBAT pin from the internal circuitry. Setting this bit allows the device to disconnect the battery and eliminate standby current drain while the device is unused. Once VDD is powered up, this bit is reset and the VBAT pin is then connected to the internal circuitry. The application for this bit involves placing the chip on a board with a battery and testing the board. Once the board is tested and ready to ship, it is desirable to disconnect the battery to keep it fresh until the board or unit is placed into final use. Setting RESEALB = “1” initiates the battery disconnect, and after VDD power is cycled down and up again, the RESEAL bit is cleared to “0”. 17 Initial AT and DT Setting Register (ITRO) These bits are used to trim the initial error (at room temperature) of the crystal. Both Digital Trimming (DT) and Analog Trimming (AT) methods are available. The digital trimming uses clock pulse skipping and insertion for frequency adjustment. Analog trimming uses load capacitance adjustment to pull the oscillator frequency. A range of +62.5ppm to -61.5ppm is possible with combined digital and analog trimming. Initial values for the ITR0 register are preset internally and recalled to RAM registers on power-up. These values are pre-set in device production and are READ-ONLY. They cannot be overwritten by the FN7576.1 June 4, 2010 ISL12022MR5421 user. If an application requires adjustment of the IATR bits outside the preset values, the user should contact Intersil. TABLE 12. IATRO TRIMMING RANGE (Continued) IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 TRIMMING RANGE AGING AND INITIAL TRIM DIGITAL TRIMMING BITS (IDTR0<1:0>) 0 0 1 1 0 0 +20 0 0 1 1 0 1 +19 These bits allow ±30.5ppm initial trimming range for the crystal frequency. This is meant to be a coarse adjustment if the range needed is outside that of the IATR control. See Table 10. The IDTR0 register should only be changed while the TSE (Temp Sense Enable) bit is “0”. 0 0 1 1 1 0 +18 0 0 1 1 1 1 +17 0 1 0 0 0 0 +16 0 1 0 0 0 1 +15 0 1 0 0 1 0 +14 0 1 0 0 1 1 +13 The ISL12022MR5421 has a preset Initial Digital Trimming value corresponding to the crystal in the module. This value is recalled on initial power-up and is READ-ONLY. It cannot be overwritten by the user. 0 1 0 1 0 0 +12 0 1 0 1 0 1 +11 0 1 0 1 1 0 +10 0 1 0 1 1 1 +9 0 1 1 0 0 0 +8 0 1 1 0 0 1 +7 0 1 1 0 1 0 +6 0 1 1 0 1 1 +5 Default/Disabled 0 1 1 1 0 0 +4 +30.5ppm 0 1 1 1 0 1 +3 0 1 1 1 1 0 +2 0 1 1 1 1 1 +1 1 0 0 0 0 0 0 AGING AND INITIAL ANALOG TRIMMING BITS (IATR0<5:0>) 1 0 0 0 0 1 -1 1 0 0 0 1 0 -2 The Initial Analog Trimming Register allows +32ppm to -31ppm adjustment in 1ppm/bit increments. This enables fine frequency adjustment for trimming initial crystal accuracy error or to correct for aging drift. 1 0 0 0 1 1 -3 1 0 0 1 0 0 -4 1 0 0 1 0 1 -5 1 0 0 1 1 0 -6 1 0 0 1 1 1 -7 1 0 1 0 0 0 -8 1 0 1 0 0 1 -9 1 0 1 0 1 0 -10 1 0 1 0 1 1 -11 1 0 1 1 0 0 -12 1 0 1 1 0 1 -13 1 0 1 1 1 0 -14 1 0 1 1 1 1 -15 1 1 0 0 0 0 -16 1 1 0 0 0 1 -17 1 1 0 0 1 0 -18 1 1 0 0 1 1 -19 1 1 0 1 0 0 -20 1 1 0 1 0 1 -21 1 1 0 1 1 0 -22 1 1 0 1 1 1 -23 1 1 1 0 0 0 -24 1 1 1 0 0 1 -25 1 1 1 0 1 0 -26 1 1 1 0 1 1 -27 1 1 1 1 0 0 -28 1 1 1 1 0 1 -29 1 1 1 1 1 0 -30 1 1 1 1 1 1 -31 TABLE 10. IDTR0 TRIMMING RANGE IDTR01 IDTR00 0 0 0 TRIMMING RANGE 1 1 0 0ppm 1 1 -30.5ppm The ISL12022MR5421 has a preset Initial Analog Trimming value corresponding to the crystal in the module. This value is recalled on initial power-up, is preset in device production and is READ-ONLY. It cannot be overwritten by the user. TABLE 11. INITIAL AT AND DT SETTING REGISTER ADDR 0Bh 7 6 5 4 3 2 1 0 IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 TABLE 12. IATRO TRIMMING RANGE TRIMMING IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 18 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 +32 +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 FN7576.1 June 4, 2010 ISL12022MR5421 ALPHA Register (ALPHA) voltage is lower than 2.7V. No temperature compensation will take place with VBAT < 2.7V. TABLE 13. ALPHA REGISTER ADDR 7 0Ch D 6 5 4 3 2 1 0 ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 The ALPHA variable is 8 bits and is defined as the temperature coefficient of crystal from -40°C to T0, or the ALPHA Cold (there is an Alpha Hot register that must be programmed as well). It is normally given in units of ppm/°C2, with a typical value of -0.034. The ISL12022MR5421 device uses a scaled version of the absolute value of this coefficient in order to get an integer value. Therefore, ALPHA <7:0> is defined as the (|Actual ALPHA Value| x 2048) and converted to binary. For example, a crystal with Alpha of -0.034ppm/°C2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. The practical range of Actual ALPHA values is from -0.020 to -0.060. The ISL12022MR5421 has a preset ALPHA value corresponding to the crystal in the module. This value is recalled on initial power-up and is preset in device production. It is READ ONLY and cannot be overwritten by the user. BETA Register (BETA) TABLE 14. ADDR 0Dh 7 6 5 4 3 2 1 0 TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 The BETA register has special Write properties. Only the TSE, BTSE and BTSR bits can be written; the BETA bits are READ-ONLY. A write to both bytes in this register will only change the 3 MSB’s (TSE, BTSE, BTSR), and the 5 LSB’s will remain the same as set at the factory. TEMPERATURE SENSOR ENABLED BIT (TSE) This bit enables the Temperature Sensing operation, including the temperature sensor, A/D converter and FATR/FDTR register adjustment. The default mode after power-up is disabled: (TSE = 0). To enable the operation, TSE should be set to 1. (TSE = 1). When temp sense is disabled, the initial values for IATR and IDTR registers are used for frequency control. When TSE is set to 1, the temperature conversion cycle begins and will end when two temperature conversions are completed. The average of the two conversions is in the TEMP registers. TEMP SENSOR CONVERSION IN BATTERY MODE BIT (BTSE) This bit enables the Temperature Sensing and Correction in battery mode. BTSE = 0 (default) no conversion, Temp Sensing or Compensation in battery mode. BTSE = 1 indicates Temp Sensing and Compensation enabled in battery mode. The BTSE is disabled when the battery 19 FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT (BTSR) This bit controls the frequency of Temp Sensing and Correction. BTSR = 0 default mode is every 10 minutes, BTSR = 1 is every 1.0 minute. Note that BTSE has to be enabled in both cases. See Table 15. TABLE 15. FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT BTSE BTSR TC PERIOD IN BATTERY MODE 0 0 OFF 0 1 OFF 1 0 10 Minutes 1 1 1 Minute The temperature measurement conversion time is the same for battery mode as for VDD mode, approximately 22ms. The battery mode current will increase during this conversion time to typically 68µA. The average increase in battery current is much lower than this due to the small duty cycle of the ON-time versus OFF-time for the conversion. To figure the average increase in battery current, we take the change in current times the duty cycle. For the 1 minute temperature period, the average current is expressed in Equation 1: 0.022s ΔI BAT = ------------------ × 68μA = 250nA 60s (EQ. 1) For the 10 minute temperature period the average current is expressed in Equation 2: 0.022s ΔI BAT = ------------------ × 68μA = 25nA 600s (EQ. 2) If the application has a stable temperature environment that doesn’t change quickly, the 10 minute option will work well and the backup battery lifetime impact is minimized. If quick temperature variations are expected (multiple cycles of more than 10° within an hour), then the 1 minute option should be considered and the slightly higher battery current figured into overall battery life. GAIN FACTOR OF AT BIT (BETA<4:0>) Beta is specified to take care of the Cm variations of the crystal. Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF, the actual AT steps may reduce from 1ppm/step to approximately 0.80ppm/step. Beta is then used to adjust for this variation and restore the step size to 1ppm/step. BETA values are limited in the range from 01000 to 11111, as shown in Table 16. To use Table 16, the device is tested at two AT settings as follows: BETA VALUES = (AT(max) - AT (min))/63, where: AT(max) = FOUT in ppm (at AT = 00H) and FN7576.1 June 4, 2010 ISL12022MR5421 AT(min) = FOUT in ppm (at AT = 3FH). TABLE 18. FINAL DIGITAL TRIMMING REGISTER The BETA VALUES result is indexed in the right hand column and the resulting Beta factor (for the register) is in the same row in the left column. ADDR 7 6 5 0Fh 0 0 0 The ISL12022MR5421 has a preset BETA value corresponding to the crystal in the module. This value is recalled on initial power-up and is preset in device production. It is READ ONLY and cannot be overwritten by the user. Final Digital Trimming Register (FDTR) TABLE 16. BETA VALUES BETA<4:0> AT STEP ADJUSTMENT 01000 0.5000 00111 0.5625 00110 0.6250 00101 0.6875 00100 0.7500 00011 0.8125 00010 0.8750 00001 0.9375 00000 1.0000 10000 1.0625 10001 1.1250 10010 1.1875 10011 1.2500 10100 1.3125 10101 1.3750 10110 1.4375 10111 1.5000 11000 1.5625 11001 1.6250 11010 1.6875 11011 1.7500 11100 1.8125 11101 1.8750 11110 1.9375 11111 2.0000 This register shows the final setting of AT after temperature correction. It is read-only; the user cannot overwrite a value to this register. This value is accessible as a means of monitoring the temperature compensation function. See Table 17 and Table 18 (for values). TABLE 17. FINAL ANALOG TRIMMING REGISTER 7 6 0Eh 0 0 5 4 3 2 1 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0 20 3 2 1 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 This Register shows the final setting of DT after temperature correction. It is read-only; the user cannot overwrite a value to this register. The value is accessible as a means of monitoring the temperature compensation function. The corresponding clock adjustment values are shown in Table 19. The FDTR setting has both positive and negative settings to adjust for any offset in the crystal. TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL TRIMMING REGISTER Final Analog Trimming Register (FATR) ADDR 4 FDTR<2:0> DECIMAL ppm ADJUSTMENT 00000 0 0 00001 1 30.5 00010 2 61 00011 3 91.5 00100 4 122 00101 5 152.5 00110 6 183 00111 7 213.5 01000 8 244 01001 9 274.5 01010 10 305 10000 0 0 10001 -1 -30.5 10010 -2 -61 10011 -3 -91.5 10100 -4 -122 10101 -5 -152.5 10110 -6 -183 10111 -7 -213.5 11000 -8 -244 11001 -9 -274.5 11010 -10 -305 ALARM Registers (10h to 15h) The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm registers (seconds, minutes, etc.) are used to make the comparison. Note that there is no alarm byte for year. The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm will be triggered once a match occurs between the alarm registers and the RTC FN7576.1 June 4, 2010 ISL12022MR5421 registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. Example 2 There are two alarm operation modes: Single Event and periodic Interrupt Mode: • Interrupts at one minute intervals when the seconds register is at 30 seconds. • Single Event Mode is enabled by setting Bit 7 on any of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and disabling the frequency output. This mode permits a one-time match between the Alarm registers and the RTC registers. Once this match occurs, the ALM bit is set to “1” and the IRQ/FOUT output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the auto-reset feature. • Set Alarm registers as follows: • Interrupt Mode is enabled by setting Bit 7 on any of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and disabling the frequency output. The IRQ/FOUT output will now be pulsed each time an alarm occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. To clear a single event alarm, the ALM bit in the status register must be set to “0” with a write. Note that if the ARST bit is set to 1 (address 08h, bit 7), the ALM bit will automatically be cleared when the status register is read. Following are examples of both Single Event and periodic Interrupt Mode alarms. Example 1 • Alarm set with single interrupt (IM = “0”) • A single alarm will occur on January 1 at 11:30 a.m. • Set Alarm registers as follows: BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, enabled HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, enabled MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30 a.m. on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register to “1” and also bringing the IRQ/FOUT output low. 21 • Pulsed interrupt once per minute (IM = “1”) BIT ALARM REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION SCA0 1 0 1 1 0 0 0 0 B0h Seconds set to 30, enabled MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled HRA0 0 0 0 0 0 0 0 0 00h Hours disabled DTA0 0 0 0 0 0 0 0 0 00h Date disabled MOA0 0 0 0 0 0 0 0 0 00h Month disabled DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled Once the registers are set, the following waveform will be seen at IRQ/FOUT: RTC AND ALARM REGISTERS ARE BOTH “30s” 60s FIGURE 14. IRQ/FOUT WAVEFORM Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared. Time Stamp VDD to Battery Registers (TSV2B) The TSV2B Register bytes are identical to the RTC register bytes, except they do not extend beyond the Month. The Time Stamp captures the FIRST VDD to Battery Voltage transition time, and will not update upon subsequent events until cleared (only the first event is captured before clearing). Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD register). Note that the time stamp registers are cleared to all “0”, including the month and day, which is different from the RTC and alarm registers (those registers default to 01h). This is the indicator that no time stamping has occurred since the last clear or initial power-up. Once a time stamp occurs, there will be a non-zero time stamp. Time Stamp Battery to VDD Registers (TSB2V) The Time Stamp Battery to VDD Register bytes are identical to the RTC register bytes, except they do not extend beyond Month. The Time Stamp captures the LAST transition of VBAT to VDD (only the last event of a series of power-up/power-down events is retained). Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD register). FN7576.1 June 4, 2010 ISL12022MR5421 TABLE 20. DST FORWARD REGISTERS ADDRESS FUNCTION 7 6 5 4 3 2 1 0 Month Forward DSTE 0 0 MoFd20 MoFd13 MoFd12 MoFd11 MoFd10 20h 21h Day Forward 0 DwFdE WkFd12 WkFd11 WkFd10 DwFd12 DwFd11 DwFd10 22h Date Forward 0 0 DtFd21 DtFd20 DtFd13 DtFd12 DtFd11 DtFd10 Hour Forward 0 0 HrFd21 HrFd20 HrFd13 HrFd12 HrFd11 HrFd10 23h TABLE 21. DST REVERSE REGISTERS ADDRESS NAME 7 6 5 4 3 2 1 0 Month Reverse 0 0 0 MoRv20 MoRv13 MoRv12 MoRv11 MoRv10 24h 25h Day Reverse 0 DwRvE WkRv12 WkRv11 WkRv10 DwRv12 DwRv11 DwRv10 26h Date Reverse 0 0 DtRv21 DtRv20 DtRv13 DtRv12 DtRv11 DtRv10 27h Hour Reverse 0 0 HrRv21 HrRv20 HrRv13 HrRv12 HrRv11 HrRv10 DST Control Registers (DSTCR) 8 bytes of control registers have been assigned for the Daylight Savings Time (DST) functions. DST beginning (set Forward) time is controlled by the registers DstMoFd, DstDwFd, DstDtFd, and DstHrFd. DST ending time (set Backward or Reverse) is controlled by DstMoRv, DstDwRv, DstDtRv and DstHrRv. Tables 20 and 21 describe the structure and functions of the DSTCR. DST FORWARD REGISTERS (20H TO 23H) DST forward is controlled by the following DST Registers: DST Enable DSTE is the DST Enabling Bit located in Bit 7 of register 20h (DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon powering up for the first time (including battery), the DSTE bit defaults to “0”. When DSTE is set to “1” the RTC time must be at least one hour before the scheduled DST time change for the correction to take place. When DSTE is set to “0”, the DSTADJ bit in the Status Register automatically resets to “0”. DST Month Forward DstMoFd sets the Month that DST starts. The format is the same as for the RTC register month, from 1 to 12. The default value for the DST begin month is 00h. DST Day/Week Forward DstDwFd contains both the Day of the Week and the Week of the Month data for DST Forward control. DST can be controlled either by actual date or by setting both the Week of the month and the Day of the Week. DstDwFdE sets the priority of the Day/Week over the Date. For DstDwFdE = 1, Day/Week is the priority. You must have the correct Day of Week entered in the RTC registers for the Day/Week correction to work properly. 22 • Bits 0, 1, 2 contain the Day of the week information which sets the Day of the Week that DST starts. Note that Day of the week counts from 0 to 6, like the RTC registers. The default for the DST Forward Day of the Week is 00h (normally Sunday). • Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST starts. The range is from 1 to 5, and Week 7 is used to indicate the last week of the month. The default for the DST Forward Week of the Month is 00h. DST Date Forward DstDtfd controls which Date DST begins. The format for the Date is the same as for the RTC register, from 1 to 31. The default value for DST forward date is 00h. DstDtFd is only effective if DstDwFdE = 0. DST Hour Forward DstHrFd controls the hour that DST begins. The RTC hour and DstHrFd registers have the same formats except there is no Military bit for DST hour. The user sets the DST hour with the same format as used for the RTC hour (AM/PM or MIL) but without the MIL bit, and the DST will still advance as if the MIL bit were there. The default value for DST hour Forward is 00h. DST REVERSE REGISTERS (24H TO 27H) DST end (reverse) is controlled by the following DST Registers: DST Month Reverse DstMoRv sets the Month that DST ends. The format is the same as for the RTC register month, from 1 to 12. The default value for the DST end month is October (10h). DST Day/Week Reverse DstDwRv contains both the Day of the Week and the FN7576.1 June 4, 2010 ISL12022MR5421 Week of the Month data for DST Reverse control. DST can be controlled either by actual date or by setting both the Week of the month and the Day of the Week. DstDwRvE sets the priority of the Day/Week over the Date. For DstDwRvE = 1, Day/Week is the priority. You must have the correct Day of Week entered in the RTC registers for the Day/Week correction to work properly. • Bits 0, 1, 2 contain the Day of the week information which sets the Day of the Week that DST ends. Note that Day of the week counts from 0 to 6, like the RTC registers. The default for the DST Reverse Day of the Week is 00h (normally Sunday). NPPM Registers (NPPM) The NPPM value is exactly 2x the net correction, in ppm, required to bring the oscillator to 0ppm error. The value is the combination of oscillator Initial Correction (IPPM) and crystal temperature dependent correction (CPPM). IPPM is used to compensate the oscillator offset at room temperature and is controlled by the ITR0 and BETA registers. This value is normally set during room temperature testing. • Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST ends. The range is from 1 to 5, and Week 7 is used to indicate the last week of the month. The default for the DST Reverse Week of the Month is 00h. The CPPM compensates the oscillator frequency fluctuation over-temperature. It is determined by the temperature (T), crystal curvature parameter (ALPHA), and crystal turnover temperature (XT0). T is the result of the temp sensor/ADC conversion, whose decimal result is 2x the actual temperature in Kelvin. ALPHA is from either the ALPHA (cold) or ALPHAH (hot) register depending on T, and XT0 is from the XT0 register. DST Date Reverse NPPM is governed by Equations 4 and 5: DstDtRv controls which Date DST ends. The format for the Date is the same as for the RTC register, from 1 to 31. The default value for DST Date Reverse is 00h. The DstDtRv is only effective if the DwRvE = 0. DST Hour Reverse TEMP Registers (TEMP) The temperature sensor produces an analog voltage output which is input to an A/D converter and produces a 10-bit temperature value in degrees Kelvin. TK07:00 are the LSBs of the code, and TK09:08 are the MSBs of the code. The temperature result is actually the average of two successive temperature measurements to produce greater resolution for the temperature control. The output code can be converted to °C by first converting from binary to decimal, dividing by 2, and then subtracting 273d. The practical range for the temp sensor register output is from 446d to 726d, or -50°C to +90°C. The temperature compensation function is only guaranteed over -40°C to +85°C. The TSE bit must be set to “1” to enable temperature sensing. TABLE 22. 6 5 4 3 2 1 0 TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 TK0M 0 0 2 ALPHA • ( T – T0 ) NPPM = IPPM + ---------------------------------------------------4096 (EQ. 4) 0 0 23 0 ALPHA = α • 2048 T is the reading of the ADC, result is 2 x temperature in degrees Kelvin. T = ( 2 • 298 ) + XT0 0 TK09 TK08 (EQ. 5) or T = 596 + XT0 Note that NPPM can also be predicted from the FATR and FDTR register by the relationship (all values in decimal): NPPM = 2*(BETA*FATR - (FDTR-16) XT0 Registers (XT0) TURNOVER TEMPERATURE (XT<3:0>) The apex of the Alpha curve occurs at a point called the turnover temperature, or XT0. Crystals normally have a turnover temperature between +20°C and +30°C, with most occurring near +25°C. TABLE 23. TURNOVER TEMPERATURE (EQ. 3) Temperature in °C = [(TK <9:0>)/2] - 273 7 NPPM = IPPM + CPPM where DstHrRv controls the hour that DST ends. The RTC hour and DstHrFd registers have the same formats except there is no Military bit for DST hour. The user sets the DST hour with the same format as used for the RTC hour (AM/PM or MIL) but without the MIL bit, and the DST will still advance as if the MIL bit were there. The default value for DST hour Reverse is 00h. TEMP NPPM = IPPM(ITR0, BETA) + ALPHA x (T-T0)2 ADDR 7 6 5 4 3 2 1 0 2Ch 0 0 0 XT4 XT3 XT2 XT1 XT0 The ISL12022MR5421 has a preset Turnover temperature corresponding to the crystal in the module. This value is recalled on initial power-up and is preset in device production. It is READ ONLY and cannot be overwritten by the user. Table 24 shows the values available, with a range from +17.5°C to +32.5°C in +0.5°C increments. The default value is 00000b or +25°C. FN7576.1 June 4, 2010 ISL12022MR5421 version, a scaled version of the absolute value of this coefficient is used in order to get an integer value. Therefore, ALP_H <7:0> is defined as the (|Actual Alpha Hot Value| x 2048) and converted to binary. For example, a crystal with Alpha Hot of -0.034ppm/°C2 is first scaled (|2048*(-0.034)| = 70d) and then converted to a binary number of 01000110b. TABLE 24. XT0 VALUES XT<4:0> TURNOVER TEMPERATURE 01111 32.5 01110 32.0 01101 31.5 01100 31 01011 30.5 01010 30 01001 29.5 01000 29.0 00111 28.5 00110 28.0 00101 27.5 00100 27.0 00011 26.5 00010 26.0 00001 25.5 00000 25.0 10000 25.0 10001 24.5 10010 24.0 10011 23.5 10100 23.0 10101 22.5 10110 22.0 10111 21.5 11000 21.0 11001 20.5 All communication over the I2C interface is conducted by sending the MSB of each byte of data first. 11010 20.0 Protocol Conventions 11011 19.5 11100 19.0 11101 18.5 11110 18.0 Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 15). On power-up of the ISL12022MR5421, the SDA pin is in the input mode. 11111 17.5 The practical range of Actual ALPHAH values is from -0.020 to -0.060. The ISL12022MR5421 has a preset ALPHAH value corresponding to the crystal in the module. This value is recalled on initial power-up and is preset in device production. It is READ ONLY and cannot be overwritten by the user. User Registers (Accessed by Using Slave Address 1010111x) Addresses [00h to 7Fh] These registers are 128 bytes of battery-backed user SRAM. The separate I2C slave address must be used to read and write to these registers. I2C Serial Interface The ISL12022MR5421 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL12022MR5421 operates as a slave device in all applications. ALPHA Hot Register (ALPHAH) TABLE 25. ALPHAH REGISTER ADDR 7 2Dh D 6 5 4 3 2 1 0 ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0 The ALPHA Hot variable is 7 bits and is defined as the temperature coefficient of Crystal from the XT0 value to +85°C (both Alpha Hot and Alpha Cold must be programmed to provide full temperature compensation). It is normally given in units of ppm/°C2, with a typical value of -0.034. Like the ALPHA Cold 24 All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL12022MR5421 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 15). A START condition is ignored during the power-up sequence. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 15). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. FN7576.1 June 4, 2010 ISL12022MR5421 SCL SDA DATA STABLE START DATA CHANGE DATA STABLE STOP FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH SDA OUTPUT FROM RECEIVER START ACK FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA S T A R T IDENTIFICATION BYTE 1 1 0 1 1 1 1 0 SIGNALS FROM THE ISL12022MR5421 ADDRESS BYTE S T O P DATA BYTE 0 0 0 0 A C K A C K A C K FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN) An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 16). The ISL12022MR5421 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again, after successful receipt of an Address Byte. The ISL12022MR5421 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. Device Addressing Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifiers. These bits are “1101111” for the RTC registers and “1010111” for the User SRAM. 25 The last bit of the Slave Address Byte defines a read or write operation to be performed. When this R/W bit is a “1”, a read operation is selected. A “0” selects a write operation (refer to Figure 18). After loading the entire Slave Address Byte from the SDA bus, the ISL12022MR5421 compares the device identifier and device select bits with “1101111” or “1010111”. Upon a correct compare, the device outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word address is either supplied by the master device or obtained from an internal counter. On power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. When required, as part of a random read, the master must supply the 1 Word Address Bytes, as shown in Figure 20. In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the FN7576.1 June 4, 2010 ISL12022MR5421 “read” section. For a random read of the Control/Status Registers, the slave byte must be “1101111x” in both places. SLAVE ADDRESS BYTE 1 1 0 1 1 1 1 R/ A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE FIGURE 18. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES Write Operation A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL12022MR5421 responds with an ACK. At this time, the I2C interface enters a standby state. Read Operation A Read operation consists of a three byte instruction, followed by one or more Data Bytes (see Figure 20). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL12022MR5421 responds with an ACK. Then the ISL12022MR5421 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (see Figure 20). The Data Bytes are from the memory location indicated by an internal pointer. This pointer’s initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 2Fh, the pointer “rolls over” to 00h, and the device continues to output data for each ACK received. Application Section Battery Backup Details The ISL12022MR5421 has automatic switchover to battery backup when the VDD drops below the VBAT mode threshold. A wide variety of backup sources can be used, including standard and rechargeable lithium, supercapacitors, or regulated secondary sources. The serial interface is disabled in battery backup, while the oscillator and RTC registers are operational. The SRAM register contents are powered to preserve their contents as well. The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind the temperature compensation only operates for VBAT > 2.7V. Note that the device is not guaranteed to operate with a VBAT < 1.8V, so the battery 26 should be changed before discharging to that level. It is strongly advised to monitor the low battery indicators in the status registers and take action to replace discharged batteries. If a supercapacitor is used, it is possible that it may discharge to below 1.8V during prolonged power-down. Once powered up, the device may lose serial bus communications until both VDD and VBAT are powered down together. To avoid that situation, including situations where a battery may discharge deeply, the circuit in Figure 19 can be used. VDD = 2.7V ISL12022MR5421 JBAT TO 5.5V VDD VBAT CIN CBAT 0.1µF 0.1µF DBAT BAT43W VBAT = 1.8V + TO 3.2V GND FIGURE 19. SUGGESTED BATTERY BACKUP CIRCUIT The diode, DBAT will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. The jumper is added as a safeguard should the battery ever need to be disconnected from the circuit. The VDD negative slew rate should be limited to below the data sheet spec (10V/ms) otherwise battery switchover can be delayed, resulting in SRAM contents corruption and oscillator operation interruption. Some applications will require separate supplies for the RTC VDD and the I2C pull-ups. This is not advised, as it may compromise the operation of the I2C bus. For applications that do require serial bus communication with the RTC VDD powered down, the SDA pin must be pulled low during the time the RTC VDD ramps down to 0V. Otherwise, the device may lose serial bus communications once VDD is powered up, and will return to normal operation ONLY once VDD and VBAT are both powered down together. Layout Considerations The ISL12022MR5421 contains a quarts crystal and requires special handling during PC board assembly. Excessive shock and vibrations should be avoided, especially with automated handling equipment. Ultrasound cleaning is not advisable as it subjects the crystal to resonance and possible failure. See also Note 5 on page 5 in the specifications tables, which pertains to solder reflow effects on oscillator accuracy. The part of the package that has NC pins from pin 1 to 5 and from pin 16 to 20 contains the crystal. Low frequency RTC crystals are known to pick up noise very easily if layout precautions are not followed, even embedded within a plastic package. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful FN7576.1 June 4, 2010 ISL12022MR5421 SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 S T IDENTIFICATION A BYTE WITH R R/W = 1 T ADDRESS BYTE S T O P A C K 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 A C K A C K SIGNALS FROM THE SLAVE A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN) layout of the RTC circuit will avoid noise pickup and insure accurate clocking. Figure 21 shows a suggested layout for the ISL12022MR5421 device. The following main precautions should be followed: • Do not run the serial bus lines or any high speed logic lines in the vicinity of pins 1 and 20, or under the package. These logic level lines can induce noise in the oscillator circuit, causing misclocking. • Add a ground trace around the device with one end terminated at the chip ground. This guard ring will provide termination for emitted noise in the vicinity of the RTC device • Be sure to ground pins 6 and 15 as well as pin 8 as these all insure the integrity of the device ground • Add a 0.1µF decoupling capacitor at the device VDD pin, especially when using the 32.768kHz FOUT function. The best way to run clock lines around the RTC is to stay outside of the ground ring by at least a few millimeters. Also, use the VBAT and VDD as guard ring lines as well, they can isolate clock lines from the oscillator section. In addition, if the IRQ/FOUT pin is used as a clock, it should be routed away from the RTC device as well. GROUND RING FOUT SCL SDA FIGURE 21. SUGGESTED LAYOUT FOR THE ISL12022MR5421 27 Measuring Oscillator Accuracy The best way to analyze the ISL12022MR5421 frequency accuracy is to set the IRQ/FOUT pin for a specific frequency, and look at the output of that pin on a high accuracy frequency counter (at least 7 digits accuracy). Note that the IRQ/FOUT is an drain output and will require a pull-up resistor. Using the 1.0Hz output frequency is the most convenient as the ppm error is expressed in Equation 6: ppm error = F OUT – 1 • 1e6 (EQ. 6) Other frequencies may be used for measurement but the error calculation becomes more complex. Use the FOUT output and a frequency counter for the most accurate results. Also, when the proper layout guidelines above are observed, the oscillator should start-up in most circuits in less than one second. Temperature Compensation Operation The ISL12022MR5421 temperature compensation feature needs to be enabled by the user. This must be done in a specific order as follows. 1. Read register 0Dh, the BETA register. This register contains the 5-bit BETA trimmed value, which is automatically loaded on initial power-up. Mask off the 5 LSB’s of the value just read. 2. Bit 7 of the BETA register is the master enable control for temperature sense operation. Set this to “1” to allow continuous temperature frequency correction. Frequency correction will then happen every 60 seconds with VDD applied. 3. Bits 5 and 6 of the BETA register control temperature compensation in battery backup mode (see Table 15). Set the values for the operation desired. 4. Write back to register 0Dh making sure not to change the 5 LSB values, and include the desired compensation control bits. Note that every time the BETA register is written with the TSE bit = 1, a temperature compensation cycle is instigated and a new correction value will be loaded into the FATR/FDTR registers (if the temperature changed since the last conversion). Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA registers, are READ-ONLY, and cannot be written to. Also the value for BETA is locked and cannot be changed with a write. However, It is still a good idea to FN7576.1 June 4, 2010 ISL12022MR5421 do the bit masking when doing TSE bit changes. Daylight Savings Time (DST) Example DST involves setting the forward and back times and allowing the RTC device to automatically advance the time or set the time back. This can be done for current year, and future years. Many regions have DST rules that use standard months, weeks and time of the day, which permit a pre-programmed, permanent setting. Table 26 shows an example setup for the ISL12022MR5421. TABLE 26. DST EXAMPLE VARIABLE VALUE Month Forward and DST Enable April REGISTER VALUE 15h 84h Week and Day Forward 1st Week and 16h and select Day/Week, Sunday not Date 48h Date Forward not used 17h 00h Hour Forward 2am 18h 02h Month Reverse October 19h 10h Week and Day Reverse Last Week and select Day/Week, and Sunday not Date 1Ah 78h Date Reverse not used 1Bh 00h Hour Reverse 2am 1Ch 02h The Enable bit (DSTE) is in the Month forward register, so the BCD value for that register is altered with the additional bit. The Week and Day values along with Week/Day vs Date select bit is in the Week/Day register, so that value is also not straight BCD. Hour and Month are normal BCD, but the Hour doesn’t use the MIL bit since Military time PM values are already discretely different from AM/PM time PM values. The DST reverse setting utilizes the option to select the last week of the month for October, which could have 4 or 5 weeks but needs to have the time change on the last Sunday. Note that the DSTADJ bit in the status register monitors whether the DST forward adjustment has happened. When it is “1”, DST forward has taken place. When it is “0”, then either DST reverse has happened, or it has been reset either by initial power-up or if the DSTE bit has been set to “0”. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 5/27/10 FN7576.1 Changed CDM in “ESD Rating” on page 5 from >1500V to >2200V 03/22/10 FN7576.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php 28 FN7576.1 June 4, 2010 ISL12022MR5421 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H M 0.25(0.010) B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B C 0.10(0.004) M C A M 0.25(0.010) SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.014 0.019 0.35 0.49 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e α B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 20 0° 20 8° 0° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8° Rev. 2 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 FN7576.1 June 4, 2010