MCP8024 3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module Features: Description: • Three Half-bridge Drivers Configured to Drive External High-Side NMOS and Low-Side NMOS MOSFETs: The MCP8024 is a 3-Phase Brushless DC (BLDC) power module. The MCP8024 device integrates three half-bridge drivers to drive external NMOS/NMOS transistor pairs configured to drive a 3-phase BLDC motor, a comparator, a voltage regulator to provide bias to a companion microcontroller, power monitoring comparators, an overtemperature sensor, two level translators and three operational amplifiers for motor current monitoring. - Independent input control for high-side NMOS and low-side NMOS MOSFETs - Peak output current: 0.5A @ 12V - Shoot-through protection - Overcurrent and short circuit protection • Adjustable Output Buck Regulator (750 mW) • Fixed Output Linear Regulators: - 5V @ 20 mA - 12V @ 20 mA • Internal Bandgap Reference • Three Operational Amplifiers for Motor Phase Current Monitoring and Position Detection • Overcurrent Comparator • Two Level Translators • Operational Voltage Range 6 - 40V • Undervoltage Lockout (UVLO): 6V • Overvoltage Lockout (OVLO): 28V • Transient (100 ms) Voltage Tolerance: 48V • Extended Temperature Range: TA -40 to +150°C The MCP8024 has three half-bridge drivers capable of delivering a peak output current of 0.5A at 12V for driving high-side and low-side NMOS MOSFET transistors. The drivers have shoot-through, overcurrent, and short-circuit protection. The MCP8024 buck converter is capable of delivering 750 mW of power for powering a companion microcontroller. The buck regulator may be disabled if not used. The on-board 5V and 12V low dropout voltage regulators are capable of delivering 20 mA of current. The MCP8024 operation is specified temperature range of -40°C to +150°C. over a Package options include the 40-lead 5x5 QFN and 48lead 7x7 TQFP. • Thermal Shutdown Applications: • Automotive Fuel, Water, Ventilation Motors • Home Appliances • Permanent Magnet Synchronous Motor (PMSM) Control • Hobby Aircraft, Boats, Vehicles Related Literature: • AN885, “Brushless DC (BLDC) Motor Fundamentals”, DS00885, Microchip Technology Inc., 2003 • AN1160, “Sensorless BLDC Control with BackEMF Filtering Using a Majority Function”, DS01160, Microchip Technology Inc., 2008 • AN1078, “Sensorless Field Oriented Control of a PMSM”, DS01078, Microchip Technology Inc., 2010 2013 Microchip Technology Inc. DS20005228A-page 1 MCP8024 Package Types DE2 CAP1 CAP2 +5V FB VDD VDD LX 43 42 41 40 39 38 37 LX 31 PWM3L VDD 32 44 FB 33 45 +5V 34 PWM3H CAP2 35 46 CAP1 36 PWM2H DE2 37 PWM2L PWM3L 38 47 PWM3H + 48 PWM2L 39 MCP8024 40 MCP8024 PWM1L 1 36 PGND PWM1H 2 35 PGND PWM2H 1 30 +12V PWM1L 2 29 VBA CE 3 34 +12V PWM1H 3 28 VBB LV_OUT2 4 33 VBA CE 4 27 VBC HV_IN2 5 32 VBB HV_IN1 5 26 PHA HV_IN1 6 31 VBC LV_OUT1 6 25 PHB PGND 7 30 PHA IOUT3 7 24 PHC LV_OUT1 8 29 PHB ISENSE3- 8 23 HSA IOUT3 9 28 PHC ISENSE3+ 9 22 HSB IOUT2 10 21 HSC 7mm x 7mm TQFP-48 ISENSE3- 10 27 HSA ISENSE3+ 11 26 HSB IOUT2 12 25 HSC 13 14 15 16 17 18 19 20 21 22 23 24 ISENSE2- ISENSE2+ ILIMIT_OUT I_OUT1 I_SENSE1- I_SENSE1+ PGND PGND LSA LSB LSC PGND 20 LSC 18 19 LSB LSA 17 PGND 16 I_SENSE1+ 15 I_SENSE1- 14 13 12 DS20005228A-page 2 I_OUT1 ILIMIT_OUT ISENSE2- ISENSE2+ 11 5mm x 5mm QFN-40 2013 Microchip Technology Inc. MCP8024 Functional Block Diagram COMMUNICATION PORT BIAS GENERATOR VDD HV_IN1 LV_OUT1 HV_IN2 LV_OUT2 I LDO O I CAP1 O CHARGE PUMP LEVEL TRANSLATOR CE +12V LDO I CAP2 +5V BUCK SMPS LX FB SUPERVISOR DE2 MOTOR CONTROL UNIT VBA VBB VBC VDD PWM1H PWM1L PWM2H PWM2L PWM3H PWM3L O HSA O HSB O HSC I I GATE I CONTROL I I I LOGIC I I I PHA PHB PHC DRIVER FAULT O +12V O LSA O LSB O LSC PGND ILIMIT_REF + ILIMIT_OUT I_OUT1 I_OUT2 I_OUT3 2013 Microchip Technology Inc. + I_SENSE1+ - I_SENSE1- + I_SENSE2+ - I_SENSE2- + I_SENSE3+ - I_SENSE3- DS20005228A-page 3 DS20005228A-page 4 I_OUT3 I_OUT2 I_OUT1 ILIMIT_OUT I PWM1H PWM1L PWM2H PWM2L PWM3H PWM3L DRIVER FAULT I CE O - + GATE I CONTROL I LOGIC I I I VDD LEVEL TRANSLATOR I O I O HV_IN1 LV_OUT1 HV_IN2 LV_OUT2 O O O I I I O O O +12V - + - + - + MOTOR CONTROL UNIT COMMUNICATION PORT ILIMIT_REF DE2 SUPERVISOR I_SENSE3- I_SENSE3+ I_SENSE2- I_SENSE2+ I_SENSE1- I_SENSE1+ PGND LSC LSB LSA PHA PHB PHC HSC HSB HSA VBA VBB VBC LX FB +5V CAP2 CAP1 +12V VDD BUCK SMPS LDO CHARGE PUMP LDO BIAS GENERATOR +12V 100 nF Ceramic VADJ B A C + _ E MCP8024 Typical Application Circuit 2013 Microchip Technology Inc. MCP8024 1.0 ESD and Latch-up protection: VDD, HV_IN1 pins 12 kV HMM and 750V CDM All other pins ...................... 4 kV HBM and 750V CDM Latch-up protection - all pins............................... > 100 mA ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Input Voltage, VDD........................................................+46.0V Input Voltage, < 100 ms Transient ...............................+48.0V Internal Power Dissipation ...........................Internally-Limited Operating Ambient Temperature Range .......-40°C to +150°C Operating Junction Temperature (Note 1).....-40°C to +160°C Transient Junction Temperature* ................................ +170°C Storage temperature (Note 1) .......................-55°C to +150°C Digital I/O .......................................................... -0.3V to 5.5V LV Analog I/O .................................................... -0.3V to 5.5V * Notice: Transient junction temperatures should not exceed one second in duration. Sustained junction temperatures above 170°C may impact the device reliability. AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted TJ = -40°C to +150°C. Parameters Symbol Min. Typ. Max. Units Conditions VDD 6.0 6.0 — — 28.0 40 V Operating Shutdown VDDmax — — 48 V < 100 ms IQ — — — — — — — 171 197 200 200 900 — 220 — — 500 — A VDD = 13V, disabled, CE = 0V, TJ = 25°C disabled, CE = 0V, TJ = 85°C disabled, CE = 0V, TJ = 130°C disabled, CE = 0V, TJ = 150°C active, CE > VDIG_HI_TH Digital Input/Output DIGITALI/O 0 — 5.5 V Digital Open-Drain Drive Strength DIGITALIOL — 1 — mA Digital Input Rising Threshold VDIG_HI_TH 1.26 — — V Digital Input Falling Threshold VDIG_LO_TH — — 0.54 V VDIG_HYS — 500 — mV IDIG — — 30 0.2 100 — µA VDIG = 3.0V VDIG = 0V ANALOGVIN 0 — 5.5 V Excludes high voltage ANALOGVOUT 0 — VOUT5 V Excludes high voltage Power Supply Input Input Operating Voltage Transient Maximum Voltage Input Quiescent Current Digital Input Hysteresis Digital Input Current Analog Low-Voltage Input Analog Low-Voltage Output VDS < 50 mV BIAS GENERATOR +12V Regulated Charge Pump Charge Pump Current ICP 20 — — mA Charge Pump Voltage VCP +10 2 * VDD — V VDD = 9.0V, ICP = 20 mA CPSTART 11.0 11.5 — V VDD falling Charge Pump Start Note 1: 2: VDD = 9.0V The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention. 1000 hour cumulative maximum for OTP data retention (typical). 2013 Microchip Technology Inc. DS20005228A-page 5 MCP8024 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted TJ = -40°C to +150°C. Parameters Symbol Min. Typ. Max. Charge Pump Stop CPSTOP Charge Pump Frequency (50% charging / 50% discharging) CPFSW — 12.0 12.5 V — — 76.80 0 — — kHz CPRDSON — 14 — Ω RDSON sum of high side and low side VOUT12 10 12 — V VDD = VOUT12 + 1V, IOUT = 1 mA |TOLVOUT12| — — 4.0 % VDD = VOUT12 + 1V, IOUT = 1 mA Output Current IOUT 20 — — mA Average current Output Current Limit ILIMIT 30 40 — mA Average current TCVOUT12 — 50 — ppm/°C Line Regulation |VOUT/ (VOUTXVDD)| — 0.1 0.5 %/V Load Regulation |VOUT/VOUT| — 0.2 0.5 % Dropout Voltage VDD-VOUT12 — 380 — mV IOUT = 20 mA, measurement taken when output voltage drops 2% from no-load value. PSRR — 60 — dB f = 1 kHz, IOUT = 10 mA VOUT5 — 5 — V VDD = VOUT5 + 1V, IOUT = 1 mA |TOLVOUT5| — — 4.0 % IOUT 20 — — mA Average current Average current Charge Pump Switch Resistance Output Voltage Output Voltage Tolerance Output Voltage Temperature Coefficient Power Supply Rejection Ratio Units Conditions VDD rising VDD = 9.0V VDD = 12.5V (stopped) 13V < VDD < 19V, IOUT = 20 mA IOUT = 0.1 mA to 15 mA +5V Linear Regulator Output Voltage Output Voltage Tolerance Output Current ILIMIT 30 40 — mA |TCVOUT5| — 50 — ppm/°C Line Regulation |VOUT/ (VOUTXVDD)| — 0.1 0.5 %/V Load Regulation |VOUT/VOUT| — 0.2 0.5 % Dropout Voltage VDD-VOUT5 — 180 350 mV IOUT = 20 mA, measurement taken when output voltage drops 2% from no-load value. PSRR — 60 — dB f = 1 kHz, IOUT = 10 mA VFB 1.19 1.25 1.31 V TOLVFB — — 5.0 % Output Current Limit Output Voltage Temperature Coefficient Power Supply Rejection Ratio 6V < VDD < 19V, IOUT = 20 mA IOUT = 0.1 mA to 15 mA Buck Regulator Feedback Voltage Feedback Voltage Tolerance Note 1: 2: IFB = 1 µA The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention. 1000 hour cumulative maximum for OTP data retention (typical). DS20005228A-page 6 2013 Microchip Technology Inc. MCP8024 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted TJ = -40°C to +150°C. Parameters Symbol Min. Typ. Max. Units Feedback Voltage Line Regulation VFB/VFB) / VDD| — 0.1 0.5 %/V Feedback Voltage Load Regulation VFB / VFB| — 0.1 0.5 % IOUT = 5 mA to 150 mA Feedback Input Bias Current IFB -100 — +100 nA Sink/Source Switching Frequency fSW — 461 — kHz Duty Cycle Range DCMAX 3 — 96 % PMOS Switch On Resistance RDSON — 0.6 — Ω PMOS Switch Current Limit IP(MAX) — 2.5 — A IGND — 1.5 2.5 mA Switching IQ — 150 200 A IOUT = 0mA Ground Current – PWM Mode Quiescent Current – PFM Mode Conditions VDD = 6V to 28V VDD = 13V, TJ=25°C Output Voltage Adjust Range VOUT 2.0 — 5.0 V Output Current IOUT 150 — — mA 250 — — POUT — 750 — mW Undervoltage Lockout Start UVLOSTRT — 6.0 6.25 V VDD rising Undervoltage Lockout Stop UVLOSTOP 5.1 5.5 — V VDD falling Undervoltage Lockout Hysteresis UVLOHYS 0.35 0.5 0.65 V Overvoltage Lockout All Functions Disabled OVLOSTOP — 32.0 33.0 V VDD rising Overvoltage Lockout All Functions Enabled OVLOSTRT 29.0 30.0 — V VDD falling Overvoltage Lockout Hysteresis OVLOHYS 1.0 2.0 3.0 V TWARN — 72 — % Rising temperature, percentage of thermal shutdown temperature “MIN” TWARN — 15 — °C Falling temperature TSD 160 170 — °C Rising temperature TSD — 25 — °C Falling temperature RPULLDN 32 47 62 kΩ Output Power 5v 3v P = IOUT * VOUT Voltage Supervisor Temperature Supervisor Thermal Warning Temperature (115°C) Thermal Warning Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis MOTOR CONTROL UNIT Output Drivers PWMH/L Input Pull-Down Note 1: 2: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention. 1000 hour cumulative maximum for OTP data retention (typical). 2013 Microchip Technology Inc. DS20005228A-page 7 MCP8024 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted TJ = -40°C to +150°C. Parameters Symbol Min. Typ. Max. Units Output Driver Source Current ISOURCE 0.3 — — A VDD = 12V, H[A:C], L[A:C] ISINK 0.3 — — A VDD = 12V, H[A:C], L[A:C] Output Driver Source Resistance RDSON — 17 — Ω IOUT = 10 mA, VDD = 12V, H[A:C], L[A:C] Output Driver Sink Resistance RDSON — 17 — Ω IOUT = 10 mA, VDD = 12V, H[A:C], L[A:C] Output Driver UVLO Threshold DUVLO 7.2 8.0 — V VBOOTSTRAP — — — — 44 48 V Continuous < 100 ms Output Driver HS Drive Voltage VHS 8.0 -5.5 12 — 13.5 — V With respect to Phase pin With respect to ground Output Driver LS Drive Voltage VLS 8.0 12 13.5 V With respect to ground VPHASE -5.5V — 34 V With respect to ground DSC — — — — — — 0.250 0.500 0.750 1.000 — — — — — V Set by DE2 CONFIG[1:0] word 00 - Default 01 10 11 Output Driver Short Circuit Detected Propagation Delay DSC_DEL — — — — — 430 10 — — — — — ns CLOAD = 1000 pF, VDD =12V, detection after blanking detection during blanking, value is delay after blanking Output Driver Turn-off Propagation Delay TDEL_OFF — 100 250 ns CLOAD = 1000 pF, VDD =12V, Output Driver Turn-on Propagation Delay TDEL_ON — 100 250 ns CLOAD = 1000 pF, VDD =12V, Standby to Motor Operational (CLOAD = 10 µF) tMOTOR — 10 50 µs tSTANDBY tFAULT_CLR — — 1 — 10 — 10 — — ms µs µs CE High-Low-High Transition < 100 µs (Fault Clearing) Standby state to Operational state Time after CE = 0V CE High-Low-High Transition Time VOS -3.0 — +3.0 mV VOS/TA — 2.0 — V/°C Output Driver Sink Current Output Driver Bootstrap Voltage (w/ respect to ground) Output Driver Phase Pin Voltage Output Driver Short Circuit Protection Threshold CE Low to Standby State CE Fault Clearing Pulse Conditions Current Sense Amplifier Input Offset Voltage Input Offset Temperature Drift Input Bias Current Common Mode Input Range Note 1: 2: IB -1 — +1 µA VCMR -0.3 — 3.5 V VCM = 0V TA = -40°C to +150°C VCM = 0V The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention. 1000 hour cumulative maximum for OTP data retention (typical). DS20005228A-page 8 2013 Microchip Technology Inc. MCP8024 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted TJ = -40°C to +150°C. Parameters Common Mode Rejection Ratio Maximum Output Voltage Swing Slew Rate Symbol Min. Typ. Max. Units Conditions CMRR 65 80 — dB Freq = 1 kHz, IOUT = 10 µA VOL, VOH 0.05 — 4.5 V IOUT = 200 µA SR — 7 — V/s Symmetrical Gain Bandwidth Product GBWP — 10.0 — MHz Current Comparator Hysteresis CCHYS — 10 — mV VCC_CMR 1.0 — 4.5 V — 8 — Bits VOL, VOH 0.991 — 4.503 V IOUT = 1 mA VDAC — — — — — 0.991 1.872 4.503 — — — — V Code * 13.77 mV/Bit + 0.991V Code 00H Code 40H Code FFH Current Comparator Common Mode Input Range Current Limit DAC Resolution Output Voltage Range Output Voltage Input to Output Delay TDELAY — 50 — µs Integral Nonlinearity INL -0.5 — +0.5 %FSR %Full Scale Range 5 time constants of 100 kHz filter Differential Nonlinearity DNL -50 — +50 %LSB %LSB ILIMIT_OUT Sink Current (Open-Drain) ILOUT — 1 — mA High-Voltage Input Range VIN 0 — VDD V Low-Voltage Output Range VOUT 0 — 5.0V V VILIMIT_OUT <= 50mV Voltage Level Translator Input Pull-up Resistor RPU 20 30 47 kΩ High-Level Input Voltage VIH 0.60 — — VDD VDD = 15V Low-Level Input Voltage VIL — — 0.40 VDD VDD = 15V Input Hysteresis VHYS — — 0.30 VDD TLV_OUT — 3.0 6.0 µs Maximum Communication Frequency FMAX — — 20 kHz Low-Voltage Output Sink Current (Open-Drain) IOL — 1 — mA HTOL — 1000 — Hours TJ = 150°C (Note 2) — 10 — Years TJ = 85°C Propagation Delay VOUT <= 50 mV OTP Data Retention OTP Cell High Temperature Operating Life OTP Cell Operating Life Note 1: 2: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation may cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 150°C can impact the device reliability and OTP data retention. 1000 hour cumulative maximum for OTP data retention (typical). 2013 Microchip Technology Inc. DS20005228A-page 9 MCP8024 TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges (Notes 1) Specified Temperature Range TA -40 +150 °C Operating Temperature Range TA -40 +150 °C Storage Temperature Range TA -55 +150 °C 5mm x 5mm QFN-40 JA JC — — 34 5.2 — — °C/W 4-Layer JC51-7 standard board, natural convection 7mm x 7mm TQFP-48-EP JA JC — — 30 15 — — °C/W (Note 2) Thermal Package Resistance Note 1: 2: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 150°C rating. Sustained junction temperatures above 150°C can impact the device reliability. 1000 hour cumulative maximum for OTP data retention (typical). ESD, SUSCEPTIBILITY, SURGE, AND LATCH-UP TESTING Parameter Standard and Test Condition Input voltage surges ISO 16750-2 ESD HBM with 1.5 k / 100 pF ESD-STM5.1-2001 JESD22-A114E 2007 CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref_D ESD-STM5.3.1-1999 ESD CDM (Charged Device Model, fieldinduced method – replaces machine-model method) Latch-up Susceptibility AEC Q100-004, 150°C DS20005228A-page 10 Value 28V for 1 minute, 45V for 0.5 seconds +4 kV +750 V all pins >100 mA 2013 Microchip Technology Inc. MCP8024 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise indicated: TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant. 0 0.010 -10 -20 VOUT = 5V PSRR (dB) Line Reg (%/V) 0.008 0.006 0.004 -30 -40 -50 -60 -70 -80 0.002 -90 VOUT = 12V -100 0.000 -45 -30 -15 0 15 30 45 60 75 90 0.01 105 120 135 150 0.10 1.00 100.00 1000.00 FIGURE 2-4: 12 V LDO Power Supply Ripple Rejection vs Frequency. FIGURE 2-1: LDO Line Regulation vs Temperature. 0.35 140.0 VOUT = 5V 120.0 Current (mA) 0.30 Load Reg (%) 10.00 Frequency (kHz) Temperature (°C) 0.25 0.20 VOUT = 12V 0.15 0.10 12V LDO 100.0 5V LDO 80.0 60.0 40.0 20.0 0.05 0.0 0.00 -30 -15 0 15 30 45 60 75 90 105 120 135 7 150 10 13 16 FIGURE 2-2: LDO Load Regulation vs Temperature. 18 0 25 28 Volts (V) -30 -40 -50 -60 -70 -80 15 150 12 100 9 50 Vout (AC) 6 0 3 Cin = Cout = 10 µF Iout = 20 mA -90 0 -100 0.10 1.00 10.00 100.00 1000.00 Frequency (kHz) FIGURE 2-3: 5V LDO Power Supply Ripple Rejection vs Frequency. 2013 Microchip Technology Inc. 31 200 Vin = 15V Vin = 14V -20 PSRR (dB) 22 FIGURE 2-5: LDO Short Circuit Current vs Input Voltage. . -10 0.01 19 Voltage (V) Temperature (°C) Volts (mV) -45 -50 -100 0 50 100 150 200 250 Time (µs) FIGURE 2-6: 5V LDO Dynamic Linestep Rising VDD. DS20005228A-page 11 MCP8024 Note: Unless otherwise indicated: TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant. 18 180 Vin = 15V 40 Vin = 14V 15 120 12 60 9 0 Vin = 14V Vout = 5V Cin = Cout = 10 µF Iout = 1 mA to 20 mA Step 30 -60 Vout (mV) Vout (AC) 6 Volts (mV) Volts (V) 20 10 Vout (AC) 0 -10 -20 3 -120 Cin = Cout = 10 µF Iout = 20 mA 0 -30 -180 0 50 100 150 200 -40 250 0 5 Time (µs) 40 15 210 30 12 140 9 70 Vin = 15V 0 3 -70 Vout (mV) 6 Volts (mV) Volts (V) Vout (AC) 10 0 -10 Vin = 14V Vout = 5V Cin = Cout = 10 µF Iout = 20 mA to 1 mA Step -20 Cin = Cout = 10 µF Iout = 20 mA 0 -30 -140 50 100 150 200 -40 250 0 5 180 40 15 120 30 12 60 Vin = 14V 20 25 Vin = 14V Vout = 12V Cin = Cout = 10 µF Iout = 1 mA to 20 mA Step 0 Vout (AC) 6 -60 Vout (mV) 9 Volts (mV) 20 Volts (V) 15 FIGURE 2-11: 5V LDO Dynamic Loadstep Falling Current. FIGURE 2-8: 12V LDO Dynamic Linestep Rising VDD. Vin = 15V 10 Time (ms) Time (µs) 18 25 Vout (AC) 20 0 20 FIGURE 2-10: 5V LDO Dynamic Loadstep Rising Current. 280 Vin = 14V 15 Time (ms) FIGURE 2-7: 5V LDO Dynamic Linestep Falling VDD. 18 10 Vout (AC) 10 0 -10 -20 3 Cin = Cout = 10 µF Iout = 20 mA 0 -120 -180 0 50 100 150 200 250 Time (µs) FIGURE 2-9: 12V LDO Dynamic Linestep Falling VDD. DS20005228A-page 12 -30 -40 0 5 10 15 20 25 Time (ms) FIGURE 2-12: 12V LDO Dynamic Loadstep Rising Current. 2013 Microchip Technology Inc. MCP8024 Note: Unless otherwise indicated: TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant. 40 30 PHA 10 BEMF Vout (mV) 20 0 -10 PHB Vin = 14V Vout = 12V Cin = Cout = 10 µF Iout = 20 mA to 1 mA Step Vout (AC) -20 -30 PHC -40 0 5 10 15 20 25 0.0 0.5 1.0 Time (ms) 1.5 2.0 2.5 Time ( ms) FIGURE 2-16: Trapezoidal Back EMF. FIGURE 2-13: 12V LDO Dynamic Loadstep Falling Current. 13.0 Charge Pump Hysteresis Vout (V) 12.5 PWMxH 12.0 11.5 11.0 Vout = 12V Cin = Cout = 10 µF Iout = 20 mA 10.5 Dead Time Dead Time PWMxL 10.0 0 5 10 15 20 25 30 0 10 20 Vin (V) 40 50 60 FIGURE 2-17: PWM Deadtime. FIGURE 2-14: 12V LDO Output Voltage vs Rising Input Voltage. 20 1200 Switch ON CE High 1000 16 800 VLX (V) Quiescent Current (µA) 30 Time (µs) 600 12 No Snubber Snubber 8 400 CE Low 4 200 0 -45 -20 5 30 55 80 105 Temperature (°C) FIGURE 2-15: Quiescent Current vs Temperature. 2013 Microchip Technology Inc. 130 155 0 0.10 0.12 0.14 0.16 0.18 0.20 Time (µs) FIGURE 2-18: Buck Snubber Turn On. DS20005228A-page 13 MCP8024 Note: Unless otherwise indicated: TA = +25°C; Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction temperature over the Ambient temperature is not significant. 20 16 Switch Off VLX (V) 12 No Snubber Snubber 8 4 0 -4 0.06 0.08 0.10 0.12 0.14 0.16 0.18 Time (µs) FIGURE 2-19: Buck Snubber Turn Off. 30.00 Hx Highside MOSFET 25.00 Hx Lowside MOSFET RDSON (:) 20.00 15.00 Lx Highside MOSFET 10.00 5.00 Lx Lowside MOSFET 0.00 -40 -15 10 35 60 85 110 135 160 Temperature (°C) FIGURE 2-20: Gate Driver RDSON vs Temperature. DS20005228A-page 14 2013 Microchip Technology Inc. MCP8024 3.0 PIN DESCRIPTIONS 3.1 Functional Pin Descriptions Pin No. Pin No. QFN TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 EP 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19,20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35,36 37 38, 39 40 41 42 43 44 45 46 47 EP Symbol I/O Description PWM2H PWM1L PWM1H CE LV_OUT2 HV_IN2 HV_IN1 PGND LV_OUT1 I_OUT3 ISENSE3ISENSE3+ I_OUT2 ISENSE2ISENSE2+ /ILIMIT_OUT I_OUT1 ISENSE1ISENSE1+ PGND LA LB LC PGND HC HB HA PHC PHB PHA VBC VBB VBA +12V PGND LX VDD FB +5V CAP2 CAP1 DE2 PWM3L PWM3H PWM2L PGND I I I I O I I Power O O I I O I I O O I I Power O O O Power O O O I/O I/O I/O Power Power Power Power Power Power Power I Power Power Power O I I I Power Digital input, phase B high-side control, 47K pulldown Digital input, phase A low-side control, 47K pulldown Digital input, phase A high-side control, 47K pulldown Digital input, device enable, 47K pulldown Digital logic level translated output interface, open drain High-voltage input interface, 30K pullup via Configuration register 0 bit 6 High-voltage input interface, 30K pullup via Configuration register 0 bit 6 Power 0V reference Digital logic level translated output interface, open drain Motor phase current sense amplifier output Motor phase current sense amplifier inverting input Motor phase current sense amplifier non-inverting input Motor phase current sense amplifier output Motor phase current sense amplifier inverting input Motor phase current sense amplifier non-inverting input Current limit comparator, MOSFET driver fault output, open drain Motor current sense amplifier output Motor current sense amplifier inverting input Motor current sense amplifier non-inverting input Power 0V reference Phase A low-side N-Channel MOSFET driver, active-high Phase B low-side N-Channel MOSFET driver, active-high Phase C low-side N-Channel MOSFET driver, active-high Power 0V reference Phase C high-side N-Channel MOSFET driver, active-high Phase B high-side N-Channel MOSFET driver, active-high Phase A high-side N-Channel MOSFET driver, active-high Phase C high-side MOSFET driver reference, back EMF sense input Phase B high-side MOSFET driver reference, back EMF sense input Phase A high-side MOSFET driver reference, back EMF sense input Phase C high-side MOSFET driver bias Phase B high-side MOSFET driver bias Phase A high-side MOSFET driver bias Analog circuitry and low-side gate drive bias Power 0V reference Buck regulator switch node, external inductor connection Input supply Buck regulator feedback node Internal circuitry bias Charge pump flying capacitor input Charge pump flying capacitor input Voltage and temperature supervisor output, open drain Digital input, phase C low-side control, 47K pulldown Digital input, phase C high-side control, 47K pulldown Digital input, phase B low-side control, 47K pulldown Exposed Pad, Connect to Power 0V reference 2013 Microchip Technology Inc. DS20005228A-page 15 MCP8024 3.2 VDD Connect VDD to the main supply voltage. This voltage must not exceed the maximum operating limits of the device. Connect a bulk capacitor close to this pin for good load step performance and transient protection. The type of capacitor used can be ceramic, tantalum or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency. 3.3 PGND, Exposed Pad (EP) Device ground. The PCB ground traces should be short, wide, and form a STAR pattern to the power source. The Exposed Pad (EP) PCB area should be a copper pour with thermal vias to help transfer heat away from the device. 3.4 +12V +12 volt Low Dropout (LDO) voltage regulator output. The +12V LDO may be used to power external devices such as Hall-effect sensors or amplifiers. The LDO requires an output capacitor for stability. The positive side of the output capacitor should be physically located as close to the +12V pin as is practical. For most applications, 4.7 µF of capacitance will ensure stable operation of the LDO circuit. The type of capacitor used can be ceramic, tantalum or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency. 3.5 +5V +5 volt Low Dropout (LDO) voltage regulator output. The +5V LDO may be used to power external devices such as Hall-effect sensors or amplifiers. The LDO requires an output capacitor for stability. The positive side of the output capacitor should be physically located as close to the +5V pin as is practical. For most applications, 4.7 µF of capacitance will ensure stable operation of the LDO circuit. The type of capacitor used can be ceramic, tantalum or aluminum electrolytic. The low ESR characteristics of the ceramic will yield better noise and PSRR performance at high frequency. 3.6 3.8 CAP1, CAP2 Charge pump flying capacitor inputs. Connect the charge pump capacitor across these two pins. 3.9 CE Chip Enable input used to enable/disable the output driver and on-board functions. When CE is high, all device functions are enabled. When CE is low, the device operates in Reduced mode. The H-Bridge, current amplifiers and 12V LDO are disabled. The buck regulator, 5V LDO, DE2, voltage and temperature sensor functions are not affected. The CE is also used to clear any hardware faults. When a fault occurs, the CE input may be used to clear the fault by setting the pin low and then high again. The fault is cleared by the rising edge of the CE signal if the hardware fault is no longer active. The CE pin has an internal 47K pulldown. 3.10 I_OUT1, I_OUT2, I_OUT3 Current sense amplifier output. May be used with feedback resistors to set the current sense gain. 3.11 ISENSE1, ISENSE2, ISENSE3 +/- Current sense amplifier inverting and non-inverting inputs. Used in conjunction with I_OUTx pins to set current sense gain. 3.12 /ILIMIT_OUT Current limit output signal. The open-drain output goes low when the current sensed by current sense amplifier 1 exceeds the value set by the internal current reference DAC. The DAC has an offset of 0.991V (typical) which represents zero current flow. The open-drain output will also go low while a motor fault is active. 3.13 PWM1H, PWM2H, PWM3H Digital PWM inputs for high-side driver control. Each input has a 47K pulldown to ground. The PWM signals may contain dead-time timing or the system may use the Configuration register 2 to set the dead time. LX Buck regulator switch node external inductor connection. Connect this pin to the external inductor chosen for the buck regulator. 3.7 voltage. Connecting this pin to the +5V LDO output disables the buck regulator. FB 3.14 PWM1L, PWM2L, PWM3L Digital PWM inputs for low-side driver control. Each input has a 47K pulldown to ground. The PWM signals may contain dead-time timing or the system may use the Configuration register 2 to set the dead time. Buck regulator feedback node that is compared with internal 1.25V reference voltage. Connect this pin to a resistor divider that sets the buck regulator output DS20005228A-page 16 2013 Microchip Technology Inc. MCP8024 3.15 LA, LB, LC Low-side N-channel MOSFET drive signal. Connect to the gate of the external MOSFETs. A low-impedance resistor may be used between these pins and the MOSFET gates to limit current and slew rate. 3.16 HA, HB, HC High-side N-channel MOSFET drive signal. Connect to the gate of the external MOSFETs. A low-impedance resistor may be used between these pins and the MOSFET gates to limit current and slew rate. 3.17 PHA, PHB, PHC Phase signals from motor. Provides high-side Nchannel MOSFET driver reference and Back EMF sense input. The phase signals are also used with the bootstrap capacitors to provide high-side gate drive via the VBx inputs. 3.18 VBA, VBB, VBC High-side MOSFET driver bias. Connect these pins between the bootstrap charge pump diode cathode and bootstrap charge pump capacitor. The 12V LDO output is used to provide 12V at the diode anodes. The phase signals are connected to the other side of the bootstrap charge pump capacitors. 3.19 DE2 Open-drain communications node. The DE2 communications is a half-duplex 9600 baud, 8-bit, no parity communications link. The open-drain DE2 pin must be pulled high by an external pull-up resistor. 3.20 HV_IN1, HV_IN2, LV_OUT1,LV_OUT2 Unidirectional digital level translators. Translates digital input signal on the HV_INx pin to a low-level digital output signal on the LV_OUTx pin. The HV_INx pins have internal 30K pullups to VDD that are controlled by Configuration register 0 bit 6. The Configuration register 0 bit 6 is only sampled during CE = 0. The HV_IN1 pin has higher ESD protection than the HV_IN2 pin. The higher ESD protection makes the HV_IN1 pin better suited for connection to external switches. LV_OUT1 and LV_OUT2 are open-drain outputs. An external pull-up resistor to the low-voltage logic supply is required. 2013 Microchip Technology Inc. DS20005228A-page 17 MCP8024 4.0 DETAILED DESCRIPTION 4.1 BIAS GENERATOR The internal bias generator controls three voltage rails. Two fixed-output low-dropout linear regulators, an adjustable buck switch-mode power converter, and an unregulated charge pump are controlled through the bias generator. In addition, the bias generator performs supervisory functions. 4.1.1 CURRENT_REF VIN + - Q1 +12V LOW-DROPOUT LINEAR REGULATOR (LDO) The +12V rail is used for bias of the 3-phase power MOSFET bridge. OUTPUT CONTROL LOGIC VDD-12V LX The regulator is capable of supplying 20mA of external load current. The regulator has a minimum overcurrent limit of 30 mA. The low-dropout regulators require an output capacitor connected from VOUT to GND to stabilize the internal control loop. A minimum of 4.7F ceramic output capacitance is required for the 12V LDO. 4.1.2 + + - BANDGAP REFERENCE - FB +5V LOW-DROPOUT LINEAR REGULATOR (LDO) The +5V LDO is used for bias of an external microcontroller, the internal current sense amplifier and the gate control logic. The +5V LDO is capable of supplying 20mA of external load current. The regulator has a minimum overcurrent limit of 30 mA. If additional external current is required, the buck switch-mode power converter should be utilized. A minimum of 4.7F ceramic output capacitance is required for the 5V LDO. 4.1.3 BUCK SWITCH-MODE POWER CONVERTER (SMPS) The SMPS is a high-efficiency, fixed-frequency, stepdown DC-DC converter. The SMPS provides all the active functions for local DC-DC conversion with fast transient response and accurate regulation. During normal operation of the buck power stage, Q1 is repeatedly switched on and off with the on and off times governed by the control circuit. This switching action causes a train of pulses at the LX node which are filtered by the L/C output filter to produce a DC output voltage, VO. Figure 4-1 depicts the functional block diagram of the SMPS. DS20005228A-page 18 FIGURE 4-1: Diagram. SMPS Functional Block The SMPS is designed to operate in Discontinuous Conduction Mode (DCM) with Voltage mode control and current limit protection. The SMPS is capable of supplying 5V, 150mA to an external load at a fixed switching frequency of 460 kHz with an input voltage of 6V. The output of the SMPS is power limited. Therefore, for a programmed output voltage of 3V, the SMPS will be capable of supplying 250mA to an external load. An external diode is required between the LX pin and ground. The diode will be required to handle the inductor current when the switch is off. The diode is external to the device to reduce substrate currents and power dissipation caused by the switcher. The external diode carries the current during the switch off time, eliminating the current path back through the device. At light loads the SMPS enters Pulse Frequency Modulation (PFM), improving efficiency at the expense of higher output voltage ripple. The PFM circuitry provides a means to disable the SMPS as well. If the SMPS is not utilized in the application, connecting the feedback pin (FB) to an external 2.5V-to-5.0V supply will force the SMPS to a shutdown state. 2013 Microchip Technology Inc. MCP8024 The maximum inductor value for operation in Discontinuous Conduction mode can be determined by the following equation. 4.1.5 EQUATION 4-1: 4.1.5.1 LMAX SIMPLIFIED SUPERVISOR The bias generator incorporates a voltage supervisor and a temperature supervisor. Voltage Supervisor VO VO 1 – -------- T V IN L MAX ---------------------------------------------2 I O CRIT The voltage supervisor protects the device, external power MOSFETs, and the external microcontroller from damage due to overvoltage or undervoltage of the input supply, VDD. Using the LMAX inductor value calculated using Equation 4-1 will ensure Discontinuous Conduction mode operation for output load currents below the critical current level, IO(CRIT). For example, with an output voltage of +5V, a standard inductor value of 4.7H will ensure Discontinuous Conduction mode operation with an input voltage of 6V, a switching frequency of 468 kHz, and a critical load current of 150 mA. In the event of an undervoltage condition, VDD < +5.5V, the motor drivers are switched off. The bias generator, communication port, and the remainder of the motor control unit remain active. The failure state is flagged on the DE2 pin with a status message. In extreme overvoltage conditions, VDD > +32V, all functions are turned off. The output voltage is set by using a resistor divider network. The resistor divider is connected between the inductor output and ground. The divider common point is connected to the FB pin which is then compared to an internal 1.25V reference voltage. The Buck regulator will set a Status bit and send a status message to the host whenever the input switching current exceeds two amperes peak (typical). The bit will be cleared when the peak input switching current drops back below the two ampere (typical) limit. The Buck regulator will set a Status bit and send a status message to the host whenever the output voltage drops below 90% of the rated output voltage. The bit will be cleared when the output voltage returns to 94% of rated value. If the Buck regulator output voltage falls below 80% of rated output voltage, the system will shutdown with a “Brown-out Error”. This will notify the Host of a power failure and subsequent loss of configuration. The Voltage Supervisor is designed to shutdown the buck regulator when VDD rises above OVLOSTOP. When shutting down the buck regulator is not desirable, the user should add a voltage suppression device to the VDD input in order to prevent VDD from rising above OVLOSTOP. The Voltage Supervisor is also designed to shutdown the buck regulator when VDD falls below UVLOSTOP. 4.1.4 CHARGE PUMP An unregulated charge pump is utilized to boost the input to the +12V LDO during low-input conditions. When the input bias to the device (VDD) drops below CPSTART, the charge pump is activated. When activated, 2 x VDD is presented to the input of the +12V LDO, which maintains a minimum +10V at its output. The typical charge pump flying capacitor is a 0.1 µF to 1.0 µF ceramic capacitor. 2013 Microchip Technology Inc. 4.1.5.2 Temperature Supervisor An integrated temperature sensor self protects the device circuitry. If the temperature rises above the overtemperature shutdown threshold, all functions are turned off. Active operation resumes when the temperature has cooled down below a set hysteresis value and the fault has been cleared by toggling CE. It is desirable to signal the microcontroller with a warning message before the overtemperature threshold is reached. The microcontroller should take appropriate actions to reduce the temperature rise. The method to signal the microcontroller is through the DE2 pin. 4.2 MOTOR CONTROL UNIT The motor control unit is comprised of the following: • External Drive for a 3-Phase Bridge with NMOS/ NMOS MOSFET pairs • Three Motor Current Sense Amplifiers • Motor Overcurrent Comparator 4.2.1 MOTOR CURRENT SENSE CIRCUITRY The internal motor current sense circuitry consists of an operational amplifier and comparator. The amplifier output is presented to the inverting comparator input and as an output to the microcontroller. The noninverting comparator input is connected to an internally programmable 8-bit DAC. A selectable motor current limit threshold may be set with a SET_ILIMIT message from the host to the MCP8024 via the DE2 communications link. The 8-bit DAC is powered by the 5V supply. The DAC output voltage range is 0.991V to 4.503V. The DAC has a bit value of (4.503V - 0.991V) / (2^8 - 1) = 13.77 mV/bit. A DAC input of 00H yields a DAC output voltage of 0.991V. The default power-up DAC value is 40H (1.872V). The DAC uses a 100 kHz filter. Input code to output voltage delay is DS20005228A-page 19 MCP8024 approximately five time constants ~= 50 µs. The desired current sense gain is established with an external resistor network. Note: The motor current limit comparator output is internally ‘OR’d with the DRIVER FAULT output of the driver logic block. The microcontroller should monitor the comparator output and take appropriate actions. The motor current limit comparator circuitry does not disable the motor drivers when an overcurrent situation occurs. Only one current limit comparator is provided. The MCP8024 provides three current sense amplifiers which can be used for implementation of advanced control algorithms such as Field Oriented Control (FOC). The comparator output may be employed as a current limit. Alternatively, the current sense output can be employed in a chop-chop PWM speed loop for any situations where the motor is being accelerated, either positively or negatively. An analog chop-chop speed loop can be implemented by hysteretic control or fixed off-time of the motor current. This makes for a very robust controller as the motor current is always in instantaneous control. A sense resistor in series with the bridge ground return provides a current signal for both feedback and current limiting. This resistor should be non-inductive to minimize ringing from high di/dt. Any inductance in the power circuit represents potential problems in the form of additional voltage stress and ringing, as well as increasing switching times. While impractical to eliminate, careful layout and bypassing will minimize these effects. The output stage should be as compact as heat sinking will allow, with wide, short traces carrying all pulsed currents. Each half-bridge should be separately bypassed with a low ESR/ESL capacitor, decoupling it from the rest of the circuit. Some layouts will allow the input filter capacitor to be split into three smaller values, and serve double duty as the halfbridge bypass capacitors. Note: With a chop-chop control, motor current always flows through the sense resistor. When the PWM is off, however, the flyback diodes, or synchronous rectifiers, conduct, causing the current to reverse polarity through the sense resistor. The current sense resistor is chosen to establish the peak current limit threshold, which is typically set 20% higher than the maximum current command level to provide overcurrent protection during abnormal conditions. Under normal circumstances with a properly compensated current loop, peak current limit will not be exercised. DS20005228A-page 20 4.2.2 MOTOR CONTROL The commutation loop of a BLDC motor control is a Phase-Locked Loop (PLL) which locks to the rotor’s position. Note that this inner loop does not attempt to modify the position of the rotor, but modifies the commutation times to match whatever position the rotor has. An outer speed loop changes the rotor velocity, and the commutation loop locks to the rotor’s position to commutate the phases at the correct times. 4.2.2.1 Sensorless Motor Control Many control algorithms can be implemented with the MCP8024 in conjunction with a microcontroller. The following discussion provides a starting point for implementing the MCP8024 in a sensorless control application of a 3-phase motor. The motor is driven by energizing two windings at a time and sequencing the windings in a six step per electrical revolution method. This method leaves one winding unenergized at all times, and the voltage on that unenergized (Back EMF) winding can be monitored to determine the rotor position. 4.2.2.2 Start-Up Sequence When the motor being driven is at rest, the back EMF is equal to zero. The motor needs to be rotating for the back EMF sensor to lock onto the rotor position and commutate the motor. The recommended start-up sequence to bring the rotor from rest up to a speed fast enough to allow back EMF sensing is comprised of three modes: Lock or Align mode, Ramp mode, and Run mode. Refer to the commutation state machine in Table 4-1. The order in which the microcontroller steps through the commutation state machine determines the direction the motor rotates. 4.2.2.3 Disabled Mode (CE = 0) When the driver is disabled (CE = 0), all of the drivers are turned off. 4.2.2.4 Lock Mode Before the motor can be started, the rotor must be in a known position. In Lock mode, the microcontroller drives phase B low and phases A and C high. This aligns the rotor 30 electrical degrees before the center of the first commutation state. Lock mode must last long enough to allow the motor and its load to settle into this position. 4.2.2.5 Ramp Mode At the end of Lock mode, Ramp mode is entered. In Ramp mode, the microcontroller steps through the commutation state machine, increasing linearly, until a minimum speed is reached. Ramp mode is an openloop commutation. No knowledge of the rotor position is used. 2013 Microchip Technology Inc. MCP8024 4.2.2.6 Run Mode At the end of the Ramp mode, Run mode is entered. In Run mode, the back EMF sensor is enabled and commutation is now under the control of the phase-locked loop. Motor speed can be regulated by an outer speed control loop. TABLE 4-1: COMMUTATION STATE MACHINE OUTPUTS STATE HA CE = 0 LOCK 1 2 3 4 5 6 4.2.2.7 OFF ON ON OFF OFF OFF OFF ON HB OFF OFF OFF ON ON OFF OFF OFF HC OFF ON OFF OFF OFF ON ON OFF PWM Speed Control The inner commutation loop is a phase-locked loop, which locks to the rotor’s position. This inner loop does not attempt to modify the position of the rotor, but modifies the commutation times to match whatever position the rotor has. The outer speed loop changes the rotor velocity and the inner commutation loop locks to the rotor’s position to commutate the phase at the correct times. The outer speed loop pulse width modulates (PWMs) the motor drive inverter to produce the desired wave shape and voltage at the motor. The inductance of the motor then integrates this PWM pattern to produce the desired average current, thus controlling the desired torque and speed of the motor. For a trapezoidal BLDC motor drive with six-step commutation, the PWM is used to generate the average voltage to produce the desired motor current and, hence, the motor speed. There are two basic methods to PWM the inverter switches. The first method returns the reactive energy in the motor inductance to the source by reversing the voltage on the motor winding during the current decay period. This method is referred to as fast decay or chop-chop. The second method circulates the reactive current in the motor with minimal voltage applied to the inductance. This method is referred to as slow decay or chop-coast. The preferred control method employs a chop-chop PWM for any situations where the motor is being accelerated, either positively or negatively. For improved efficiency, chop-coast PWM is employed during steady-state conditions. The chop-chop speed loop is implemented by hysteretic control, fixed offtime control, or average Current mode control of the motor current. This makes for a very robust controller 2013 Microchip Technology Inc. LA OFF OFF OFF OFF ON ON OFF OFF LB OFF ON OFF OFF OFF OFF ON ON LC OFF OFF ON ON OFF OFF OFF OFF BEMF SAMPLE N/A N/A Phase B Phase A Phase C Phase B Phase A Phase C as the motor current is always in instantaneous control. The motor speed presented to the chop-chop loop is reduced by approximately 9%. A fixed-frequency PWM that only modulates the high-side switches implements the chop-coast loop. The chop-coast loop is presented with the full motor speed, so if it is able to control the speed, the chop-chop loop will never be satisfied and will remain saturated. The chop-chop remains able to assume full control if the motor torque is exceeded, either through a load change or a change in speed that produces acceleration torque. The chopcoast loop will remain saturated, with the chop-chop loop in full control, during start-up and acceleration to full speed. The bandwidth of the chop-coast loop is set to be slower than the chop-chop loop so that any transients will be handled by the chop-chop loop and the chop-coast loop will only be active in steady-state operation. 4.2.3 EXTERNAL DRIVE FOR A 3-PHASE BRIDGE WITH NMOS/NMOS MOSFET PAIRS Each motor phase is driven with external NMOS/ NMOS MOSFET pairs. These are controlled by a lowside and a high-side gate driver. The gate drivers are controlled directly by the digital input pins PWM[1:3]H/ L. A logic High turns the associated gate driver ON, and a logic Low turns the associated gate driver OFF. The PWM[1:3]H/L digital inputs are equipped with internal pull-down resistors. The low-side gate drivers are biased by the +12V LDO output, referenced to ground. The high-side gate drivers are a floating drive biased by a bootstrap capacitor circuit. The bootstrap capacitor is charged by the +12V LDO whenever the accompanying low-side MOSFET is turned on. DS20005228A-page 21 MCP8024 4.2.3.1 External Driver Protection Features Each driver is equipped with Undervoltage Lock Out (UVLO) and short circuit protection features. 4.2.3.1.1 Driver Undervoltage Lock Out (UVLO) At anytime the driver bias voltage is below the Driver Undervoltage Lock Out threshold (DUVLO), the driver will not turn ON when commanded ON. A driver fault will be indicated to the host microcontroller on the ILIMIT_OUT, open-drain output pin and also via a DE2 communications Status 1 message. This is a latched fault. Clearing the fault requires either removal of device power or disabling and re-enabling the device via the device enable input (CE). Bit 3 of the Configuration 0 register is used to enable or disable the Driver Undervoltage Lockout feature. This protection feature prevents the external MOSFETs from being controlled with a gate voltage not suitable to fully enhance the device. 4.2.3.1.2 External MOSFET Short Circuit Current Short circuit protection monitors the voltage across the external MOSFETs during an ON condition. If the voltage rises above a user configurable threshold, all drivers will be turned OFF. A driver fault will be indicated to the host microcontroller on the open-drain ILIMIT_OUT output pin and also via a DE2 communications Status 1 message. This is a latched fault. Clearing the fault requires either removal of device power or disabling and re-enabling the device via the device enable input (CE). This protection feature helps detect internal motor failures such as winding to case shorts. Note: The driver short-circuit protection is dependent on application parameters. A configuration message is provided for a set number of threshold levels. In addition, Driver UVLO and/or short-circuit protection has the option to be disabled. The short-circuit voltage may be set via a DE2 Set_Cfg_0 message. Bits 0 and 1 are used to select the voltage level for the short circuit comparison. If the voltage across the MOSFET drain-source exceeds the selected voltage level, a fault will be triggered. The selectable voltage levels are 250 mV, 500 mV, 750 mV, and 1000 mV. Bit 2 of the Configuration 0 register is used to enable or disable the short-circuit detection. 4.2.3.2 Gate Control Logic The gate control logic provides level shifting of the digital inputs, polarity control, and cross conduction protection. Cross conduction protection is performed in two ways. DS20005228A-page 22 4.2.3.2.1 Cross Conduction Protection First, logic prevents switching ON one power MOSFET while the opposite one in the same half-bridge is already switched ON. If both MOSFETs in the same half-bridge are commanded on simultaneously by the digital inputs, both will be turned OFF. 4.2.3.2.2 Programmable Dead Time Second, the gate control logic employs a breakbefore-make dead-time delay that is programmable. A configuration message is provided to configure the driver dead time. The allowable dead times are 250 ns, 500 ns, 1 µs and 2 µs. 4.2.3.2.3 Programmable Blanking Time A configuration message is provided to configure the driver current limit blanking time. The blanking time allows the system to ignore any current spikes that may occur when switching outputs. The allowable blanking times are 500 ns, 1 µs, 2µs, and 4µs (default). The blanking time will start after the dead time circuitry has timed out. 4.3 CHIP ENABLE (CE) The Chip Enable (CE) pin allows the device to be disabled by external control. When the Chip Enable pin is not active, the following subsystems are disabled: • high side gate drives (HA, HB, HC) • low side gate drives (LA, LB, LC) • 12V LDO • 30K pull-up resistor connected to the level translator is switched out of the circuit to minimize current consumption (configurable). The 5V LDO and Buck Regulator stay enabled. The DE2 communications port remains active but the port may only respond to commands. When CE is inactive, the DE2 port is prevented from initiating communications in order to conserve power. The total current consumption of the device when CE is inactive (device disabled) stays within the “input quiescent current” limits specified in the device characteristics table. 4.4 COMMUNICATION PORTS The communication ports provide a means of communicating to the host system. 4.4.1 DE2 COMMUNICATIONS PORT A half-duplex 9600 baud UART interface is available to communicate with an external host. The port is used to configure the MCP8024 and also for status and fault messages. 2013 Microchip Technology Inc. MCP8024 4.4.2 LEVEL TRANSLATOR The level translator is an interface between the companion microcontrollers logic levels and the input voltage levels from the system. Typically, the input is driven from the Engine Control Unit (ECU). The level translator is a unidirectional translator. Signals on the high-voltage input are translated to low-voltage signals on the low-voltage outputs. The high-voltage HV_INx inputs have a configurable 30K pullup. The pullup is configured via a SET_CFG_0 message. Bit 6 of the register controls the state of the pullup. The bit may only be changed when the CE pin is active. The lowvoltage LV_OUTx outputs are open-drain outputs. Note: The TQFP package has two level translators. The second level translator typically interfaces to an Ignition Key ON/OFF signal. 4.5 4.5.1 4.5.3 PACKET TIMING While no data is being transmitted, a logic ‘1’ must be placed on the open-drain DE2 line by an external pullup resistor. A data packet is composed of one Start bit, which is always a logic ‘0’, followed by eight data bits, and a Stop bit. The Stop bit must always be a logic ‘1’. It takes 10 bits to transmit a byte of data. The device detects the Start bit by detecting the transition from logic 1 to logic 0 (note that while the data line is idle, the logic level is high). Once the Start bit is detected, the next data bit’s “center” can be assured to be 24 ticks minus 2 (worst case synchronizer uncertainty) later. From then on, every next data bit center is 16 clock ticks later. Figure 4-3 illustrates this point. HOST COMMUNICATIONS DE2 COMMUNICATIONS A single-wire, half-duplex, 9600 baud, 8-bit bidirectional communications interface is implemented using the open-drain DE2 pin. The interface consists of eight data bits, one Stop bit, and one Start bit. The implementation of the interface is described in the following sections. A 2K resistor should typically be used between the host transmit pin and the MCP8024 DE2 pin to allow the MCP8024 to drive the DE2 line when the host TX pin is at an idle high level. The DE2 communications is active when CE = 0 with the constraint that the MCP8024 will not initiate any messages. The host processor may initiate messages regardless of the state of the CE pin. The MCP8024 will respond to host commands when the CE pin is low. 4.5.2 PACKET FORMAT Every internal status change will provide a communication to the microcontroller. The interface uses a standard UART baud rate of 9600 bits per second. In the DE2 protocol, the transmitter and the receiver do not share a clock signal. A clock signal does not emanate from one transmitter to the other receiver. Due to this reason the protocol is asynchronous. The protocol uses only one line to communicate, so the transmit/ receive packet must be done in Half-Duplex mode. A new transmit message is allowed only when a complete packet has been transmitted. The Host must listen to the DE2 line in order to check for contentions. In case of contention, the host must release the line and wait for at least three packet-length times before initiating a new transfer. Figure 4-2 illustrates a basic DE2 data packet. 2013 Microchip Technology Inc. DS20005228A-page 23 MCP8024 Message Format DE2 B0 START FIGURE 4-2: B1 B2 B3 B4 B5 B6 B7 STOP DE2 PACKET FORMAT. Detect start bit by sensing transition from logic 1 to logic 0 T = 1/Baud Rate (bit-cell period) T START TSTART B0 B1 B2 B3 B4 B5 B6 B7 STOP TS TS = T/16 (oversampled bit-cell period) Receiver samples the incoming data using x16 baud rate clock TSTART = 1.5T – uncertainty on start (worst case: 2x TS) Detection (worse FIGURE 4-3: 4.5.4 DE2 PACKET TIMING. MESSAGING INTERFACE A command byte will always have the most significant bit 7 (msb) set to ‘1’. Bits 6 and 5 are reserved for future use and should be set to ‘0’. Bits 4:0 are used for commands. That allows for 32 possible commands. 4.5.4.1 Host to MCP8024 Messages sent from the host to the MCP8024 device consist of either one or two eight-bit bytes. The first byte transmitted is the command byte. The second byte transmitted, if required, is the data for the command. 4.5.4.2 MCP8024 to Host A solicited response byte from the MCP8024 device will always echo the command byte with bit 7 set to ‘0’ (Response) and with bit 6 set to ‘1’ for Acknowledged (ACK) or ‘0’ for Not Acknowledged (NACK). The second byte, if required, will be the data for the host command. Any command that causes an error or is not supported will receive a NACK response. The MCP8024 may send unsolicited command messages to the host controller. All messages to the host controller do not require a response from the host controller. DS20005228A-page 24 Sample incoming data at the bit-cell center 4.5.4.3 Messages 4.5.4.3.1 SET_CFG_0 There is a SET_CFG_0 message that is sent by the host to the MCP8024 device to configure the device. The SET_CFG_0 message may be sent to the device at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CFG_0 message. The SET_CFG_0 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 4.5.4.3.2 GET_CFG_0 There is a GET_CFG_0 message that is sent by the host to the MCP8024 device to retrieve the device configuration register. The GET_CFG_0 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 4.5.4.3.3 STATUS_0/1 There is a STATUS_0/1 message that is sent by the host to the MCP8024 device to retrieve the device STATUS register. The STATUS_0/1 message may also be sent to the host by the MCP8024 device to inform the host of status changes. The STATUS_0/1 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 2013 Microchip Technology Inc. MCP8024 The Brown-out Reset – Config Lost bit 4 of status message 1 will be set every time the device restarts due to a brown-out event or a normal start-up. When the bit is set, an unsolicited message will be sent to the host indicating a Reset has taken place and that the configuration data may have been lost. The flag is reset by a “Status 1 Ack” (01000110 (46H)) from the device in response to a Host Status Request command. 4.5.4.3.4 SET_CFG_1 There is a SET_CFG_1 message that is sent by the host to the MCP8024 device to configure the motor current limit reference DAC. The SET_CFG_1 message may be sent to the device at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CFG_1 message. The SET_CFG_1 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 4.5.4.3.5 GET_CFG_1 There is a GET_CFG_1 message that is sent by the host to the MCP8024 device to retrieve the motor current limit reference DAC Configuration register. The GET_CFG_1 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 4.5.4.3.6 SET_CFG_2 There is a SET_CFG_2 message that is sent by the host to the MCP8024 device to configure the driver current limit blanking time. The SET_CFG_2 message may be sent to the device at any time. The host is responsible for making sure the system is in a state that will not be compromised by sending the SET_CFG_2 message. The SET_CFG_2 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 4.5.4.3.7 GET_CFG_2 There is a GET_CFG_2 message that is sent by the host to the MCP8024 device to retrieve the device Configuration register #2. The GET_CFG_2 message format is indicated in Table 4-2. The response is indicated in Table 4-3. 2013 Microchip Technology Inc. DS20005228A-page 25 MCP8024 TABLE 4-2: DE2 COMMUNICATIONS COMMANDS TO MCP8024 FROM HOST COMMAND BYTE BIT SET_CFG_0 1 2 7 6 5 4 3 2 1:0 GET_CFG_0 STATUS_0 STATUS_1 SET_CFG_1 1 1 1 1 2 7:0 SET_CFG_2 1 7:4 3:2 1:0 GET_CFG_2 1 DS20005228A-page 26 DESCRIPTION 10000001 (81H) Set Configuration Register 0 0 Unused (Start-up Default) 0 Disable Disconnect of 30K Level Translator Pullup when CE = 0 (Default) 1 Enable Disconnect of 30K Level Translator Pullup when CE = 0 0 Unused 0 Reserved 0 Enable Undervoltage Lockout (Start-up Default) 1 Disable Undervoltage Lockout 0 Enable External MOSFET Short Circuit Detection (Start-up Default) 1 Disable External MOSFET Short Circuit Detection 00 Set External MOSFET Overcurrent Limit to 0.250V (Start-up Default) 01 Set External MOSFET Overcurrent Limit to 0.500V 10 Set External MOSFET Overcurrent Limit to 0.750V 11 Set External MOSFET Overcurrent Limit to 1.000V 10000010 (82H) 10000101 (85H) 10000110 (86H) 10000011 (83H) GET_CFG_1 1 2 VALUE Get Configuration Register 0 Get Status Register 0 Get Status Register 1 Set Configuration Register 1 DAC Motor Current Limit Reference Voltage 00H - FFH Select DAC Current Reference value. (4.503V - 0.991V)/ 255 = 13.77 mV / bit 00H = 0.991 Volts 40H = 1.872 Volts (40H * 0.1377mV/Bit + 0.991V) (Start-up Default) FFH = 4.503 Volts (FFH * 0.1377mV/Bit + 0.991V) 10000100 (84H) Get Configuration register 1 Get DAC Motor Current Limit reference voltage 10000111 (87H) Set Configuration register 2 00H --00 01 10 11 --00 01 10 11 10001000 (88H) Unused (Start-up Default) Driver Dead Time (For PWMH /PWML inputs) 2 µs (Default) 1 µs 500 ns 250 ns Driver Blanking Time (Ignore Switching Current Spikes) 4 µs (Start-up Default) 2 µs 1 µs 500 ns Get Configuration Register 2 2013 Microchip Technology Inc. MCP8024 TABLE 4-3: MESSAGE DE2 COMMUNICATIONS MESSAGES FROM MCP8024 TO HOST BYTE BIT 1 7:0 2 7:0 1 7:0 2 7:0 SET_CFG_0 1 7:0 STATUS_0 STATUS_1 2 7 6 5 4 3 2 1:0 GET_CFG_0 1 2 7:0 7 6 5 4 VALUE DESCRIPTION 00000101 (05H) 01000101 (45H) 10000101 (85H) 00000000 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 00000110 (06H) 01000110 (46H) 10000110 (86H) 00000000 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000 00000001 (01H) 01000001 (41H) 0 0 Status Register 0 Response Not Acknowledged (Response) Status Register 0 Response Acknowledged (Response) Status Register 0 Command To Host (Unsolicited) Normal Operation Temperature Warning (TJ > 125°C (Default Warning Level)) Over Temperature (TJ > 160°C) Input Undervoltage (VDD < 5.5V) Reserved Input Overvoltage (VDD > 32V) Buck Regulator Overcurrent Buck Regulator Output Undervoltage Warning Buck Regulator Output Undervoltage (< 80%,brown-out error) STATUS Register 1 Response Not Acknowledged (Response) STATUS Register 1 Response Acknowledged (Response) STATUS Register 1 Command To Host (Unsolicited) Normal Operation 5V LDO Overcurrent 12V LDO Overcurrent External MOSFET Undervoltage Lock Out (UVLO) External MOSFET Overcurrent Detection Brown-out Reset – Config Lost (Start-up default = 1) Not Used Not Used Not Used Set Configuration Register 0 Not Acknowledged (Response) Set Configuration Register 0 Acknowledged (Response) Unused (Start-up Default) Disable Disconnection of 30K Level Translator Pullup when CE = 0 (Default) 1 Enable Disconnection of 30K Level Translator Pullup when CE = 0 0 Unused 0 Reserved 0 Undervoltage Lockout Enabled (Default) 1 Undervoltage Lockout Disabled 0 External MOSFET Overcurrent Detection Enabled (Default) 1 External MOSFET Overcurrent Detection Disabled 00 0.250V External MOSFET Overcurrent Limit (Default) 01 0.500V External MOSFET Overcurrent Limit 10 0.750V External MOSFET Overcurrent Limit 11 1.000V External MOSFET Overcurrent Limit 00000010 (02H) Get Configuration Register 0 Response Not Acknowledged (Response) 01000010 (42H) Get Configuration Register 0 Response Acknowledged (Response) 0 Unused (Start-up Default) 0 Disable Disconnection of 30K Level Translator Pullup when CE = 0 (Default) 1 Enable Disconnection of 30K Level Translator Pullup when CE = 0 0 Unused 0 Reserved 2013 Microchip Technology Inc. DS20005228A-page 27 MCP8024 TABLE 4-3: MESSAGE DE2 COMMUNICATIONS MESSAGES FROM MCP8024 TO HOST (CONTINUED) BYTE BIT 3 2 1:0 SET_CFG_1 1 2 GET_CFG_1 1 7:0 7:0 2 7:4 3:2 1:0 GET_CFG_2 1 7:4 3:2 1:0 DS20005228A-page 28 DESCRIPTION Undervoltage Lockout Enabled (Default) Undervoltage Lockout Disabled External MOSFET Overcurrent Detection Enabled (Default) External MOSFET Overcurrent Detection Disabled 0.250V External MOSFET Overcurrent Limit (Default) 0.500V External MOSFET Overcurrent Limit 0.750V External MOSFET Overcurrent Limit 1.000V External MOSFET Overcurrent Limit Set DAC Motor Current Limit Reference Voltage Not Acknowledged (Response) 01000011 (43H) Set DAC Motor Current Limit Reference Voltage Acknowledged (Response) 2 SET_CFG_2 1 2 VALUE 0 1 0 1 00 01 10 11 00000011 (03H) 00H - FFH Current DAC Current Reference value 13.77 mV / bit + 0.991V 00000100 (04H) Get DAC Motor Current Limit Reference Voltage Not Acknowledged 01000100 (44H) 00H - FFH 00000111 (07H) 01000111 (47H) 00H --00 01 10 11 --00 01 10 11 00001000 (08H) 01001000 (48H) 00H --00 01 10 11 --00 01 10 11 (Response) Get DAC Motor Current Limit Reference Voltage Acknowledged (Response) Current DAC Current Reference value 13.77 mV / bit + 0.991V Set Configuration Register 2 Not Acknowledged (Response) Set Configuration Register 2 Acknowledged (Response) Unused (Default) Driver Dead Time (For PWMH /PWML inputs) 2 µs (Default) 1 µs 500 ns 250 ns Driver Blanking Time (Ignore Switching Current Spikes) 4 µs (Default) 2 µs 1 µs 500 ns Get Configuration Register 2 Response Not Acknowledged (Response) Get Configuration Register 2 Response Acknowledged (Response) Unused (Default) Driver Dead Time (For PWMH /PWML inputs) 2 µs (Default) 1 µs 500 ns 250 ns Driver Blanking Time (Ignore Switching Current Spikes) 4 µs (Default) 2 µs 1 µs 500 ns 2013 Microchip Technology Inc. MCP8024 5.0 APPLICATION INFORMATION 5.1.1.3 5.1 Component Calculations VCAP = VDD (1 - e -T/t) 5.1.1 CHARGE PUMP CAPACITORS Transfer Charging Path (Flying Capacitor across CAP1 and CAP2) VCAP = 6V (1 - e -[6.67 µs / ([7.5 + 3.5 + 20 m] * 180 nF)]) VCAP = 5.79V available for transfer 5.1.1.4 Transfer Path (Flying and Output Capacitors) V12P = VDD + VCAP - IOUT * dt / C V12P = 6V + 5.79V - (20 mA * 6.67 µs / 180 nF) V12P = 11.049V Charge FIGURE 5-1: Charge Pump. Let: • • • • • • • • • Iout = 20 mA Fcp = 75 kHz (charge/discharge in one cycle) 50% duty cycle VDD = 6V (worst case) RDSON = 7.5 (RPMOS), 3.5 (RNMOS) Vout = 2 x VDD (ideal) CESR = 20 m (ceramic capacitors) Vdrop = 100 mV (Vout ripple) Tchg= Tdchg = 0.5 * 1/75 kHz = 6.67 µs 5.1.1.1 Flying Capacitor The flying capacitor should be chosen to charge to a minimum of 95% (3 ) of VDD within one half of a switching cycle. 3 * = Tchg 5.1.1.5 Calculate the Flying Capacitor Voltage Drop in One Cycle While Supplying 20 mA dv = Iout * dt / C dv = 20 mA * 6.67 µs / 180 nF dv = 0.741V @ 20 mA The second and subsequent transfer cycles will have a higher voltage available for transfer since the capacitor is not completely depleted with each cycle. VCAP will then be VCAP - dV after the first transfer, plus VDD (VCAP - dV) times the RC constant. This repeats for each subsequent cycle, allowing a larger charge pump capacitor to be used if the system will tolerate several charge transfers before requiring full-output voltage and current. Repeating section 5.1.1.3 for the second cycle (and subsequent by re-calculating for each new value of VCAP after each transfer): VCAP = (VCAP - dV) + (VDD - (VCAP - dV)) (1 - e -T/t) VCAP = (5.79V - 0.741V) + (6V - (5.79V - 0.741V) * (1 - e-[6.67 μs/([7.5Ω + 3.5Ω + 20 mΩ] * 180 nF)]) = Tchg/3 VCAP = 5.049V + 0.951V * 0.96535 RC = Tchg/3 VCAP = 5.967V available for transfer on second cycle C = Tchg/(R * 3) 5.1.1.6 C = 6.67 µs/([7.5 + 3.5 + 0.02] * 3) The maximum charge pump flying capacitor value is 202 nF to maintain a 95% voltage transfer ratio on the first charge pump cycle. Larger capacitor values may be used but they will require more cycles to charge to maximum voltage. The minimum required output capacitor value is 2.65 µF to supply 20 mA for 13.3 µs with a 100 mV drop. A larger output capacitor may be used to cover losses due to capacitor tolerance over temperature, capacitor dielectric and PCB losses. C = 202 nF Choose a 180 nF capacitor. 5.1.1.2 Charge Pump Output Capacitor Solve for the charge pump output capacitance, connected between V12P and ground, that will supply the 20 mA load for one switch cycle. The 12VLDO pin on the MCP8024 is the "V12P" pin referenced in the calculations. C = Iout * dt/dV C = Iout * 13.3 µs/(Vdrop + Iout * CESR) C = 20 mA * 13.3 µs/(0.1V + 20 mA * 20 m) C >= 2.65 µF 2013 Microchip Technology Inc. Charge Pump Results These are approximate calculations. The actual voltages may vary due to incomplete charging or discharging of capacitors per cycle due to load changes. The charge pump calculations assume the charge pump is able to charge up the external boot cap within a few cycles. DS20005228A-page 29 MCP8024 5.1.2 BOOTSTRAP CAPACITOR LMAX 7.05 µH The high-side driver bootstrap capacitor needs to power the high-side driver and gate for 1/3 of the motor electrical period for a 3-phase BLDC motor. Choose an inductor 7.05 µH to ensure Discontinuous Conduction mode. Let: Table 5-1 shows the various maximum inductance values for a worst case input voltage of 6V and various output voltages. • • • • • • • • • • • MOSFET driver current: 300 mA PWM period: 50 µs (20 kHz) to 50 ms (20Hz) Minimum duty cycle: 1% (500 ns to 500 µs) Maximum duty cycle: 99% (49.5 µs to 49.5 ms) Vin = 12V Minimum gate drive voltage: 8V (VGS) Total gate charge: 130 nC (80A MOSFET) Allowable VGS drop (VDROP): 3V (12V - 3V = 9V) Switch RDSON: 100 m Driver bias current: 20 µA (IBIAS) Switching transition time (tSW): 40 ns Solve for the smallest capacitance that can supply: - 130 nC of charge to the MOSFET gate - 1 Megohm Gate-Source resistor current - Driver bias current and switching losses 5.1.3.2 Determine the Peak Switch Current for the Calculated Inductor Ipeak = (Vs - Vo) * D * T/L Ipeak = (6V - 3.3V) * (3.3V/6.0V) * 2.137 µs / 7.05 µH Ipeak = 450 mA 5.1.3.3 Setting the Buck Output Voltage The buck output voltage is set by a resistor voltage divider from the inductor output to ground. The divider center tap is fed back to the MCP8024 FB pin. The FB pin is compared to an internal 1.25V reference voltage. When the FB pin voltage drops below the reference voltage, the Buck duty cycle increases. When the FB pin rises above the reference voltage, the Buck duty cycle decreases. QMOSFET = 130 nC QRESISTOR = [(VGS/R) * TON] QDRIVER = (IBIAS * TON + IDRIVER * tSW) TON = 49.5 ms (99% DC) for worst case. CURRENT_REF VDD + - QRESISTOR = (12V/1 Megohm) * 49.5 ms Q1 QRESISTOR = 594 nC QDRIVER = 20 µA * 49.5 ms + 300 mA * 40 ns QDRIVER = 1.002 µC OUTPUT CONTROL LOGIC LX VDD-12V D1 Sc hottky Sum all of the energy requirements: C = (QMOSFET + QRESISTOR + QDRIVER)/VDROP C = (130 nC + 594 nC + 1.002 µC) / 3V + + - C = 575 nF L1 BANDGAP REFERENCE R1 FB C1 R2 Choose a bootstrap capacitor value that is larger than 575 nF. 5.1.3 5.1.3.1 BUCK SWITCHER Calculate the Buck Inductor for Discontinuous Mode Operation Let: FIGURE 5-2: Typical Buck Application. Start with an R2 value of 10K to 51K to minimize current through the divider. VBUCK = 1.25V * (R1 + R2) / R2 Vin = 6V (worse case) Vout = 3.3V Iout = 225 mA Switching Frequency (FSW): 468 kHz (TSW = 2.137 µs) LMAX Vout * (1 - Vout / Vin) * TSW / (2 * Iout) LMAX 3.3V * (1 - 3.3V/6.0V) * 2.137 µs / (2 * 225 mA) DS20005228A-page 30 2013 Microchip Technology Inc. MCP8024 TABLE 5-1: 5.2 MAX INDUCTANCE FOR BUCK DISCONTINUOUS MODE OPERATION Vin (worst case) Vout Iout Max. Inductance 6 3V 250 mA 7.12 µH 6 3.3V 225 mA 7.05 µH 6 5.0V 150 mA 5.94 µH Device Overvoltage Protection When a motor shaft is rotating and power is removed, the magnetism of the motor components will cause the motor to act like a generator. The current that was flowing into the motor will now flow out of the motor. As the motor magnetic field decays, the generator output will also decay. The voltage across the generator terminals will be proportional to the generator current and circuit impedance of the generator circuit. If the power supply is part of the return path for the current and the power supply is disconnected, then the voltage at the generator terminals will increase until the current flows. This voltage increase must be handled external to the driver. A voltage suppression device must be used to clamp the motor terminal voltage to a level that will not exceed the maximum motor operating voltage. A voltage suppressor should be connected from ground to each motor terminal. The PCB traces must be capable of carrying the motor current with minimum voltage and temperature rise. An additional method is to inactivate the high-side drivers and to activate the low-side drivers. This allows current to flow through the low-side external MOSFETs and prevent the voltage increases at the power supply terminals. 2013 Microchip Technology Inc. DS20005228A-page 31 MCP8024 6.0 ERRATA 6.1 5V and 12V Regulator Overcurrent Messages The MCP8024 may send an 0x86 0x01, 0x86 0x02 or 0x86 0x03 message when accelerating a high-current motor. The messages are overcurrent warnings for the 5V and 12V regulators. The warnings have no effect on the actual regulator operation, they are only indicators of the status of the regulator. The overcurrent warnings are due to the large initial current caused by the acceleration rates of high current motors. The messages may be ignored. DS20005228A-page 32 2013 Microchip Technology Inc. MCP8024 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 40-Lead QFN (5x5x0.85 mm) PIN 1 Example PIN 1 MCP8024 e3 H/MP ^^ YYWWNNN 48-Lead TQFP (7x7) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example MCP8024 H/PT YYWW NNN Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013 Microchip Technology Inc. DS20005228A-page 33 MCP8024 40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N 1 2 NOTE 1 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C C SEATING PLANE 0.10 C A (A3) SIDE VIEW D2 A1 0.08 C 0.10 C A B 0.10 C A B E2 K 2 1 N L e 40X b 0.07 0.05 C A B C Microchip Technology Drawing C04-047-002A Sheet 1 of 2 DS20005228A-page 34 2013 Microchip Technology Inc. MCP8024 40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Notes: Units Dimension Limits Number of Terminals N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 0.15 0.30 0.20 MILLIMETERS NOM 40 0.40 BSC 0.85 0.02 0.20 REF 5.00 BSC 3.70 BSC 5.00 BSC 3.70 BSC 0.20 0.40 - MAX 0.90 0.05 0.25 0.50 - 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-047-002A Sheet 2 of 2 2013 Microchip Technology Inc. DS20005228A-page 35 MCP8024 40-Lead Plastic Quad Flat, No Lead Package (MP) - 5x5 mm Body [QFN] With 3.7x3.7 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 E C2 Y2 Y1 X1 SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E X2 Optional Center Pad Width Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X40) X1 Contact Pad Length (X40) Y1 MIN MILLIMETERS NOM 0.40 BSC MAX 3.80 3.80 5.00 5.00 0.20 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2047-002A DS20005228A-page 36 2013 Microchip Technology Inc. MCP8024 48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D A B NOTE 1 E1 E A A E1/2 E1/4 N 48X TIPS 0.20 C A-B D 12 4X 0.20 H A-B D D1/4 TOP VIEW A SEATING PLANE A2 H 0.10 C C 0.08 C SIDE VIEW A1 D2 4X 0.20 H A-B D 12 4X N 0.20 E2 e 48x b 0.08 e/2 C A-B D TOP VIEW Microchip Technology Drawing C04-183A Sheet 1 of 2 2013 Microchip Technology Inc. DS20005228A-page 37 MCP8024 48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D H c E L T (L1) SECTION A-A Units Dimension Limits Number of Leads N e Lead Pitch Overall Height A Standoff A1 Molded Package Thickness A2 L Foot Length Footprint L1 I Foot Angle Overall Width E Overall Length D Molded Package Width E1 Molded Package Length D1 Exposed Pad Width E2 Exposed Pad Length D2 c Lead Thickness b Lead Width D Mold Draft Angle Top E Mold Draft Angle Bottom MIN 0.05 0.95 0.45 0° 0.09 0.17 11° 11° MILLIMETERS NOM 48 0.50 BSC 1.00 0.60 1.00 REF 3.5° 9.00 BSC 9.00 BSC 7.00 BSC 7.00 BSC 3.50 BSC 3.50 BSC 0.22 12° 12° MAX 1.20 0.15 1.05 0.75 7° 0.16 0.27 13° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-183A Sheet 2 of 2 DS20005228A-page 38 2013 Microchip Technology Inc. MCP8024 48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP] With Thermal Tab Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 E C2 Y2 Y1 X1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Tab Width X2 Optional Center Tab Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X48) X1 Contact Pad Length (X48) Y1 MIN MILLIMETERS NOM 0.50 BSC 3.50 3.50 8.40 8.40 MAX 0.30 1.50 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2183A 2013 Microchip Technology Inc. DS20005228A-page 39 MCP8024 NOTES: DS20005228A-page 40 2013 Microchip Technology Inc. MCP8024 APPENDIX A: REVISION HISTORY Revision A (September 2013) • Original Release of this Document. 2013 Microchip Technology Inc. DS20005228A-page 41 MCP8024 NOTES: DS20005228A-page 42 2013 Microchip Technology Inc. MCP8024 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Device Temperature Range Package Examples: Device: MCP8024: 3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module MCP8024T: 3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module (Tape and Reel) Temperature Range: H Package: MP = Plastic Quad Flat, No Lead Package with Exposed Pad - 5x5 mm body, 40-lead PT = Plastic Thin Quad Flatpack with Exposed Pad 7x7 mm body, 48-lead, Thermally Enhanced (EP) = a) MCP8024-H/MP: High Temperature, 40LD 5x5 QFN package b) MCP8024T-H/PT: Tape and Reel, High Temperature, 48LD TQFP-EP package -40°C to +150°C (High) 2013 Microchip Technology Inc. DS20005228A-page 43 MCP8024 NOTES: DS20005228A-page 44 2013 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62077-502-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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