SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+™ Family • Pinout Optimizes DDR2 DIMM PCB Layout • Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer • Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line 2 • • • • • • Supports SSTL_18 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the Control and RESET Inputs Checks Parity on DIMM-Independent Data Inputs Able to Cascade with a Second SN74SSTUB32866 Supports Industrial Temperature Range (-40°C to 85°C) DESCRIPTION This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output. The SN74SSTUB32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2–D3, D5–D6, D8–D25 when C0 = 0 and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state. When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated. When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTUB32866. The QERR output of the first SN74SSTUB32866 is left floating, and the valid error information is latched on the QERR output of the second SN74SSTUB32866. ORDERING INFORMATION TA -40°C to 85°C (1) PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING LFBGA–ZKE Tape and reel SN74SSTUB32866ZKER SB866 LFBGA–ZWL Tape and reel SN74SSTUB32866ZWLR SB866 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity-check computation. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTUB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level. The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and gates the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle after DCS and CSR go high), the device gates the QERR output from changing states. If LPS1 is low, the QERR output functions normally. The RESET input has priority over the DCS and CSR control and, when driven low, forces the Qn and PPO outputs low and forces the QERR output high. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input should be pulled up to VCC through a pullup resistor. The two VREF pins (A3 and T3) are connected together internally by approximately 150Ω. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor. 2 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 PACKAGE Terminal Assignments for 1:1 Register-A (C0 = 0, C1 = 0) 1 2 3 4 5 6 A D1 (DCKE) PPO VREF VCC Q1 (QCKE) DNU B D2 D15 GND GND Q2 Q15 C D3 D16 VCC VCC Q3 Q16 QERR GND GND Q4 (QODT) DNU D D4 (DODT) E D5 D17 VCC VCC Q5 Q17 F D6 D18 GND GND Q6 Q18 G PAR_IN RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7 (QCS) DNU J CLK CSR VCC VCC NC NC K D8 D19 GND GND Q8 Q19 L D9 D20 VCC VCC Q9 Q20 M D10 D21 GND GND Q10 Q21 N D11 D22 VCC VCC Q11 Q22 P D12 D23 GND GND Q12 Q23 R D13 D24 VCC VCC Q13 Q24 T D14 D25 VREF VCC Q14 Q25 Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU - Do not use NC - No internal connection Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 3 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0 4 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Parity Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0 Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 5 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 PACKAGE (TOP VIEW) 1 2 3 4 5 6 A D1 (DCKE) PPO VREF VCC Q1A (QCKEA) Q1B (QCKEB) B D2 DNU GND GND Q2A Q2B C D3 DNU VCC VCC Q3A Q3B QERR GND GND Q4A (QODTA) Q4B(QODTB) D D4 (DODT) E D5 DNU VCC VCC Q5A Q5B F D6 DNU GND GND Q6A Q6B G PAR_IN RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) J CLK CSR VCC VCC NC NC K D8 DNU GND GND Q8A Q8B L D9 DNU VCC VCC Q9A Q9B M D10 DNU GND GND Q10A Q10B N D11 DNU VCC VCC Q11A Q11B P D12 DNU GND GND Q12A Q12B R D13 DNU VCC VCC Q13A Q13B T D14 DNU VREF VCC Q14A Q14B Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU - Do not use NC - No internal connection 6 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Logic Diagram for 1:2 Register-A Configuration (Positive Logic); C0 = 0, C1 = 1 Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 7 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Parity Logic Diagram for 1:2 Register-A Configuration (Positive Logic); C0 = 0, C1 = 1 8 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 PACKAGE (TOP VIEW) Terminal Assignments for 1:2 Register-B (C0 = 1, C1 = 1) 1 2 3 4 5 6 A D1 PPO VREF VCC Q1A Q1B B D2 DNU GND GND Q2A Q2B C D3 DNU VCC VCC Q3A Q3B D D4 QERR GND GND Q4A Q4B E D5 DNU VCC VCC Q5A Q5B F D6 DNU GND GND Q6A Q6B G PAR_IN RESET VCC VCC C1 C0 H CLK D7 (DCS) GND GND Q7A (QCSA) Q7B (QCSB) J CLK CSR VCC VCC NC NC K D8 DNU GND GND Q8A Q8B L D9 DNU VCC VCC Q9A Q9B M D10 DNU GND GND Q10A Q10B N D11 (DODT) DNU VCC VCC P D12 DNU GND GND Q12A Q12B R D13 DNU VCC VCC Q13A Q13B DNU VREF VCC T D14 (DCKE) Q11A (QODTA) Q11B (QODTB) Q14A (QCKEA) Q14B (QCKEB) Each pin name in parentheses indicates the DDR2 DIMM signal name. DNU - Do not use NC - No internal connection Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 9 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Logic Diagram for 1:2 Register-B Configuration C0 = 1, C1 = 1 10 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Parity Logic Diagram for 1:2 Register-B Configuration (Positive Logic); C0 = 1, C1 = 1 Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 11 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 TERMINAL FUNCTIONS TERMINAL NAME ELECTRICAL CHARACTERISTICS DESCRIPTION GND Ground Ground input VCC Power-supply voltage 1.8 V nominal VREF Input reference voltage 0.9 V nominal CLK Positive master clock input Differential input CLK Negative master clock input Differential input C0, C1 Configuration control input. Register A or Register B and 1:1 mode or 1:2 mode select. LVCMOS inputs RESET Asynchronous reset input. Resets registers and disables VREF, data, and clock differential-input receivers. When RESET is low, all Q outputs are forced low and the QERR output is forced high. LVCMOS input D1-D25 Data input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. SSTL_18 inputs CSR, DCS Chip select inputs. Disables D1–D25 (1) outputs switching when both inputs are high SSTL_18 inputs DODT The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 input DCKE The outputs of this register bit will not be suspended by the DCS and CSR control. SSTL_18 input PAR_IN Parity input. Arrives one clock cycle after the corresponding data input. Pulldown resistor of typical 150kΩ to GND. SSTL_18 input pulldown Q1–Q25 (2) Data outputs that are suspended by the DCS and CSR control. 1.8 V CMOS outputs PPO Partial parity out. Indicates odd parity of inputs D1–D25. (1) 1.8 V CMOS output QCS Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QODT Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QCKE Data output that will not be suspended by the DCS and CSR control 1.8 V CMOS output QERR Output error bit. Timing is determined by the device mode. Open-drain output NC No internal connection DNU Do not use. Inputs are in standby-equivalent mode, and outputs are driven low. (1) (2) Data inputs = D2, D3, D5, D6, D8-D25 when C0 = 0 and C1 = 0 Data inputs = D2, D3, D5, D6, D8-D14 when C0 = 0 and C1 = 1 Data inputs = D1-D6, D8-D10, D12, D13 when C0 = 1 and C1 = 1.D Data outputs = Q2, Q3, Q5, Q6, Q8-Q25 when C0 = 0 and C1 = 0 Data outputs = Q2, Q3, Q5, Q6, Q8-Q14 when C0 = 0 and C1 = 1 Data outputs = Q1-Q6, Q8-Q10, Q12, Q13 when C0 = 1 and C1 = 1. FUNCTION TABLE INPUTS OUTPUTS RESET DCS CSR CLK CLK H L X ↑ ↓ L L H L X ↑ ↓ H H H X L ↑ ↓ L L H X L ↑ ↓ H H H H H ↑ ↓ X Q0 H X X L or H L or H X Q0 X or Floating X or Floating X or Floating L L X or Floating X or Floating Dn Qn FUNCTION TABLE INPUTS 12 OUTPUTS RESET CLK CLK H ↑ ↓ H H ↑ ↓ L L H L orH L orH X Q0 L X or Floating X or Floating X or Floating L Submit Documentation Feedback DCKE, DCS, DODT QCKE, QCS, QODT H Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 PARITY AND STANDBY FUNCTION INPUTS OUTPUTS RESET CLK CLK DCS CSR Σ OF INPUTS = H D1–D25 (1) PAR_IN (2) H ↑ ↓ L X Even L L H H ↑ ↓ L X Odd L H L H ↑ ↓ L X Even H H L H ↑ ↓ L X Odd H L H H ↑ ↓ H L Even L L H H ↑ ↓ H L Odd L H L H ↑ ↓ H L Even H H L H ↑ ↓ H L Odd H L H H ↑ ↓ H H X X PPO0 QERR 0 H L or H L or H X X X X PPO0 QERR 0 L X or Floating X or Floating X or Floating X or Floating X X or Floating L H (1) (2) (3) PPO QERR (3) Data inputs = D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0 Data inputs = D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1 Data inputs = D1-D6, D8-D10, D12, D13 when C0 = 1 and C1 = 1 PAR_IN arrives one clock cycle (C0 = 0) or two clock cycles (C0 = 1) after the data to which it applies. This transition assumes that QERR is high at the crossing of CLK going high and CLK going low. If QERR goes low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity duration or until RESET is driven low. PARITY ERROR DETECT IN LOW-POWER MODE (1) INPUT-DATA ERROR OCCURRENCE (2) (1) (2) (3) 1:1 MODE (C0 = 0, C1 = 0) 1:2 REGISTER-A MODE (C0 = 0, C1 = 1) 1:2 REGISTER-B MODE (C0 = 1, C1 = 1) CASCADED MODE (Registers A and B) PPO DURATION (3) QERR DURATION(3) PPO DURATION(3) QERR DURATION(3) PPO DURATION(3) QERR DURATION(3) PPO DURATION(3) QERR DURATION(3) n–4 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles n–3 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles n–2 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles 1 Cycle 2 Cycles n–1 LPM + 2 Cycles LPM + 2 Cycles LPM + 1 Cycle LPM + 1 Cycle LPM + 2 Cycles LPM + 2 Cycles LPM + 2 Cycles LPM + 2 Cycles n Not detected Not detected Not detected Not detected Not detected Not detected Not detected Not detected If a parity error occurs before the device enters the low-power mode (LPM), the behavior of PPO and QERR is dependent on the mode of the device and the position of the parity error occurrence. This table illustrates the low-power-mode effect on parity detect. The low-power mode is activated on the n clock cycle when DCS and CSR go high. The clock-edge position of a one cycle data-input error relative to the clock-edge (n) which initiates LPM at the DCS and CSR inputs. If an error occurs, then QERR output may be driven low and the PPO output driven high. These columns show the clock duration for which the PPO signal will be high. Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 13 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.5 to 2.5 V (3) -0.5 to VCC + 0.5 V (2) (3) VCC Supply voltage range VI Input voltage range (2) VO Output voltage range –0.5 to VCC + 0.5 V IIK Input clamp current, (VI < 0 or VI > VCC) ±50 mA IOK Output clamp current, (VO < 0 or VO > VCC) ±50 mA IO Continuous output current (VO = 0 to VCC) ±50 mA ICC Continuous current through each VCC or GND ±100 mA RθJA Thermal impedance, junction-to-ambient (4) RθJC Thermal resistance, junction-to-case (4) Tstg Storage temperature range (1) (2) (3) (4) No airflow 39.8 Airflow 150 ft/min 34.1 Airflow 250 ft/min 33.6 Airflow 500 ft/min 32.5 No airflow 14.5 K/W °C –65 to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) MIN NOM Supply voltage VREF Reference voltage VTT Termination voltage VI Input voltage VIH AC high-level input voltage Data inputs, CSR, PAR_IN VIL AC low-level input voltage Data inputs, CSR, PAR_IN VIH DC high-level input voltage Data inputs, CSR, PAR_IN VIL DC low-level input voltage Data inputs, CSR, PAR_IN VIH High-level input voltage RESET, Cn VIL Low-level input voltage RESET, Cn VICR Common-mode input voltage range CLK, CLK 0.675 VI(PP) Peak-to-peak input voltage CLK, CLK 600 IOH High-level output current Q outputs, PPO –8 Q outputs, PPO 8 IOL Low-level output current TA Operating free-air temperature (1) 14 1.7 MAX VCC UNIT 1.9 V 0.49 × VCC 0.5 × VCC 0.51 × VCC V VREF–40 mV VREF VREF + 40 mV V VCC V 0 VREF + 250 mV V VREF–250 mV VREF + 125 mV V VREF–125 mV 0.65 × VCC 1.125 V V mV 30 -40 V V 0.35 × VCC QERR output V 85 mA mA °C The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. See the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH Q outputs, PPO Q outputs, PPO VOL QERR output PAR_IN II IOZ ICC ICCD IOL = 100 µA TYP (1) MAX VCC–0.2 UNIT V 1.3 1.7V to 1.9V 0.2 1.7V 0.4 IOL = 25 mA 1.7V 0.5 1.9V 25 VI = GND V -5 VI = VCC VO = VCC or GND RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle Chip-select-enabled low-power active mode – 1:2 configuration MIN IOL = 6 mA Static standby Chip-select-enabled ICCDLP low-power active mode 1:1 configuration (1) (2) 1.7V QERR output Chip-select-enabled low-power active mode – clock only 1.7V to 1.9V IOH = –6 mA VI = VCC or GND Dynamic operating – per each data input, 1:1 configuration VCC IOH = –100 µA All other inputs (2) Dynamic operating – per each data input, 1:2 configuration CI TEST CONDITIONS RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle 1.9V IO = 0 1.9V Data inputs, CSR, PAR_IN VI = VREF ± 250 mV CLK, CLK VICR = 0.9 V, VI(PP) = 600 mV RESET VI = VCC or GND ±10 µA 200 µA 40 mA µA/MHz 45 IO = 0 1.8V 43 µA clock MHz/ D input 60 RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, one data input switching at one-half clock frequency, 50% duty cycle µA ±5 µA/MHz 45 IO = 0 1.8V 2 µA clock MHz/ D input 3 2.5 1.8V 3 2 3.5 3 pF 4 All typical values are at VCC = 1.8 V, TA = 25°C. Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open. Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 15 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 and (1) VCC = 1.8 V ± 0.1 V MIN MAX fclock Clock frequency tw Pulse duration, CLK, CLK high or low tact Differential inputs active time (2) 10 ns tinact Differential inputs inactive time (3) 15 ns tsu Setup time th (1) (2) (3) Hold time 410 UNIT 1 DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high 600 DCS before CLK↑, CLK↓, CSR low 500 DODT, DCKE, and Data before CLK↑, CLK↓ 500 PAR_IN before CLK↑, CLK↓ 500 DCS, DODT, DCKE, and Data after CLK↑, CLK↓ 400 PAR_IN after CLK↑, CLK↓ 400 MHz ns ps ps All inputs slew rate is 1 V/ns ± 20%. VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high. VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 1.8 V ± 0.1 V MIN MAX fmax See Figure 2 tpdm Production test, See Figure 1 CLK and CLK Q 0.4 0.8 ns tpd See Figure 5 CLK and CLK PPO 0.6 1.6 ns 1.2 2.4 1 2.0 tPLH See Figure 4 tPHL tRPHL (1) See Figure 2 tRPHL See Figure 5 tRPLH See Figure 5 (1) 410 UNIT CLK and CLK RESET RESET QERR MHz Q 3 PPO 3 QERR 3 ns ns ns Includes 350-ps test-load transmission-line delay. OUTPUT SLEW RATES over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) (1) 16 PARAMETER FROM TO dV/dt_r 20% dV/dt_f 80% dV/dt_Δ (1) 20% or 80% 80% or 20% VCC = 1.8 V ± 0.1 V UNIT MIN MAX 80% 1 4 V/ns 20% 1 4 V/ns 1 V/ns Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 PARAMETER MEASUREMENT INFORMATION VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 Figure 1. Output Load For Production Test PROPAGATION DELAY (Design Goal as per JEDEC Specification) (1) PARAMETER FROM (INPUT) TO (OUTPUT) tpdm (1) CLK and CLK Q tpdmss (1) CLK and CLK Q VCC = 1.8 V ± 0.1 V UNIT MIN MAX 1.1 1.5 ns 1.6 ns Includes 350 psi test-load transmission delay line Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 17 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Figure 2. Data Output Load Circuit and Voltage Waveforms 18 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Figure 3. Data Output Slew-Rate Measurement Information Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 19 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Figure 4. Error Output Load Circuit and Voltage Waveforms 20 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Figure 5. Partial-Parity-Out Load Circuit and Voltage Waveforms Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 21 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 APPLICATION INFORMATION The typical values below are for standard raw cards. Test equipment used was the JEDEC register validation board using pattern 0x43, 0x4F, and 0x5A. Table 1. Raw Card Values RAW CARD (1) (2) (1) (2) tpdmss OVERSHOOT MIN MAX A/F 1.2 ns 1.6 ns 140 mV B/G 1.3 ns 2.0 ns 430 mV C/H 1.3 ns 2.0 ns 430 mV All values are valid under nominal conditions and minimum/maximum of typical signals on one typical DIMM. Measurements include all jitter and ISI effects. SN74SSTUB32866 Used as a Single Device in the 1:1 Register Configuration; C0 = 0, C1 = 0 22 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for SN74SSTUB32866 Used as a Single Device; C0 = 0, C1 = 0 (RESET Switches From L to H) Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 23 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for SN74SSTUB32866 Used as a Single Device; C0 = 0, C1 = 0 (RESET = H) 24 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for SN74SSTUB32866 Used as a Single Device; C0 = 0, C1 = 0 (RESET Switches From = H to L) Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 25 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 SN74SSTUB32866 Used in Pair in the 1:2 Register Configuration 26 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for the First SN74SSTUB32866 (1:2 Register-A Configuration) Device Used in Pair; C0 = 0, C1 = 1 (RESET Switches From L to H) Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 27 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for the First SN74SSTUB32866 (1:2 Register-A Configuration) Device Used in Pair; C0 = 0, C1 = 1 (RESET = H) 28 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for the First SN74SSTUB32866 (1:2 Register-A Configuration) Device Used in Pair; C0 = 0, C1 = 1 (RESET = Switches From H to L) Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 29 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for the Second SN74SSTUB32866 (1:2 Register-B Configuration) Device Used in Pair; C0 = 1, C1 = 1 (RESET = Switches From L to H) 30 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for the Second SN74SSTUB32866 (1:2 Register-B Configuration) Device Used in Pair; C0 = 1, C1 = 1 (RESET = H) Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 Submit Documentation Feedback 31 SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 Timing Diagram for the Second SN74SSTUB32866 (1:2 Register-B Configuration) Device Used in Pair; C0 = 1, C1 = 1 (RESET = Switches From H to L) 32 Submit Documentation Feedback Copyright © 2006–2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTUB32866 PACKAGE OPTION ADDENDUM www.ti.com 9-Feb-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74SSTUB32866ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR SN74SSTUB32866ZWLR ACTIVE BGA ZWL 96 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74SSTUB32866ZWLR Package Package Pins Type Drawing BGA ZWL 96 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 5.7 B0 (mm) K0 (mm) P1 (mm) 13.7 2.0 8.0 W Pin1 (mm) Quadrant 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 3-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74SSTUB32866ZWLR BGA ZWL 96 1000 333.2 345.9 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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