Supervisor, WDT and Reset Generation
with ProcessorPM
July 2009
Reference Design RD1056
Introduction
The ProcessorPM™ (ispPAC-POWR605) device is shipped from the factory preprogrammed with a design that
provides three functions: voltage supervision, watchdog timer, and reset generator. ProcessorPM is provided preprogrammed so that designers can take advantage of a fully functioning Power Manager design similar to that of a
factory set off-the-shelf reset or supervisor IC.
This document describes in detail the design that is preprogrammed at the factory. This design is also included in the
Examples folder of PAC-Designer® for review or modification by users (file name = POWR605-4-factory-config.pac).
While the ProcessorPM comes from the factory preprogrammed it can be reprogrammed with a slight modification to
this design or a completely new design just like any other Power Manager device from Lattice Semiconductor Corporation.
ProcessorPM provides six programmable threshold comparators (accuracy +/-0.7%) with individual glitch filters to
monitor up to six supply rails. Three comparators are configured for standard power supplies: 3.3V, 2.5V, and 1.8V.
The three remaining comparators are configured to 0.699V so they can be configured using external resistor dividers. The comparator outputs are connected to the 16-macrocell, ruggedized on-chip PLD for voltage supervision
and reset generation using simple logic equations. The four built-in timers are used to provide input debounce,
reset pulse stretching, and watchdog delays. An I/O pin is used to enable or disable a 200ms stretch on the
Reset_CPU output. And two I/O pins are used to digitally select the watchdog timer delay period from 500ms, 2s,
10s, and 1 minute. All device settings are stored using on-chip non-volatile EEPROM that is programmed via a
JTAG interface.
Features
• Six supply monitors
– 3.3V (-5%) supply rail monitor
– 2.5V (-5%) supply rail monitor
– 1.8V (-5%) supply rail monitor
– Three user-selectable voltage monitors
• Watchdog timer with selectable settings of 500ms, 2sec, 10sec, and 1min
• Reset generator with optional 200ms pulse-stretch
• De-bounced manual reset input
• Watchdog timer trigger input
Functional Description
This design has two output functions: reset generation and watchdog timer. The behavior of these two outputs is
controlled by the condition of the six VMON inputs, two input pins, and the status of three configuration pins.
The reset generation output pin (Reset_CPU) is active low and is held low when any of the VMON inputs is below
the respective trip point threshold or when the input Manual_reset is held low. Each of the voltage monitoring inputs
is filtered with a 48-microsecond glitch filter. The Reset_CPU output will go high after the last VMON input is above
its respective trip point and the Manual_reset input is high. If the Stretch_200ms input is low, the Reset_CPU output will go high with no delay but, if the Stretch_200ms input is high, then the Reset_CPU output will go high after a
200ms delay. The pin Manual_reset is an active low input that is de-bounced by a 50ms timer circuit. The minimum
pulse width of the Manual_reset input is 10us.
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1
rd1056_01.0
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
The watchdog output pin (WDT_Int) is active low that pulses low when the watchdog timer delay expires. The two
input pins WDT_Sel1 and WDT_Sel0 signals are used to select the Watchdog timer delay as listed in Table 1. The
watchdog timers are reset by the falling edge of the WDT_Trig input. The minimum pulse width of the WDT_Trig
input is 10 microseconds. When the delay between successive WDT_Trig falling edge signals exceeds the watchdog timer delay setting, a low-going pulse is generated on the WDT_Int output. After generating the output pulse,
the watchdog timer is restarted. It continues to generate low-going pulses regularly at watchdog delay set intervals
until a falling edge of WDT_Trig signal is received. The watchdog timers are held in reset when the Reset_CPU
output is active and released when the Reset_CPU output goes high.
Table 1. Programmable Watchdog Timer Delay Selection
WDT_Sel1
WDT_Sel0
Watchdog Timer Delay (Typ.)
0
0
500 ms
0
1
2 sec.
1
0
10 sec.
1
1
1 min.
Table 2. Pin Description
Pin
Function
Name
Type
Description
1
VMON1
Main_3V3_OK
Analog Input
Voltage monitor of 3.3V supply
2
VMON21
IO_2V5_OK
Analog Input
Voltage monitor of 2.5V supply
3
VCC
VCC
Power
Power supply
1
4
VMON3
IO_1V8_OK
Analog Input
Voltage monitor of 1.8V supply
5
VMON41
Prog1_OK
Analog Input
Voltage monitor of programmable supply
6
1
VMON5
Prog2_OK
Analog Input
Voltage monitor of programmable supply
7
VMON61
Prog3_OK
Analog Input
Voltage monitor of programmable supply
8
GND
Ground
Ground
Ground
9
GND
Ground
Ground
Ground
10
VCCJ
VCCJ
Power
VCC for JTAG logic interface pins
11
TDO
TDO
Output
JTAG test data out
12
TCK
TCK
Input
JTAG test clock
13
TDI
TDI
Input
JTAG test data in
14
TMS
TMS
Input
JTAG test mode select
15
IN_OUT5
WDT_Sel1
Input
Watchdog timer delay select MSB
16
VCC
VCC
Power
Power supply
17
IN_OUT4
WDT_Sel0
Input
Watchdog timer delay select LSB
18
IN_OUT3
Stretch_200ms Input
Reset_CPU pulse stretch: Low=none, High=200ms
19
IN_OUT2
WDT_Int
Output
Watchdog timer interrupt, active low.
20
IN_OUT1
Reset_CPU
Output
Reset generator output, active low.
21
IN2
WDT_Trig
Input
Watchdog timer trigger, negative edge resets WDT.
22
IN1_PWRDN
Manual_reset
Input
Reset generator input, active low.
23
NC
NC
N/A
No connection
24
NC
NC
N/A
No connection
25
Die Pad
NC
N/A
No connection
1. Connect unused VMON inputs to VMON1.
2
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Design Description
In order to fit all the functionality of this design into 13 macrocells, the design is realized using Supervisory Logic
Equations in PAC-Designer software. This section describes the function and interaction of these equations using
block diagrams combined with listings of the 20 Supervisory Logic Equations. First we will discuss the Reset Generator function and then the Watchdog Timer function.
In Figure 1, the reset generator function is represented with four key blocks. The Analog Settings block translates
the power supply voltage levels into a logic true for good voltage conditions and false for under voltage conditions.
The Glitch Filter (GF) ensures that voltage transients that are less than 48us are blocked from the logic. All of the
VMON outputs are ANDed together with the Manual_reset input in Equation 8 to provide the gate signal for Timer
4. When the gate signal of a timer is low, the timer is reset and its output is also low. When the timer gate signal is
high, the timer is allowed to run and after the time-out period the Terminal Count output (TC) goes high. Timer 4 is
set for 200ms to support the pulse stretch option.
Figure 1. Six-Supply Reset Generator Block Diagram
Analog Settings
3V3_Rail
2V5_Rail
Main_3V3_OK
3.3V -5%
GF
IO_2V5_OK
2.5V -5%
GF
Equation 8
1V8_Rail
IO_1V8_OK
1.8V -5%
GF
D
ADJ1
ADJ2
ADJ3
Manual_reset
Timer 4
200ms
Equation 8
Prog1_OK
0.669V
GF
Q
Prog2_OK
0.669V
GF
TIMER4_GATE
Prog3_OK
0.669V
TIMER4_TC
GF
TIMER1_GATE
Timer 1
50ms
Equation 20
TIMER1_TC
RST
Stretch_200ms
D
Macrocell
Equation 9
Q
Equations 9 &19
250kHz
PLD_CLK
Reset_CPU
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Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Equation 9 decodes the state of the input Stretch_200ms and combines the status of either the gate or the terminal
count condition to drive the Reset_CPU output. Equation 20 defines the gate of Timer 1 which is used to debounce the Manual_reset input. Equation 19 provides the asynchronous reset to the Reset_CPU output macrocell
so the output will go low as soon as Manual_reset is asserted and will stay low as long as Manual_reset is
asserted. Reset_CPU will stay low for at least 50ms after Manual_reset is de-asserted and stable. The 250kHz
PLD clock drives the 200ms and 50ms timers and the Reset_CPU macrocell. Listing 1 contains the equations that
make up the Reset Generator Function.
Listing 1. Reset Generator Equations
EQ 8
EQ 9
TIMER4_GATE.D = Main_3V3_OK AND IO_2V5_OK AND IO_1V8_OK AND
Prog1_OK AND Prog2_OK AND Prog3_OK AND Manual_reset
Reset_CPU.D
= Stretch_200ms AND TIMER4_TC OR
NOT Stretch_200ms AND TIMER4_GATE
.
. {equations 10 - 18 are used for the watchdog function: see Listing 2}
.
EQ 19 Reset_CPU.ar = NOT TIMER1_TC
EQ 20 TIMER1_GATE.D = Manual_reset
Figure 2. Selectable Watchdog Timer Block Diagram
Equation 7 & 18
WDT_Trig
D
Macrocell
Equation 7
Q
WDT_Fall_Edge
Reset_CPU
WDT_Reset
Equation 6
Cnt4
Equations 5 & 15
cnt3
Equations 4 &14
Count=30
Cnt2
Equations 3 & 13
SEL=0x11
cnt1
Equations 2 & 12
Count=5
Cnt0
Equations 1 & 11
SEL=0x10
Timer 2
2s
Equations 0 & 16
TIMER2_TC
Timer 3
500ms
Equations 10 & 17
TIMER3_TC
WDT_Int
SEL=0x01
SEL=0x00
250kHz
PLD_CLK
WDT_Sel1
WDT_Sel0
4
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
In Figure 2 the Watchdog Timer function is represented by two large blocks and several smaller ones. The largest
block is Equation 6 that decodes the WDT_Sel1 and WDT_Sel0 inputs and combines the appropriate timer terminal count or counter combination to drive the WDT_Int output. Equation 7 synchronizes the WDT_Trig input to the
internal PLD clock and Equation 18 detects the falling edge to reset the timers and counters. Equation 18 also OR’s
the Reset_CPU output and WDT_Int output to drive the internal node WDT_Reset. Equations 1- 5 define a five-bit
binary counter that counts the number of times the 2 second timer has expired. Equations 11-15 provide the asynchronous reset to the binary counter from the internal WDT_Reset node. Equation 0 allows the 2-second timer to
self-run, providing the binary counter a time base and Equation 16 provides the asynchronous reset for timer 2.
Equation 10 allows the 500ms timer to run regardless of the state of WDT_Trig input and Equation 17 provides the
asynchronous reset for timer 3. The watchdog timer equations are shown in Listing 2 and further details of timers 2
and 3 are provided in Figure 3. Table 3 lists the critical timing specifications for the entire design.
Listing 2. Watchdog Timer Equations
EQ
EQ
EQ
0
1
2
TIMER2_GATE.D
Cnt0.D
cnt1.D
=
=
=
EQ
3
Cnt2.D
=
EQ
4
cnt3.D
=
EQ
5
Cnt4.D
=
EQ
6
WDT_Int.D
=
EQ
7 WDT_Fall_Edge.D =
.
. {equations 8 & 9 are used for reset generation: see Listing 1}
.
EQ
EQ
EQ
EQ
EQ
EQ
EQ
EQ
EQ
10
11
12
13
14
15
16
17
18
NOT TIMER2_TC
Cnt0 AND NOT TIMER2_TC OR NOT Ctr0 AND TIMER2_TC
( NOT cnt1 AND Cnt0 AND TIMER2_TC ) OR
( cnt1 AND NOT ( Cnt0 AND TIMER2_TC ) )
( NOT Cnt2 AND cnt1 AND Cnt0 AND TIMER2_TC ) OR
( Cnt2 AND NOT ( cnt1 AND Cnt0 AND TIMER2_TC ) )
( NOT cnt3 AND Cnt2 AND cnt1 AND Cnt0 AND TIMER2_TC ) OR
( cnt3 AND NOT ( Cnt2 AND cnt1 AND Cnt0 AND TIMER2_TC ) )
( NOT Cnt4 AND cnt3 AND Cnt2 AND cnt1 AND Cnt0 AND TIMER2_TC ) OR
( Cnt4 AND NOT ( cnt3 AND Cnt2 AND cnt1 AND Cnt0 AND TIMER2_TC ) )
NOT ( ( NOT WDT_Sel0 AND NOT WDT_Sel1 AND TIMER3_TC ) OR
( NOT WDT_Sel1 AND WDT_Sel0 AND TIMER2_TC ) OR
( WDT_Sel1 AND NOT WDT_Sel0 AND Cnt2 AND NOT cnt1 AND Cnt0 ) OR
( WDT_Sel0 AND WDT_Sel1 AND Cnt4 AND cnt3 AND Cnt2 AND cnt1 AND NOT Cnt0 ) )
WDT_Trig
TIMER3_GATE.D = NOT ( NOT WDT_Trig AND WDT_Fall_Edge )
Cnt0.ar = WDT_Reset
cnt1.ar = WDT_Reset
Cnt2.ar = WDT_Reset
cnt3.ar = WDT_Reset
Cnt4.ar = WDT_Reset
TIMER2_GATE.ar = WDT_Reset
TIMER3_GATE.ar = WDT_Reset
WDT_Reset.D = ( NOT WDT_Trig AND WDT_Fall_Edge ) OR
NOT WDT_Int OR NOT Reset_CPU
Table 3. Timing Specifications
Min.
Typ.
Max.
Units
Manual_reset pulse width
Description
10
—
—
us
WDT_Trig pulse width
10
—
—
us
WDT_Int pulse width
3.8
6
8.4
us
Manual_reset debounce
42.6
49.2
51.7
ms
Reset_CPU pulse stretch
186.0
213.0
223.7
ms
500ms Watchdog timer delay
432.5
524.3
550.5
ms
2 sec. Watchdog timer delay
1.737
1.966
2.064
seconds
10 sec. Watchdog timer delay
8.68
9.83
10.32
seconds
1 min. Watchdog timer delay
52.1
58.98
61.9
seconds
5
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Figure 3. Timer 2 & 3 Block Diagram
WDT_Reset
Timer 2
Equations 0 & 16
RST
Macrocell
Equation 0
D
Q
2 sec.
Timer
GATE/RST
TC
Equations 10 & 17
Timer 3
RST
Macrocell
Equation 10
D
Q
GATE/RST
500ms
Timer
TC
WDT_Fall_Edge
WDT_Trig
250kHz
PLD_CLK
Simulation and Verification
Because the simulator that is included in PAC-Designer is a functional simulator and it produces a result for every
PLD clock transition, this design is simulated with reduced timer values as listed in Table 4. By using a timer value
that is roughly 1000 times shorter, the simulation time, data file size, and redraw time are all optimized. Also, using
a factor of 1000 results in a more straightforward interpretation of the simulation results (1000us = 1ms). One must
be sure to reset the timers back to the design value before generating a JEDEC file or programming the device.
Table 4. Timing Specifications
Timer (ms)
Design Value
Simulation Value
Timer 1
49.15
0.048
Timer 2
1966.08
1.92
Timer 3
524.29
0.512
Timer 4
212.99
0.208
Hardware verification of this design is available using the ProcessorPM Evaluation Board (order part number
PACPOWR605-P-EVN) as shown in Figure 4. One key difference in the design programmed into the evaluation
board and the design that is described in this document is the WDT_Int output is active high and not active low.
This is to support a pulse stretching circuit on the evaluation board to drive an LED. The evaluation board design
file is also located in the PAC-Designer Examples folder and is named POWR605-5-Evaluation_Board.pac.
6
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Figure 4. ProcessorPM Evaluation Board
Figure 5. Simulation of De-Bounce
7
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Figure 6. Simulation of Pulse Stretch and 500ms Watchdog
Figure 7. Simulation of Pulse Stretch and 2s Watchdog
8
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Figure 8. Simulation of Pulse Stretch and 10s Watchdog
Figure 9. Simulation of Pulse Stretch and 60s Watchdog
9
Supervisor, WDT and Reset Generation
with ProcessorPM
Lattice Semiconductor
Implementation
Table 5. Performance and Resource Utilization1
Device Family
Macrocells
Product Terms
VMONs
I/Os
Timers
ProcessorPM-POWR605
13
52
6
7
4
1. Resource utilization characteristics are generated using PAC-Designer 5.1 software. When using this design in a different device,
utilization characteristics may vary.
References
• ProcessorPM-POWR605 Data Sheet
• ProcessorPM Development Kit User’s Guide
• AN6076 – Optimizing the Accuracy of ispPAC Power Manager Timers
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
[email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
July 2009
01.0
Change Summary
Initial release.
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