JANSR2N7281 Formerly FRL430R4 Data Sheet Radiation Hardened, N-Channel Power MOSFET November 1998 File Number 4294 Features • 2A, 500V, rDS(ON) = 2.50Ω The Intersil has designed a series of SECOND GENERATION hardened power MOSFETs of both NChannel and P-Channel enhancement types with ratings from 100V to 500V, 1A to 60A, and on resistance as low as 25mΩ. Total dose hardness is offered at 100K RAD (Si) and 1000K RAD (Si) with neutron hardness ranging from 1E13 for 500V product to 1E14 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current limiting and 2E12 with current limiting. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and neutron (no) exposures. Design and processing efforts are also directed to enhance survival to dose rate (GAMMA DOT) exposure. • Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) • Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM • Photo Current - 8nA Per-RAD (Si)/s Typically • Neutron - Maintain Pre-RAD Specifications for 3E12 Neutrons/cm2 - Usable to 3E13 Neutrons/cm2 Symbol D Also available at other radiation and screening levels. See us on the web, Intersil’ home page: www.semi.intersil.com. Contact your local Intersil Sales Office for additional information. G S Ordering Information PART NUMBER JANSR2N7281 PACKAGE TO-205AF BRAND JANSR2N7281 Package TO-205AF Die family TA17635. MIL-PRF-19500/604. D 4-1 G S CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 JANSR2N7281 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJC, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JANSR2N7281 500 500 UNITS V V 2 1 6 ±20 A A A V 25 10 0.20 6 2 6 -55 to 150 300 W W W/oC A A A oC oC 1.0 g CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 1mA Zero Gate Voltage Drain Current IDSS VDS = 400V, VGS = 0V Gate to Source Leakage Current IGSS VGS = ±20V Drain to Source On-State Voltage VDS(ON) On Resistance rDS(ON) Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time MIN MAX ID = 1A, VGS = 10V 500 - - V - - 5.0 V TC = 25oC 2.0 - 4.0 V TC = 125oC 1.0 - - V TC = 25oC TC = 125oC TC = 25oC TC = 125oC - - 25 µA - - 250 µA - - 100 nA TC = 25oC TC = 125oC VDD = 250V, ID = 2A, RL = 125Ω, VGS = 10V, RGS =25Ω tf VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V UNITS TC = -55oC VGS = 10V, ID = 2A Qg(TOT) Total Gate Charge TYP VDD = 250V, ID = 2A, RL = 125Ω 200 nA 5.25 V - - 2.50 Ω - - 6.50 Ω - - 46 ns - - 58 ns - - 208 ns - - 54 ns - - 130 nC - - 64 nC - - 4 nC nC Gate Charge Source Qgs - - 12 Gate Charge Drain Qgd - - 32 nC RθJC RθJA Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient - - 5.0 oC/W - - 175 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage VSD Reverse Recovery Time trr 4-2 TEST CONDITIONS ISD = 2A ISD = 2A, dISD/dt = 100A/µs MIN TYP MAX UNITS 0.6 - 1.8 V - - 900 ns JANSR2N7281 Electrical Specifications up to 100K RAD TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS V Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA 500 - Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA 2.0 4.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±20V, VDS = 0V - 100 nA IDSS Zero-Gate Leakage (Note 3) VGS = 0, VDS = 400V - 25 µA Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 10V, ID = 2A - 5.25 V Drain to Source On Resistance (Notes 1, 3) rDS(ON) VGS = 10V, ID = 1A - 2.5 Ω NOTES: 1. Pulse test, 300µs Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = 10V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Typical Performance Curves Unless Otherwise Specified 30 TC = 25oC 10 ID , DRAIN CURRENT (A) ID , DRAIN (A) 2 1 0 -50 0 50 100 150 TC , CASE TEMPERATURE (oC) FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 100µs 1 1ms 10ms 0.1 0.01 1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100ms 100 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 1000 FIGURE 2. FORWARD BIAS SAFE OPERATING AREA 1.0 NORMALIZED THERMAL RESPONSE (ZqJC) 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE PDM NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZqJC + TC 0.001 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE 4-3 100 t1 t2 101 JANSR2N7281 Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS VARY tP TO OBTAIN REQUIRED PEAK IAS tP VDD 50V-150V DUT tP VDD + 50Ω VGS ≤ 20V 0V VDS IAS 50Ω tAV FIGURE 4. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 5. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS VGS = 10V 10% DUT 10% 0V 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 6. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 7. RESISTIVE SWITCHING WAVEFORMS QG 10V QGS QGD VG CHARGE BASIC GATE CHARGE WAVEFORM FIGURE 8. BASIC GATE CHARGE WAVEFORM 4-4 JANSR2N7281 Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 4) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 4) µA On Resistance rDS(ON) TC = 125oC at Rated ID ±20% (Note 5) Ω Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 5) V NOTES: 4. Or 100% of Initial Reading (whichever is greater). 5. Of Initial Reading. Screening Information TEST JANS Gate Stress VGS = 30V, t = 250µs Pind Required Pre Burn-In Tests (Note 6) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 6) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 5% Final Electrical Tests (Note 6) MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 6. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER SYMBOL Safe Operating Area SOA Unclamped Inductive Switching TEST CONDITIONS VDS = 200V, t = 10ms MAX UNITS 0.50 A IAS VGS(PEAK) = 15V, L = 0.1mH 6 A Thermal Response ∆VSD tH = 10ms; VH = 25V; IH = 2A 92 mV Thermal Impedance ∆VSD tH = 500ms; VH = 25V; IH = 1A 190 mV 4-5 JANSR2N7281 Rad Hard Data Packages - Intersil Power Transistors 1. JANS Rad Hard - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. JANS Rad Hard - Optional Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data 4-6 JANSR2N7281 TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES ØD ØD1 SYMBOL P A SEATING PLANE h L Øb e e1 2 e2 1 90o 3 45o j k MIN MILLIMETERS MAX MIN MAX NOTES A 0.160 0.180 4.07 4.57 - Øb 0.016 0.021 0.41 0.53 2, 3 ØD 0.350 0.370 8.89 9.39 - ØD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 4-7 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029