HM-65262/883 TM 16K x 1 Asynchronous CMOS Static RAM March 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Fast Access Time . . . . . . . . . . . . . . . . . . . 70/85ns Max • Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max • Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max • Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max • TTL Compatible Inputs and Outputs • JEDEC Approved Pinout • No Clocks or Strobes Required • Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC • Gated Inputs-No Pull-Up or Pull-Down Resistors Required • Equal Cycle and Access Time • Single 5V Supply The HM-65262/883 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262/883 is available in both JEDEC Standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high board-level packing density. Gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resistors. The HM-65262/883, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices. Ordering Information 70ns/20µA HM4-65262B/883 85ns/20µA 85ns/400µA TEMP. RANGE PACKAGE PKG. NO. HM1-65262/883 - -55oC to +125oC CERDIP F20.3 HM4-65262/883 - -55oC to +125oC CLCC J20.C Pinouts 19 A13 A13 20 VCC 2 VCC 1 A1 A0 A0 HM-65262 (CLCC) TOP VIEW A1 HM1-65262/883 (CERDIP) TOP VIEW 2 1 20 19 A0 - A13 18 A12 A2 3 18 A12 A2 3 A3 4 17 A11 A3 4 17 A11 A4 5 16 A10 A4 5 A5 6 15 A9 W 9 12 D GND 10 11 E Q Data Out A5 6 15 A9 D Data In A6 7 14 A8 Q 8 13 A7 VSS/GND Ground 9 10 11 12 VCC Power (+5) D 13 A7 16 A10 E 14 A8 8 Chip Enable/Power Down W 7 Q E GND A6 Address Input W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 204 Write Enable FN3003.2 HM-65262/883 Functional Diagram A0 A1 A2 A3 A4 A12 A13 A 7 ROW ROW ADDRESS DECODER 128 MEMORY ARRAY BUFFER A (1 OF 128) 128 X 128 7 128 COLUMN DECODER (1 OF 128) AND I / O CIRCUITRY D A 7 A 7 E COLUMN ADDRESS BUFFERS A7 A8 A9 A10 A11 A5 A6 W 205 Q HM-65262/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades . . . . . -0.3V to VCC +0.3V Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical) θJA θJC CERDIP Package. . . . . . . . . . . . . . . . . . 66oC/W 13oC/W CLCC Package . . . . . . . . . . . . . . . . . . . 75oC/W 18oC/W Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . ±2.2V to VCC Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max. TABLE 1. HM-65262/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested DC PARAMETER (NOTE 1) CONDITIONS SYMBOL GROUP A SUB-GROUPS TEMPERATURE MIN MAX UNITS High Level Output Voltage VOH1 VCC = 4.5V, IO = -4.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.4 - V Low Level Output Voltage VOL VCC = 4.5V, IO = 8.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V VCC = 5.5V, E = 5.5V, VO = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA VCC = 5.5V, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA - 50 µA High Impedance Output Leakage Current IOZ Input Leakage Current II Standby Supply Current ICCSB1 VCC = 5.5V, IO = 0mA, E = VCC -0.3V 1, 2, 3 -55oC ≤ TA ≤ +125oC Standby Supply Current ICCSB VCC = 5.5V, IO = 0mA, E = 2.2V 1, 2, 3 -55oC ≤ TA ≤ +125oC - 5 mA Operating Supply Current ICCOP VCC = 5.5V, (Note 2), f = 1MHz, E = 0.8V 1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 mA Data Retention Supply Current ICCDR VCC = 2.0V, IO = 0mA, E = VCC -0.3V 1, 2, 3 -55oC ≤ TA ≤ +125oC - 20 µA Enable Supply Current ICCEN VCC = 5.5V, IO = 0mA, E = 0.8V 1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 mA 7, 8A, 8B -55oC ≤ TA ≤ +125oC - - - Functional Test FT VCC = 4.5V (Note 3) NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V. TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested AC PARAMETER SYMBOL HM65262B/883 LIMITS HM-65262/883 LIMITS (NOTES 1, 2) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX MIN MAX UNITS Read/Write/Cycle Time (1) TAVAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 70 - 85 - ns Address Access Time (2) TAVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 70 - 85 ns 206 HM-65262/883 TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested HM65262B/883 LIMITS HM-65262/883 LIMITS (NOTES 1, 2) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX MIN MAX UNITS AC PARAMETER SYMBOL Chip Enable to End of Write (3) TELWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 55 - 65 - ns Chip Enable Access Time (4) TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 70 - 85 ns Address Hold Time (5) TWHAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - ns Address Setup Time (6) TAVWL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - ns Address Valid to End of Write (7) TAVWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 55 - 65 - ns Address Setup Time (8) TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - ns Address Hold Time (9) TEHAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - ns 55 - 65 - ns Address Valid to End of Writes (10) TAVEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC Write Enable Pulse Write (11) TWLWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - 45 - ns Data Setup Time (12) TDVWH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 30 - 35 - ns 0 - 0 - ns Data Hold Time (13) TWHDX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC Enable Pulse Width (14) TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 55 - 65 - ns Write to End of Write (15) TWLEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - 45 - ns Data Setup Time (16) TDVEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 30 - 35 - ns 9, 10, 11 -55oC ≤ TA ≤ +125oC 0 - 0 - ns Data Hold Time (17) TEHDX VCC = 4.5V and 5.5V NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC LIMITS PARAMETER Input Capacitance Output Capacitance SYMBOL CIN CO (NOTE 1) CONDITIONS NOTES TEMPERATURE MIN MAX UNITS VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds 1, 2 TA = +25oC - 10 pF VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds 1, 3 TA = +25oC - 6 pF VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds 1, 2 TA = +25oC - 12 pF VCC = Open, f = 1MHz, All Measurements Referenced To Device Grounds 1, 3 TA = +25oC - 8 pF 207 HM-65262/883 TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC (Continued) LIMITS PARAMETER SYMBOL Write Enable to Output in High Z (18) TWLQZ Write Enable High to Output ON Chip Enable to Output ON Output Enable High to Output in High Z NOTES TEMPERATURE MIN MAX UNITS VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC - 40 ns (19) TWHQX VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 0 - ns (20) TELQX VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 5 - ns (21) TEHQZ VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC - 40 ns VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤+125oC 5 - ns (23) TAXQX VCC = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 5 - ns 1 -55oC ≤ TA ≤ +125oC- VCC -0.4V - V (22) TEHQX Chip Disable to Output Hold Time Address Invalid Output Hold Time High Level Output Voltage (NOTE 1) CONDITIONS (24) VOH2 VCC = 4.5V, IO = -100mA NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to DIP device types only. 3. Applies to LCC device types only. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100%/5004 1 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 208 HM-65262/883 Timing Waveforms A (4) TELQV E (21) TEHQZ (20) TELQX (22) TEHQX Q NOTE: 1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high. FIGURE 1. READ CYCLE 1: CONTROLLED BY E (1) TAVAX A (2) TAVQV E (21) TEHQZ (20) TELQX (23) TAXQX Q NOTE: 1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid. FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS 209 HM-65262/883 Timing Waveforms (Continued) (1) TAVAX A (5) TWHAX (7) TAVWH (3) TELWH E (6) TAVWL (21) TEHQZ (11) TWLWH W (12) TDVWH (13) TWHDX D (18) TWLQZ (20) TELQX (19) TWHQX Q NOTE: 1. In this mode, E rises after W. The address must remain stable whenever both E and W are low. FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE) (1) TAVAX A (10) TAVEH (8) TAVEL (9) TEHAX (14) TELEH E (15) TWLEH W (19) TWHQX (16) TDVEH (17) TEHDX D (20) TELQX Q (18) TWLQZ (21) TEHQZ NOTE: 1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle. FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE) Low Voltage Data Retention 210 HM-65262/883 Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 1. Chip Enable (E) must be held high during data retention; within VCC to VCC +0.3V. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation >55ns after VCC reaches the minimum operating voltage (4.5V). DATA RETENTION MODE VCC VCC ≥ 2.0V 4.5V 4.5V >55ns VCC -0.3V TO VCC +0.3V E FIGURE 5. DATA RETENTION TIMING Test Circuit DUT (NOTE 1) CL IOH + - 1.5V EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. 211 IOL HM-65262/883 Burn-In Circuits HM-65262/883 CERDIP TOP VIEW HM-65262/883 CLCC TOP VIEW A3 F6 A4 F7 A5 F8 A6 F9 Q F2 W F1 GND 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 A13 A12 A11 A10 A9 A8 A7 D E F15 2 F14 F16 F0 F16 1 20 19 A12 A2 F13 F5 18 3 A3 F12 F6 F11 4 17 5 16 A4 F7 F10 F2 F8 F0 F9 A5 15 6 A6 14 7 Q 13 8 F15 A11 A10 A9 A8 F14 F13 F12 F11 A7 F10 11 12 F2 D E 10 F0 F1 W 9 GND F2 C A13 F5 2 VCC VCC A2 20 A0 A1 F4 1 A1 A0 F3 F4 VCC NOTES: NOTES: All resistors 47kΩ ±5%. All resistors 47kΩ ±5%. F0 = 100kHz ±10%. F0 = 100kHz ±10%. F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2. F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F13 = F12 ÷ 2. VCC = 5.5V ±0.5V. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V. VIL = -0.2V to +0.4V. C = 0.01µF Min. C = 0.01µF Min. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 212 Die Characteristics DIE DIMENSIONS: 148 x 187 x 19 mils GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ METALLIZATION: Type: Si - Al Thickness: 11kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.2 x 105 A/cm 2 Metallization Mask Layout HM-65262/883 A2 A1 A0 VCC A13 A12 A3 A11 A4 A10 A5 A9 A6 A8 Q W E GND 213 D A7