RT9218B

RT9218B
12V Synchronous Buck PWM DC/DC and Linear Power
Controller
General Description
Features
The RT9218B is a dual output with one synchronous buck
PWM and one linear controller. The part is proposed to
generate logic-supply voltages for PC based systems. The
high-performance device includes internal soft-start,
frequency-compensation networks, power good signaling
with specific sequence, and it comes all of the logic control,
output adjustment, power monitoring and protection
functions into a small footprint package. The part is
operated at fixed 300kHz frequeny providing an optimum
compromise between efficiency, external component size,
and cost. The linear controller is implemented to drive an
external MOSFET for regulation and it's adjustable by
setting external resistors. Moreover the specific internal
PGOOD sequence and indicator is also implemented to
conform to Intel® new platform requirement on FSB_VTT
power plane. An adjustable over-current protection (OCP)
is proposed to monitor the voltage drop across the RDS(ON)
of the lower MOSFET for synchronous buck PWM DC/DC
controller.
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Applications
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Ordering Information
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RT9218B
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Package Type
S : SOP-14
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Operating with 12V Supply Voltage
Drives All Low Cost N-MOSFETs
Voltage Mode PWM Control
300kHz Fixed Frequency Oscillator
Fast Transient Response :
` High-Speed GM Amplifier
` Full 0 to 100% Duty Ration
Internal Soft-Start
Power Good Indicator
Adaptive Non-Overlapping Gate Driver
Over Current Fault Monitor on MOSFET, No Current
Sense Resistor Required
Specific Power Good Indicator for Intel® Grantsdale
FSB_VTT Power Sequence
RoHS Compliant and 100% Lead (Pb)-Free
Graphic Card
Motherboard, Desktop Servers
IA Equipments
Telecomm Equipments
High Power DC/DC Regulators
Pin Configurations
(TOP VIEW)
BOOT
UGATE
GND
LGATE
DRV
NC
NC
2
3
4
5
6
7
14
13
12
11
10
9
8
PHASE
OPS
FB
VCC
PGOOD
FBL
NC
SOP-14
DS9218B-10 April 2011
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1
RT9218B
Typical Application Circuit
VCC
12V
VIN
5 to 12V
RBOOT
2.2
D1
1N4148
VCC
12V
C8
PHASE
C1 to C2
1000uF x 2
SVOUT
L1
C3 to C4
1uF x 2
Q1
MU
RUGATE
C7
1uF
C5 to C6
1000uF x 2
RT9218B
1 BOOT
2 UGATE
2.2
PHASE
2.2uH
0.1uF
3
R Q2
ML
C
4
GND
LGATE
5 DRV
6
NC
7
NC
Q3
PHASE
OPS
FB
VCC
14
R3
10R
ROCSET
13
12
11
PGOOD 10
9
FBL
8
NC
Q4
C10
1uF
Disable
3904
R1
LVOUT
4k
C9
470uF
R2
8k
R4
1k/NC
R5
C11
0.1uF/NC
R6
32R
68R
SVOUT = VREF × (1 + R5 )
R6
R1
LVOUT = VREF × (1 +
)
R2
VREF : Internal reference voltage
(0.8V ± 1%)
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DS9218B-10 April 2011
RT9218B
Functional Pin Description
UGATE (Pin 2)
VCC (Pin 11)
Upper gate driver output. Connect to gate of the high-side
power N-MOSFET. This pin is monitored by the adaptive
shoot-through protection circuitry to determine when the
upper MOSFET has turned off.
Connect this pin to a well-decoupled 12V bias supply. It
is also the positive supply for the lower gate driver, LGATE.
BOOT (Pin 1)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn
on the upper MOSFET.
PHASE (Pin 14)
Connect this pin to the source of the upper MOSFET and
GND (Pin 3)
Both signal and power ground for the IC. All voltage levels
are measured with respect to this pin. Ties the pin directly
to the low-side MOSFET source and ground plane with
the lowest impedance.
DRV (Pin 5)
Connect this pin to the base/gate of an external transistor/
MOSFET. This pin provides the drive for the linear
regulator's pass transistor/MOSFET.
the drain of the lower MOSFET.
FBL (Pin 9)
OPS (OCSET, POR and Shut-Down) (Pin 13)
This pin provides multi-function of the over-current setting,
UGATE turn-on POR sensing, and shut-down features.
Connecting a resistor (ROCSET) between OPS and PHASE
pins sets the over-current trip point.
Pulling the pin to ground resets the device and all external
MOSFETs are turned off allowing the output voltage power
rails to float.
This pin is also used to detect VIN in power on stage and
issues an internal POR signal.
LGATE (Pin 4)
Lower gate drive output. Connect to gate of the low-side
power N-MOSFET. This pin is monitored by the adaptive
shoot-through protection circuitry to determine when the
lower MOSFET has turned off.
Linear regulator feedback voltage. This pin is the inverting
input of the error amplifier and protection monitor. Connect
this pin to the external resistor divider network of the linear
regulator.
PGOOD (Pin 10)
PGOOD is an open-drain output used to indicate that the
regulator is within normal operating voltage ranges and
it's implemented with a specific sequence as following
chart.
NC (Pin 6,7,8)
No internal connection.
FB (Pin 12)
Switcher feedback voltage. This pin is the inverting input
of the error amplifier. FB senses the switcher output through
an external resistor divider network.
DS9218B-10 April 2011
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3
RT9218B
Function Block Diagram
VCC
EN
+
0.15V
-
Bias & Regulators
(3V_Logic & 3VDD_Analog)
PH_M
Power On
Reset
Reference
+
0.6V
VCC
+
-
DRV
0.6V
+
-
UV_S
+
-
UV_L
1.5V
-
0.8VREF
3V
40uA
Soft-Start
&
Fault Logic
OC
+
OPS
0.4V
+
-
FBL
PGOOD
BOOT
UGATE
+
+GM
-
FB
PHASE
EO
+
+
-
Gate Control
Logic
VCC
LGATE
Oscillator
(300k/600kHz)
GND
Timing Diagram
Specific Power Sequence for LDO
90%
80%
FSB_VTT (1.2V @ 5Amp)
VTT_GD
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4
1-10ms
<1ms
DS9218B-10 April 2011
RT9218B
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VCC -----------------------------------------------------------------------------------z BOOT, VBOOT - VPHASE ---------------------------------------------------------------------------------z PHASE to GND
DC ----------------------------------------------------------------------------------------------------------< 200ns ----------------------------------------------------------------------------------------------------
16V
16V
BOOT to PHASE ---------------------------------------------------------------------------------------BOOT to GND
DC ----------------------------------------------------------------------------------------------------------< 200ns ---------------------------------------------------------------------------------------------------z UGATE ----------------------------------------------------------------------------------------------------z LGATE ----------------------------------------------------------------------------------------------------z Input, Output or I/O Voltage --------------------------------------------------------------------------z Package Thermal Resistance (Note 2)
SOP-14, θJA ----------------------------------------------------------------------------------------------z Junction Temperature ----------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------z Storage Temperature Range --------------------------------------------------------------------------z ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------
15V
z
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−5V to 15V
−10V to 30V
z
Recommended Operating Conditions
z
z
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−0.3V to VCC+15V
−0.3V to 42V
VPHASE − 0.3V to VBOOT + 0.3V
GND − 0.3V to VVCC + 0.3V
GND − 0.3V to 7V
127.67°C/W
150°C
260°C
−40°C to 150°C
2kV
200V
(Note 4)
Supply Voltage, VCC ------------------------------------------------------------------------------------ 12V ± 10%
Junction Temperature Range -------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC = 5V/12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VCC Supply Current
ICC
UGATE and LGATE Open
--
6
15
mA
POR Threshold
VCCRTH
VCC Rising
--
4.1
4.5
V
Hysteresis
VCCHYS
0.35
0.5
--
V
Nominal Supply Current
Power-On Reset
Switcher Reference
Reference Voltage
VREF
V CC = 12V
0.792
0.8
0.808
V
Free Running Frequency
fOSC
V CC = 12V
250
300
350
kHz
Ramp Amplitude
ΔVOSC
--
1.5
--
V P-P
Oscillator
To be continued
DS9218B-10 April 2011
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RT9218B
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Error Amplifier (GM)
E/A Transconductance
gm
--
0.2
--
ms
Open Loop DC Gain
AO
--
90
--
dB
--
1.4
--
mA
0.792
0.8
0.808
V
Linear Regulator
DRV Driver Source
IDS
Reference Voltage
VREFREG VCC = 12V
VDRV = 6V
PWM Controller Gate Drivers (V CC = 12V)
Upper Gate Source
IUGATE
VBOOT − VPHASE = 12V
VUGATE − VPHASE = 6V
0.6
1
--
A
Upper Gate Sink
RUGATE
VBOOT − VPHASE = 12V
VUGATE − VPHASE = 1V
--
4
--
Ω
Lower Gate Source
ILGATE
VCC = 12V, V LGATE = 6V
0.6
1
--
A
Lower Gate Sink
RLGATE
VCC = 12V, VLGATE = 1V
--
3
4
Ω
Dead Time
TDT
--
--
100
ns
Protection
FB Under-Voltage Trip
ΔFBUVT
FB Falling
70
75
80
%
FBL Under-Voltage Trip
ΔFBLUVT FB and FBL Falling
70
75
80
%
OC Current Source
IOC
--
40
--
μA
Soft-Start Interval
TSS
--
3.5
--
ms
VPHASE = 0V
Power Good
Power Good Rising Threshold
VCC = 12V
--
90
--
%
Power Good Hysteresis
VCC = 12V
--
10
--
%
PG Sink Capability
VCC = 12V, 1mA
--
0.2
0.4
V
Power Good Rising Delay
VCC = 12V
1
3
10
ms
Power Good Falling Delay
VCC = 12V
--
15
--
μs
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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DS9218B-10 April 2011
RT9218B
Typical Operating Characteristics
(VOUT = 2.5V, unless otherwise specified )
Efficiency vs. Output Current
Soft Start & PGOOD
1
0.95
Efficiency(%)
0.9
PGOOD
0.85
(1V/Div)
0.8
0.75
0.7
0.65
0.6
SVOUT
VCC = 12V
VIN = 5V
0
IL
5
10
15
20
(500mV/Div)
(2A/Div)
Time (10ms/Div)
25
Output Current (A)
Reference Voltage vs. Temperature
Reference Voltage (V)
0.81
Frequency vs. Temperature
350
VCC = 12V
VIN = 5V
330
Frequency (kHz)
0.812
0.808
0.806
0.804
0.802
310
290
270
0.8
250
0.798
-40 -25 -10
5
20
35
50
65
80
-40
95 110 125
-10
20
50
80
110
140
Temperature (°C)
Temperature (°C)
OCP
POR vs. Temperature
POR Rising or Falling (V)
4.75
Rising
4.5
(10V/Div)
UGATE
4.25
4
(10A/Div)
Falling
3.75
IL
VCC = 12V, VIN = 5V
IOCSET= 20A
ROCSET = 15kΩ
3.5
-40
-10
20
50
80
110
140
Time (5us/Div)
Temperature (°C)
DS9218B-10 April 2011
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RT9218B
Transient Response (Rising)
Transient Response (Falling)
L = 2.2uH
C = 2000uF
UGATE
UGATE
(10V/Div)
(10V/Div)
SVOUT
(100mV/Div)
SVOUT
(100mV/Div)
VCC = VIN = 12V
IOUT= 0A to 15A
IL
(10A/Div)
L = 2.2uH
C = 2000uF
f = 1/20ms, SR = 2.5A/us
VCC = VIN = 12V
IOUT= 15A to 0A
f = 1/20ms
(10A/Div) SR = 2.5A/us
IL
Time (5us/Div)
Time (25us/Div)
Power On
Power Off
V CC
(500mV/Div)
SVOUT
SV OUT
(2A/Div)
IOUT
V IN
UGATE
UGATE
(10V/Div)
Time (500us/Div)
Time (5ms/Div)
Dead Time (Rising)
Dead Time (Falling)
VCC = 12V
VIN = 5V
IOUT= 25A
VCC = 12V
VIN = 5V
IOUT= 25A
UGATE
PHASE
LGATE
Time (25ns/Div)
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UGATE
PHASE
LGATE
Time (10ns/Div)
DS9218B-10 April 2011
RT9218B
Application Information
Inductor Selection
The selection of output inductor is based on the
considerations of efficiency, output power and operating
frequency. Low inductance value has smaller size, but
results in low efficiency, large ripple current and high output
ripple voltage. Generally, an inductor that limits the ripple
current (ΔIL) between 20% and 50% of output current is
appropriate. Figure 1 shows the typical topology of
synchronous step-down converter and its related
waveforms.
iS1
L
iS2
S2
+
VOR
+
VOC
-
ΔIL
V
D
; Δt = ; D = OUT
Δt
fs
VIN
L = (VIN − VOUT ) ×
VOUT
VIN × fs × ΔIL
(1)
Where :
VIN = Maximum input voltage
VOUT = Output Voltage
rC
ΔIL = Inductor current ripple
IOUT
iC
+
VIN
VIN − VOUT = L
Δt = S1 turn on time
IL
+ VL S1
According to Figure 1 the ripple current of inductor can be
calculated as follows :
+
RL
COUT
VOUT
-
fS = Switching frequency
D = Duty Cycle
rC = Equivalent series resistor of output capacitor
Output Capacitor
The selection of output capacitor depends on the output
ripple voltage requirement. Practically, the output ripple
voltage is a function of both capacitance value and the
equivalent series resistance (ESR) rC. Figure 2 shows the
related waveforms of output capacitor.
TS
Vg1
TON TOFF
Vg2
VIN - VOUT
VL
diL VIN-VOUT
=
L
dt
iL
diL
VOUT
dt =
L
IOUT
- VOUT
TS
iL
iC
ΔIL
IL = IOUT
iS1
1/2ΔIL
0
ΔIL
VOC
ΔVOC
iS2
VOR
ΔIL x rc
0
Figure 1. The waveforms of synchronous step-down
converter
DS9218B-10 April 2011
t1
t2
Figure 2. The related waveforms of output capacitor
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9
RT9218B
The AC impedance of output capacitor at operating
frequency is quite smaller than the load impedance, so
the ripple current (ΔIL) of the inductor current flows mainly
through output capacitor. The output ripple voltage is
described as :
ΔVOUT = ΔVOR + ΔVOC
1 t2
∫ ic dt
C O t1
1 VOUT
2
ΔVOUT = ΔIL × ΔIL × rc +
(1− D)T
S
8 COL
ΔVOUT = ΔIL × rc +
(see Figure 3 and Figure 4),
VOUT
GM
C1
(2)
C2
R1
(3)
(4)
where ΔVOR is caused by ESR and ΔVOC by capacitance.
For electrolytic capacitor application, typically 90 to 95%
of the output voltage ripple is contributed by the ESR of
output capacitor. So Equation (4) could be simplified as :
ΔVOUT = ΔIL x rc
ZOUT is the shut impedance at the output node to ground
Figure 3. A Type 2 error-amplifier with shut network to
ground
+
+
EA+
EA-
(5)
Users could connect capacitors in parallel to get calculated
ESR.
-
VOUT
RO
GM
Figure 4. Equivalent circuit
Pole and Zero :
Input Capacitor
The selection of input capacitor is mainly based on its
maximum ripple current capability. The buck converter
draws pulsewise current from the input capacitor during
the on time of S1 as shown in Figure 1. The RMS value of
ripple current flowing through the input capacitor is
described as :
Irms = IOUT D(1 − D) (A)
FP =
1
1
; FZ =
2π × R1C2
2π × R1C1
We can see the open loop gain and the Figure 3 whole
loop gain in Figure 5.
(6)
The input capacitor must be cable of handling this ripple
current. Sometime, for higher efficiency the low ESR
capacitor is necessarily.
Gain (dB)
Open Loop, Unloaded Gain
A
FZ
FP
Gain = GMR1
PWM Loop Stability
RT9218B is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier).
The transconductance :
dI
GM = OUT
dVm
The mid-frequency gain :
Closed Loop, Unloaded Gain
100
1000
10k
B
100k
Frequency (Hz)
Figure 5. Gain with the Figure 2 circuit
RT9218B internal compensation loop :
GM = 0.2ms, R1 = 75kΩ, C1 = 2.5nF, C2 = 10pF
dVOUT = dIOUT Z OUT = GMdVIN Z OUT
dVOUT
G=
= GMZ OUT
dVIN
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DS9218B-10 April 2011
RT9218B
OPS (Over Current Setting, VIN_POR and Shutdown)
1.OCP
Sense the low-side MOSFET's RDS(ON) to set over-current trip point.
Connecting a resistor (ROCSET) from this pin to the source of the upper MOSFET and the drain of the lower MOSFET sets
the over-current trip point. ROCSET, an internal 40μA current source, and the lower MOSFET on resistance, RDS(ON), set the
converter over-current trip point (IOCSET) according to the following equation :
I OCSET =
40uA × R OCSET − 0.4V
R DS(ON) of the lower MOSFET
OPS pin function is similar to RC charging or discharging circuit, so the over-current trip point is very sensitive to parasitic
capacitance (ex. shut-down MOSFET) and the duty ratio.
Below Figures say those effect. And test conditions are Rocset = 15kΩ (over -current trip point = 20.6A), Low-side
MOSFET is IR3707.
OCP
OCP
UGATE
(10V/Div)
UGATE (10V/Div)
IL (10A/Div)
IL (10A/Div)
OPS (200mV/Div)
VIN = 5V, VCC = 12V
VOUT = 1.5V
VIN = 5V, VCC = 12V
VOUT = 1.5V
Time (5μs/Div)
Time (5μs/Div)
OCP
OCP
OPS
(200mV/Div)
UGATE (10V/Div)
UGATE
(10V/Div)
IL (10A/Div)
IL (10A/Div)
VIN = 12V, VCC = 12V
VOUT = 1.5V
Time (2.5μs/Div)
DS9218B-10 April 2011
VIN = 12V, VCC = 12V
VOUT = 1.5V
Time (2.5μs/Div)
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RT9218B
2. VIN_POR
1) Mode 1 (SS< Vramp_valley)
UGATE will continuously generate a 10kHz colck with 1%
duty cycle before VIN is ready. VIN is recognized ready by
detecting VOPS crossing 1.5V four times (rising & falling).
ROCSET must be kept lower than 37.5kΩ for large ROCSET
will keep VOPS always higher than 1.5V. Figure 6 shows
the detail actions of OCP and POR. It is highly recommended that ROCSET be lower than 30kΩ.
Initially the COMP stays in the positive saturation. When
SS< VRAMP_Valley, there is no non-inverting input available
to produce duty width. So there is no PWM signal and
VOUT is zero.
3V
40uA
ROCSET
OC
+
OPS
0.4V
10pF
+
-
VIN POR_H
+
PHASE_M
-
Cparasitic
UGATE
1.5V
PHASE
Q2
DISABLE
1st 2nd 3rd 4th OPS
waveform
(1) Internal Counter will count (VOPS > 1.5V)
four times (rising & falling) to recognize
VIN is ready.
(2) ROCSET can　be set too large. Or can　detect VIN is ready (counter = 1, not equal 4)
Figure 6. OCP and VIN_POR actions
3. Shutdown
Pulling low the OPS pin by a small single transistor can
shutdown the RT9218B PWM controller as shown in typical
application circuit.
Soft Start
A built-in soft-start is used to prevent surge current from
power supply input during power on. The soft-start voltage
is controlled by an internal digital counter. It clamps the
ramping of reference voltage at the input of error amplifier
and the pulse-width of the output driver slowly. The typical
soft-start duration is 3ms.
COMP
2) Mode 2 (VRAMP_Valley< SS< Cross-over)
When SS>VRAMP_Valley, SS takes over the non-inverting
input and produce the PWM signal and the increasing duty
width according to its magnitude above the ramp signal.
The output follows the ramp signal, SS. However while
VOUT increases, the difference between VOUT and SSE
(SS − VGS) is reduced and COMP leaves the saturation
and declines. The takeover of SS lasts until it meets the
COMP. During this interval, since the feedback path is
broken, the converter is operated in the open loop.
3) Mode3 ( Cross-over< SS < VGS + VREF)
When the Comp takes over the non-inverting input for PWM
Amplifier and when SSE (SS − VGS) < VREF, the output of
the converter follows the ramp input, SSE (SS − VGS).
Before the crossover, the output follows SS signal. And
when Comp takes over SS, the output is expected to follow
SSE (SS − VGS). Therefore the deviation of VGS is
represented as the falling of VOUT for a short while. The
COMP is observed to keep its decline when it passes the
cross-over, which shortens the duty width and hence the
falling of VOUT happens.
Since there is a feedback loop for the error amplifier, the
output’ s response to the ramp input, SSE (SS − VGS) is
lower than that in Mode 2.
4) Mode 4 (SS > VGS + VREF)
When SS > VGS + VREF, the output of the converter follows
the desired VREF signal and the soft start is completed
now.
VRAMP_Valley
Cross-over
SS_Internal
VCORE
SSE_Internal
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DS9218B-10 April 2011
RT9218B
VIN_SW (5V/12V)
Under Voltage Protection
The voltage at FB and FBL pin is monitored and protected
against UV (under voltage). The UV threshold is the FB or
FBL under 75%. UV detection has 30μs triggered delay.
When OC or UV_FBL is trigged, a hiccup restart sequence
will be initialized, as shown in Figure 7 Only 4 times of
trigger are allowed to latch off. Hiccup is disabled during
soft-start interval, but UV_FB has some difference from
OC and UV_FBL, it will always trigger VIN power sensing
after 4 times hiccup, as shown in Figure 8.
COUNT = 2
COUNT = 3
COUNT = 4
4V
SS
Internal
COUNT = 1
2V
0V
Inductor Current
OVERLOAD
APPLIED
0A
T0 T1
T2
T3
T4
TIME
Figure 7. UV and OC trigger hiccup mode
Power Off
UGATE
FB
(20V/Div)
UV
(500mV/Div)
VIN Power
Sensing
VOUT
VIN
(2V/Div)
(2V/Div)
IOUT = 2A
Time (10ms/Div)
Figure 8, UV_FB trigger VIN power sensing
LDO Power Sequence
In VGA field, the MOSFET of LVOUT is sourced by external
voltage not by SVOUT.
This connection may trigger UV protection to shutdown
RT9218B, but using the typical application circuit won't
have this issue. See figure 9 using OPS pin to control the
power sequence.
DS9218B-10 April 2011
VIN_LDO (3.3V)
OPS_Disable
Shutdown
Enable
Figure 9. LDO power sequence
PWM Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency and radiate noise, that results
in over-voltage stress on devices. Careful component
placement layout and printed circuit design can minimize
the voltage spikes induced in the converter. Consider, as
an example, the turn-off transition of the upper MOSFET
prior to turn-off, the upper MOSFET was carrying the full
load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the low side MOSFET
or schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selections, layout of the critical
components, and use shorter and wider PCB traces help
in minimizing the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using the RT9218B. The switching power
components are most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the PWM controller should
be placed firstly. Place the input capacitors, especially the
high-frequency ceramic decoupling capacitors, close to the
power switches. Place the output inductor and output
capacitors between the MOSFETs and the load. Also locate
the PWM controller near by MOSFETs.
A multi-layer printed circuit board is recommended.
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RT9218B
Figure 10 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each
of them represents numerous physical capacitors. Use a dedicated grounding plane and use vias to ground all critical
components to this layer. Apply another solid layer as a power plane and cut this plane into smaller islands of common
voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the
top and bottom circuit layers for the PHASE node, but it is not necessary to oversize this particular island. Since the
PHASE node is subjected to very high dV/dt voltages, the stray capacitance formed between these island and the
surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal routing.
The PCB traces between the PWM controller and the gate of MOSFET and also the traces connecting source of MOSFETs
should be sized to carry 2A peak currents.
IQ1
IL
VOUT
5V/12V
IQ2
+
+
+
Q1
LOAD
Q2
GND
GND
LGATE VCC
RT9218B
UGATE
FB
Figure 10. The connections of the critical components in the converter
Below PCB gerber files are our test board for your reference :
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DS9218B-10 April 2011
RT9218B
DS9218B-10 April 2011
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15
RT9218B
According to our test experience, you must still notice two items to avoid noise coupling :
1.The ground plane should not be separated.
2.VCC rail adding the LC filter is recommended.
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DS9218B-10 April 2011
RT9218B
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
8.534
8.738
0.336
0.344
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.178
0.254
0.007
0.010
I
0.102
0.254
0.004
0.010
J
5.791
6.198
0.228
0.244
M
0.406
1.270
0.016
0.050
14–Lead SOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS9218B-10 April 2011
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17