MP2910 Synchronous Buck PWM DC-DC and Linear Power Controller The Future of Analog IC Technology DESCRIPTION FEATURES The MP2910 is a dual output with one synchronous buck PWM and one linear controller. The part is used to generate logicsupply voltages for PC based systems. MP2910 includes internal soft-start, frequencycompensation networks, power good signaling with specific sequence, and it comes all of the logic control, output adjustment, power monitoring and protection functions into a small footprint package. The part is operated at fixed 300 kHz frequency providing an optimum compromise between efficiency, external component size, and cost. The linear controller is implemented to drive an external MOSFET for regulation and it's adjustable by setting external resistors. Moreover the specific internal PG sequence and indicator is also implemented to conform to Intel® new platform requirement on FSB_VTT power plane. An adjustable overcurrent protection (OCP) is proposed to monitor the voltage drop across the RDS(ON) of the lower MOSFET for synchronous buck PWM DC-DC controller. Operating with 5V or 12V Supply Voltage Drives ALL Low Cost N-Channel MOSFETs Voltage Mode PWM Control 300kHz Fixed Frequency Oscillator Fast Transient Response: High speed GM Amplifier Full 0 to 100% Duty Ratio Internal Soft-Start Adaptive Non-Overlapping Gate Driver Over-Current Fault Monitor on MOSFET, No Current Sense Resistor Required Specific Power Good Indicator for Intel® Grantsdale FSB_VTT Power Sequence Available in a SOIC-14 Package and a SOIC8E Package. APPLICATIONS Graphic Card Motherboard, Desktop Servers IA Equipments Telecomm Equipments High Power DC-DC Regulators “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 1 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER TYPICAL APPLICATION MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 2 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER ORDERING INFORMATION Part Number Package Top Marking Free Air Temperature (TA) MP2910ES* MP2910EN** SOIC14 SOIC8E MP2910ES MP2910EN –20C to +85C * For Tape & Reel, add suffix –Z (e.g. MP2910ES–Z); For RoHS, compliant packaging, add suffix –LF (e.g. MP MP2910ES–LF–Z). ** For Tape & Reel, add suffix –Z (e.g. MP2910EN–Z); For RoHS, compliant packaging, add suffix –LF (e.g. MP MP2910EN–LF–Z). PACKAGE REFERENCE SOIC14 SOIC8E ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply Voltage VCC ...................................... 16V BST, VBST-VSW .............................................. 16V SW to GND DC………………………………………...-5 to 15V <200nS………………………………….-10 to 30V HG…………………………VSW-0.3V to VBsT+0.3V LG……………………………..-0.3V to VCC+0.3V All Other Pins ................................. –0.3V to +6V Continuous Power Dissipation (TA = +25°C) (2) SOIC14 ...................................................... 1.5W SOIC8E ...................................................... 2.6W Junction Temperature ...............................150C Lead Temperature ....................................260C Storage Temperature .............. –65C to +150C SOIC8E ................................... 48 ...... 10 ... C/W SOIC14 ................................... 86 ...... 38 ... C/W Recommended Operating Conditions (4) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. (3) Supply Voltage VCC ................ 5V±5%,12±10% Operating Junct. Temp (TJ)..... –20C to +125C Ambient Temperature range ..... –20C to +85C MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 3 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER ELECTRICAL CHARACTERISTICS VCC = 5V/12V, TA = 25C, unless otherwise noted. Parameters Symbol Supply Current Nominal Supply Current Power-On Reset ICC POR Threshold VCCRTH Hysteresis VCCHYS Switcher Reference Reference Voltage Condition Min Typ Max Units 2.7 4 mA 3.8 4.1 4.4 V 0.15 0.4 UGATE AND LGATE OPEN VCC Rising V VREF VCC=12V 0.784 0.8 0.816 V fOSC ΔVOSC VCC=12V 240 290 1.5 340 kHz V Oscillator Free Running Frequency Ramp Amplitude Error Amplifier EA Transconductance Open Loop DC Gain Linear Regulator DRV Driver Source Gm AO IDS Reference Voltage VREF PWM Controller Gate Drivers (VCC=12V) Upper Gate Source IHG Upper Gate Sink RHG Lower Gate Source ILG Lower Gate Sink RLG Dead Time Protection FB Under-Voltage Trip FBL Under-Voltage Trip TDT OC Current Source IOC Soft-Start Interval TSS 0.2 85 VDRV=6V VCC=12V VBST − VSW = 12V VHG − VSW = 6V VBST − VSW = 12V VHG − VSW = 1V VCC = 12V, VLG = 6V VCC = 12V, VLG= 1V FB Falling FB and FBL Falling ms DB 2.3 0.784 0.8 0.6 1 4 0.6 75 75 VSW = 0V mA 0.816 V A 6 1 Ω A 2.8 3.8 Ω 25 100 ns 82.5 82.5 90 90 % % 38 µA 2.5 ms 90 10 0.02 4 15 % % V ms µs Power Good Power Good Rising Threshold Power Good Hysteresis PG Sink Capability Power Good Rising Delay Power Good Falling Delay MP2910 Rev. 1.0 12/14/2011 VCC=12V VCC=12V VCC=12V, 1mA VCC=12V VCC=12V 1 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 0.4 10 4 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER PIN FUNCTIONS SOIC14 Pin # SOIC8E Name Description Pin # 1 1 BST Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BST pin and the SW pin 2 2 HG Upper gate driver output. Connect to gate of the high side power N-MOSFET. 3 3 4 4 GND Both signal and power ground for the IC LG Lower gate drive output. Connect to gate of the low-side power N-MOSFET DRV This pin provides the drive for the linear regulator's pass transistor/MOSFET. 5 6, 7, 8 NC No internal connection 9 FBL Linear regulator feedback voltage. 10 PG PG is an open-drain output used to indicate that the regulator is within normal operating voltage ranges 11 5 VCC Connect this pin to a well-decoupled 5V or 12V bias supply. It is also the positive supply for the lower gate driver, LG. 12 6 FB Switcher feedback voltage. This pin is the inverting input of the error amplifier. 13 7 OPS 14 8 SW MP2910 Rev. 1.0 12/14/2011 This pin provides multi-function of the over-current setting, HG turn-on POR sensing, and shut-down features. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 5 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS VIN=12V, SVOUT=3.3V, L1=4.7μF, C5=1000μF, LVout=1.2V, TA=25°C, unless otherwise noted. MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 6 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, SVOUT=3.3V, L1=4.7μF, C5=1000μF, LVout=1.2V, TA=25°C, unless otherwise noted. MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 7 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN=12V, SVOUT=3.3V, L1=4.7μF, C5=1000μF, LVout=1.2V, TA=25°C, unless otherwise noted. MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 8 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER FUNCTION BLOCK DIAGRAM Figure 1 — Function Block Diagram TIMING DIAGRAM Specific Power Sequence for LDO 90% 80% F SB_VTT(1.3V@ 5Am p 1~10 m s VTT _G D MP2910 Rev. 1.0 12/14/2011 <1m s www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 9 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER OPERATION The MP2910 is a 5V/12V synchronous buck PWM DC/DC and linear power controller. It adopts voltage mode PWM control and includes internal soft-start, frequency-compensation networks, power good signaling with specific sequence. The part is operated at fixed 300 kHz frequency providing an optimum compromise between efficiency, external component size, and cost. The linear controller is implemented to drive an external MOSFET for regulation and it's adjustable by setting external resistors. An adjustable over-current protection (OCP) is proposed to monitor the voltage drop across the RDS(ON) of the lower MOSFET for synchronous buck PWM DC-DC controller. VCC Under-Voltage Lockout (UVLO) VCC Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP2910 UVLO’s rising threshold is about 4.1V with a hysteresis of 400mV. It’s not-latch protection. Internal Soft-Start The soft-start is employed to prevent the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a soft-start voltage (SS) ramping up from 0V. When it is lower than the internal reference (REF), SS overrides REF so the error amplifier uses SS as the reference. The output voltage smoothly ramps up with the SS voltage. When SS is higher than REF, REF regains control. The circuit enters into steady stage operation. The SS time’s typical value is 2.5ms. Power Good Indicator The PG pin is the open drain of a MOSFET, it should be connected to supply power by a resistor network. When the FB voltage reaches 90% of REF voltage, the PG pin is pulled high after an about 4ms delay. When the FB voltage drops to 80% of REF voltage, the PG pin will be pulled low. MP2910 Rev. 1.0 12/14/2011 Internal Loop Compensation MP2910 is a voltage mode buck controller with internal loop compensation using a high gain transconductance error amplifier as shown in Figure 2. Figure 2 — Compensation Loop with Transconductance Error Amplifier The pole and zero of the compensation network are: fP = 1 2π×R1C2 fZ = 1 2π×R1C1 MP2910 internal parameters: compensation network GM=0.2mS , R1 =75kΩ , C1=2.5nF , C2 =5pF OPS (Over Current Setting, VIN Power on Reset and Shutdown) (Pin 13) OCP (Over Current Setting) MP2910 senses the low-side MOSFET’s RDS(ON) to set the over current trip point. Connect an over current setting resistor ROCSET from this pin to SW (Pin 14), then the over current trip point can be estimated according to the following equation: IOCSET 38μA ROCSET - 0.4V RDS(ON) of the low-side MOSFET www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 10 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER The over current trip point is very sensitive to external parasitic capacitance because the OPS pin function is similar to RC charging/discharging circuit. When OCP is trigged, a hiccup restart sequence will be initialized and only 4 times of trigger are allowed to latch off (Refer to OCP waveforms as shown in Typical Performance Characteristics). VIN_POR (VIN Power On Reset) Before VIN is ready, the HG pin will continuously generate a 10kHz clock with 1% duty cycle. VIN is recognized ready by sensing the voltage of OPS pin crossing 1.5V four times (rising & falling). ROCSET must be lower than 39.5kΩ, otherwise, an internal 38μA current source flowing through ROCSET will keep the voltage of OPS pin always higher than 1.5V. If so, the VIN_POR function will be disabled. It is highly recommended that ROCSET be lower than 30kΩ. Shutdown Connect a small transistor from the OPS pin to ground, then enabling the transistor can shutdown the MP2910 as shown in typical application circuit. UVP (Under Voltage Protection) To protect against UV, the voltage of FB and FBL pins is monitored in MP2910. The UV threshold typical value is 82.5% of the FB or FBL rated value. Once UVP_FBL is trigged, a hiccup restart sequence will be initialized and only 4 times of trigger are allowed to latch off. During soft-start interval hiccup is disabled. UVP_FB has some difference from OCP and UVP_FBL, it will always trigger VIN Power sensing even after 4 times hiccup. So the controller will restart when the voltage of FB pin recovers. MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 11 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER APPLICATION INFORMATION Setting the Output Voltage The output voltage is set by using a resistive voltage divider from the output voltage to FB pin. First, choose a value for the feedback resistor R6, e.g. 10kΩ, and then R5 is determined as follows: R5 = VOUT -VREF R6 VREF Selecting the Inductor An inductor with a DC current rating of at least 25% higher than the maximum load current is recommended for most applications. A larger value inductor will result in less ripple current and lower output ripple voltage. However, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. Generally, choose the inductor ripple current approximately 30% of the maximum load current, then the inductance value can be calculated by: L VOUT (VIN - VOUT ) VIN ΔIL fS where VOUT is the output voltage, VIN is the input voltage, fS is the 300KHz switching frequency, and ΔI L is the peak-to-peak inductor ripple current. The maximum inductor peak current is: IL(MAX) =ILOAD + ΔIL 2 where ILOAD is the load current. Input Capacitor Selection Since the input capacitor absorbs the input switching current, it requires an adequate ripple current rating. The selection of input capacitor is mainly based on its maximum ripple current capability. The RMS value of ripple current flowing through the input capacitor is described as: IRMS =ILOAD selected must be capable of handling this ripple current. Output Capacitor Selection The output capacitor keeps output voltage ripple small and ensures regulation loop stability. The output capacitor impedance should be low at the switching frequency. The output voltage ripple can be estimated by: ΔVOUT VOUT VOUT 1 1 RESR fS L VIN 8 fS CO where CO is the output capacitance value and RESR is the equivalent series resistance (ESR) value of the output capacitor. For tantalum or electrolytic capacitor application, the ESR dominates the impedance at the switching frequency. So the above formula can be approximated as: ΔVOUT VOUT VOUT 1 RESR fS L VIN PCB Layout Guide PCB layout is very important to achieve stable operation. A multi-layer PCB is highly recommended. The high current paths (GND, VIN and SW) should be placed very close to the device with short, direct and wide traces. A RC low pass filter is recommended for VCC supply. The VCC decoupling capacitor must be placed as close to VCC pin and GND pin as possible. The external feedback resistors should be placed next to the FB and FBL pins. Below PCB layout files are our test board for your reference: VOUT V (1- OUT ) VIN VIN The worst-case condition occurs at VIN=2VOUT, where IRMS=ILOAD/2. So, the input capacitor you MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 12 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER Top and Top Silk Layers Inner Layer 2 Inner Layer 1 Bottom Layer Figure 3 ― MP2910DS PCB Layout MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 13 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER PACKAGE INFORMATION SOIC14 0.338(8.55) 0.344(8.75) 0.024(0.61) 8 14 0.063 (1.60) 0.150 (3.80) 0.157 (4.00) PIN 1 ID 0.050(1.27) 0.228 (5.80) 0.244 (6.20) 0.213 (5.40) 7 1 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.050(1.27) BSC 0.013(0.33) 0.020(0.51) 0.004(0.10) 0.010(0.25) SEE DETAIL "A" SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) 0.0075(0.19) 0.0098(0.25) NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AB. 6) DRAWING IS NOT TO SCALE. DETAIL "A" MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 14 MP2910 – 5V/12V SYNCHRONOUS BUCK PWM DC-DC AND LINEAR POWER CONTROLLER SOIC8E (EXPOSED PAD) NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2910 Rev. 1.0 12/14/2011 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2011 MPS. All Rights Reserved. 15