RICHTEK RT9245

RT9245
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
RT9245 is a multi-phase buck DC/DC controller integrated
with all control functions for Intel® GHz CPU which is
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Multi-Phase Power Conversion with Automatic
Phase Selection
VRD10.X-compliant. The RT9245 could be operated with
2, 3 or 4 buck switching stages operating in interleaved
phase set automatically. The multiphase architecture
provides high output current while maintaining low power
dissipation on power devices and low stress on input and
output capacitors. The high equivalent operating frequency
also reduces the component dimension and the output
voltage ripple in load transient.
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6-bits VRD10.x DAC Output with Active Droop
Compensation for Fast Load Transient
Smooth VCORE Transition at VID Jump
Power Stage Thermal Balance by DCR Current
Sense
Hiccup Mode Over-Current Protection
Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and SoftStart
High Ripple Frequency Times Channel Number
28-TSSOP Package
RoHS Compliant and 100% Lead (Pb)-Free
RT9245 implements both voltage and current loops to
achieve good regulation, response and power stage
thermal balance.
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RT9245 applies the DCR sensing technology newly. The
RT9245 extracts the ESR of output inductor as sense
component to deliver a precise load line regulation and
good thermal balance for next generation processor
application.
Current sense setting, droop tuning, VCORE initial offset
and over current protection are independent on
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. The DAC output of RT9245 supports VRD10.x with
6-bit VID input, precise offset value & smooth VCORE
transient at VID jump. The IC monitors the VCORE voltage
for PGOOD and over-voltage protection. Soft-start, overcurrent protection and programmable under-voltage lockout
are also provided to assure the safety of microprocessor
and power system. The RT9245 comes to a small footprint
package TSSOP-28.
Applications
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Intel® Processors Voltage Regulator : VRD10.x
Low Output Voltage, High Current DC-DC Converters
Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
VID4
VID3
VID2
VID1
VID0
VID125
SGND
FB
COMP
PGOOD
DVD
SS
RT
VOSS
Ordering Information
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PWM1
PWM2
PWM3
PWM4
CSP4
CSP2
CSP3
CSP1
GND
ADJ
NC
CSN
IMAX
TSSOP-28
RT9245
Package Type
C : TSSOP-28
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commercial Standard)
Note :
RichTek Pb-free and Green products are :
`RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS9245-06 March 2007
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2
ATX
12V
13
12
11
R8 100k
R7 30k 14
C3
0.1uF
R4 10k
10
9
VOSS
RT
SS
DVD
PGOOD
COMP
26
25
IMAX
C7
0.1uF
C6
0.1uF
15
R21
6.8k
NC
R20 330
18 R19 82
17
0
0
0
0
C5
0.1uF
R13
R12
R11
R10
19 R18 0
20
21
22
23
CSN 16
NC
ADJ
GND
CSP1
CSP3
CSP2
CSP4
PWM4 24
PWM3
PWM2
28
27
R14
C8
0.1uF
R17
10k
R16 10k
R15 10k
10k
C29
0.1uF
VCC
3
2
4
1
3
2
4
1
NC
IN
VCC
BST
NC
IN
C30
0.1uF
PGND
6
DRVL
SW
5
7
RT9603
8
DRVH
5
7
PGND
6
DRVL
SW
5
7
RT9603
8
DRVH
VCC
BST
C24
0.1uF
PGND
6
DRVL
SW
RT9603
8
BST
DRVH
2
IN
3
NC
4
1
Q3
Q4
Q5
Q6
Q7
Q8
IPD06N03LA
R36
0
IPD09N03LA
R35
0
VIN
IPD06N03LA
R32
0
IPD09N03LA
R31
0
VIN
IPD06N03LA
R28
0
IPD09N03LA
R27
0
VIN
L2
1uH
L3
1uH
C34
3.3nF
R37
2.2
1uF
C31
L4
1uH
C33
C32
1000uF 1000uF
C28
3.3nF
R33
2.2
1uF
C25
C27
C26
1000uF 1000uF
C22
3.3nF
R29
2.2
1uF
C19
C47 to C50
10uF x 4
+
C35 to C46
1000uF x 12
+
VOUT
C15
1000uF
C21
C20
1000uF 1000uF
C16
3.3nF
R25
2.2
L1
1uH
+
R34
10 D4
1N4148
ATX
12V
C23
0.1uF
R30
10 D3
1N4148
ATX
12V
C17
0.1uF
R26
10
D2
1N4148
Q2
IPD06N03LA
R24
0
+
R6
2k
R5 9.1k
R3 15k
C2
10nF
33pF
FB
SGND
VID125
VID0
VID1
VID2
PWM1
VCC
5
IPD09N03LA
+
VCC
5V
C1
8
7
6
5
4
3
VID3
VID4
C18
0.1uF
PGND
6
DRVL
7
C13
1uF
C14
1000uF
+
R2 3k
N.C
VID125
R1 0
VID0
VID1
VID2
1
2
ATX
12V
NC
IN
SW
RT9603
8
DRVH
Q1
VIN
+
C4
0.1uF
3
2
VCC
BST
R23
0
C12
1uF
1uH
+
VID3
VID4
RT9245
R9
10
VCC
5V
C9
0.1uF
4
1
C10
0.1uF
C11
1000uF
+
R22
10
D1
1N4148
ATX
12V
ATX
12V
RT9245
Typical Application Circuit
+
+
DS9245-06 March 2007
RT9245
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VID0 (Pin 5) & VID125 (Pin 6)
DAC voltage identification inputs for VRD10.x. These pins
are internally pulled to 1.2V if left open.
IMAX (Pin 15)
Programmable over currert setting.
CSN (Pin 16)
Current sense negative input of all channels.
SGND (Pin 7)
VCORE differential sense negative input.
NC (Pin 17)
No Connection.
FB (Pin 8)
Inverting input of the internal error amplifier.
ADJ (Pin 18)
COMP (Pin 9)
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
Output of the error amplifier and input of the PWM
comparator.
GND (Pin 19)
Ground for the IC.
PGOOD (Pin 10)
Power good open-drain output.
CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4
(Pin 23)
DVD (Pin 11)
Current sense positive inputs for individual converter
channel current sense.
Programmable power UVLO detection input. Trip threshold
= 1.2V at VDVD rising.
SS (Pin 12)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval. Pulling this pin below 1V (ramp
valley of sawtooth wave in pulse width modulator) would
make all PWMs low, turn on low side MOSFETs, and turn
off high side MOSFETs.
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &
PWM4 (Pin 24)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 high.
VCC (Pin 28)
RT (Pin 13)
IC power supply. Connect this pin to a 5V supply.
Switching frequency setting. Connect this pin to GND with
a resistor to set the frequency.
VOSS (Pin 14)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the negative offset value. Connect this pin
to VCC to set positive offset value.
DS9245-06 March 2007
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3
VOSS
Offset Currrent
Source/Sink
FB
Error
Amplifier
COMP
PG Trip
Point
+
-
DAC + Droop
OVP Trip
Point
+
SS
SS
Control
-
DAC
GAP
Amplifier
-
+
ADJ
INH
GND
Power On Reset
-
+
-
+
-
+
-
+
OCP
Setting
Oscillator
&
Sawtooth
SUM/M
Current
Correction
+ +
+ +
+ +
+ +
INH
MUX
PWMCP
INH
PWMCP
INH
PWMCP
INH
PWMCP
-
+
+
-
VID4
VID3
VID2
VID1
VID0
VID125
+
-
RT
+
-
PGOOD VCC DVD
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
PWM Logic
& Driver
MUX
Phase Control
-
+
+
-
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4
IMAX
CSN
CSP4
CSP3
CSP2
CSP1
PWM4
PWM3
PWM2
PWM1
RT9245
Function Block Diagram
DS9245-06 March 2007
RT9245
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID125
1
1
1
1
1
X
No CPU
0
1
0
1
0
0
0.8375V
0
1
0
0
1
1
0.850V
0
1
0
0
1
0
0.8625V
0
1
0
0
0
1
0.875V
0
1
0
0
0
0
0.8875V
0
0
1
1
1
1
0.900V
0
0
1
1
1
0
0.9125V
0
0
1
1
0
1
0.925V
0
0
1
1
0
0
0.9375V
0
0
1
0
1
1
0.950V
0
0
1
0
1
0
0.9625V
0
0
1
0
0
1
0.975V
0
0
1
0
0
0
0.9875V
0
0
0
1
1
1
1.000V
0
0
0
1
1
0
1.0125V
0
0
0
1
0
1
1.025V
0
0
0
1
0
0
1.0375V
0
0
0
0
1
1
1.050V
0
0
0
0
1
0
1.0625V
0
0
0
0
0
1
1.075V
0
0
0
0
0
0
1.0875V
1
1
1
1
0
1
1.100V
1
1
1
1
0
0
1.1125V
1
1
1
0
1
1
1.125V
1
1
1
0
1
0
1.1375V
1
1
1
0
0
1
1.150V
1
1
1
0
0
0
1.1625V
1
1
0
1
1
1
1.175V
1
1
0
1
1
0
1.1875V
1
1
0
1
0
1
1.200V
1
1
0
1
0
0
1.2125V
To be continued
DS9245-06 March 2007
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RT9245
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID125
1
1
0
0
1
1
1.225V
1
1
0
0
1
0
1.2375V
1
1
0
0
0
1
1.250V
1
1
0
0
0
0
1.2625V
1
0
1
1
1
1
1.275V
1
0
1
1
1
0
1.2875V
1
0
1
1
0
1
1.300V
1
0
1
1
0
0
1.3125V
1
0
1
0
1
1
1.325V
1
0
1
0
1
0
1.3375V
1
0
1
0
0
1
1.350V
1
0
1
0
0
0
1.3625V
1
0
0
1
1
1
1.375V
1
0
0
1
1
0
1.3875V
1
0
0
1
0
1
1.400V
1
0
0
1
0
0
1.4125V
1
0
0
0
1
1
1.425V
1
0
0
0
1
0
1.4375V
1
0
0
0
0
1
1.450V
1
0
0
0
0
0
1.4625V
0
1
1
1
1
1
1.475V
0
1
1
1
1
0
1.4875V
0
1
1
1
0
1
1.500V
0
1
1
1
0
0
1.5125V
0
1
1
0
1
1
1.525V
0
1
1
0
1
0
1.5375V
0
1
1
0
0
1
1.550V
0
1
1
0
0
0
1.5625V
0
1
0
1
1
1
1.575V
0
1
0
1
1
0
1.5875V
0
1
0
1
0
1
1.600V
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
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DS9245-06 March 2007
RT9245
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Package Thermal Resistance
TSSOP-28, θJA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
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7V
GND − 0.3V to VCC + 0.3V
100°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V ± 10%
Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C
Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
12
16
mA
4.0
4.2
4.5
V
0.2
0.5
--
V
1.1
1.2
1.3
V
--
50
--
mV
170
200
230
kHz
50
--
400
kHz
--
1.9
--
V
0.7
1.0
--
V
62
66
75
%
RRT = 32kΩ
1.4
1.60
1.8
V
VDAC ≥ 1V
−1
--
+1
%
VDAC < 1V
−10
--
+10
mV
VCC Supply Current
Nominal Supply Current
ICC
PWM 1,2,3,4 Open
POR Threshold
VCCRTH
VCC Rising
Hysteresis
VCCHYS
Power-On Reset
VDVD Threshold
Trip (Low to High)
VDVDTP
Hysteresis
VDVDHYS
Enable
Oscillator
Free Running Frequency
fOSC
Frequency Adjustable Range
fOSC_ADJ
Ramp Amplitude
ΔVOSC
Ramp Valley
VRV
RRT = 32kΩ
RRT = 32kΩ
Maximum On-Time of Each Channel
RT Pin Voltage
VRT
Reference and DAC
DACOUT Voltage Accuracy
ΔVDAC
DAC (VID0-VID125) Input Low
VILDAC
--
--
0.4
V
DAC (VID0-VID125) Input High
VIHDAC
0.8
--
--
V
DAC (VID0-VID125) Bias Current
IBIAS_DAC
25
50
75
μA
VOSS Pin Voltage
VVOSS
1.5
1.65
1.8
V
RVOSS = 100kΩ
To be continued
DS9245-06 March 2007
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7
RT9245
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
--
85
--
dB
--
10
--
MHz
--
3
--
V/μs
100
--
--
μA
150
--
--
μA
8
13
18
μA
130
140
150
%
1.4
1.60
1.8
V
--
--
0.2
V
Error Amplifier
DC Gain
Gain-Bandwidth Product
GBW
Slew Rate
SR
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
IISPFSS
CSN Current for OCP
Protection
SS Current
ISS
Over-Voltage Trip (VSEN/DACOUT)
ΔOVT
IMAX Voltage
VIMAX
RIMAX = 32k
VPGOODL
IPG = 4mA
VSS = 1V
Power Good
Output Low Voltage
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
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DS9245-06 March 2007
RT9245
Typical Operating Characteristics
GM1
GM2
300
300
VADJ
250
200
200
Voltage (mV)
Voltage (mV)
VADJ
250
VP
150
100
VN
50
VP
150
100
VN
50
0
0
0
25
50
75
100
125
150
0
25
50
Vx (mV)
75
100
125
Vx (mV)
GM4
GM3
300
300
VADJ
250
250
200
200
Voltage (mV)
Voltage (mV)
VADJ
VP
150
100
VN
50
VP
150
100
VN
50
0
0
0
25
50
75
100
125
150
0
25
50
Vx (mV)
75
100
125
150
Vx (mV)
Adjustable Frequency
Linearity of each PWM
450
3
400
2.8
350
2.6
2.4
300
V COMP (V)
FOSC (kHz)
150
250
200
150
PWM2
PWM3
PWM1
PWM4
2.2
2
1.8
1.6
100
1.4
50
1.2
0
1
0
25
50
75
100
RRT (kΩ)
(k⎠ )
DS9245-06 March 2007
125
150
175
fOSC = 200k
0
500
1000
1500
2000
2500
3000
3500
Pulse Width (ns)
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RT9245
Load Transient Response
Load Transient Response
V CORE
V CORE
Phase1
Phase
Phase2
CH1:
CH2:
CH3:
CH4:
IOUT
VADJ
(500mV/Div)
(10V/Div)
(50A/Div)
(100mV/Div)
Phase3
CH1: (500mV/Div), CH2: (10V/Div)
CH3: (10V/Div), CH4: (10V/Div)
Time (5μs/Div)
Time (5μs/Div)
Relationship Between Inductor
Current and VADJ
Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
PWM
PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
CH4:(1V/Div)
VADJ
LGATE
CH3:(50mV/Div)
CH4:(20A/Div)
IL
Time (25ms/Div)
VCOMP
Time (10μs/Div)
Power-On @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
VSS
PWM
UGATE
CH3:(20V/Div)
CH4:(10V/Div)
LGATE
Time (10ms/Div)
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DS9245-06 March 2007
RT9245
Application Information
RT9245 is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9245 and its companion MOSFET driver RT9603/
RT9603A provides high quality CPUpower and all
protection functions to meet the requirement of modern
VRM.
Voltage Control
RT9245 senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracy VID DAC provides the reference voltage for
VRD10.X compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of
error amplifier and the error signal is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
Current Balance
RT9245 senses the inductor current via inductor's DCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of single GM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
Load Droop
The sensed power channel current signals regulate the
reference of DAC to form an output voltage droop
proportional to the load current. The droop or so call “active
voltage positioning” can reduce the output voltage ripple
at load transient and the LC filter size.
Fault Detection
The chip detects FB for over voltage and power good
detection. The “hiccup mode” operation of over current
protection is adopted to reduce the short circuit current.
The in-rush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and
output voltage.
Phase Setting and Converter Start Up
RT9245 interfaces with companion MOSFET drivers (like
RT9603, RT9602 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VCC
and DVD trip). The channel is enabled if the pin voltage is
1.2V less than VCC. Tie the PWM to VCC and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Current Sensing Setting
RT9245 senses the current flowing through inductor via
its DCR for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 1).
L
VC
= R × C VC = DCR × IL I X =
DCR
R CSN
L
R
DCR
C
+
-
GMx
RCSN
Ix
Figure 1. Current Sense Circuit
DS9245-06 March 2007
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11
RT9245
Figure 2 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 3 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
L
VCSP
+
VCSN
GMx
Time Sharing of GM
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
PWM3
DCR
ESR
VCSP4
VCSP4
and
V CSN
VX
RCSN
1k
Time (1μs/Div)
Ix
Figure 4
Figure 2. The Test Circuit of GM
Over Current Protection
RT9245 uses an external resistor R IMAX to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT9245 uses hiccup mode to eliminate fault detection of
OCP or reduce output current when output is shorted to
ground.
1 VIMAX
1 IL × DCR
×
⇔
×
2 RIMAX
3 R COMMON
GM
300
250
200
VADJ (mV)
V CSN
150
100
OCP Comparator
50
+
-
0
0
25
50
75
100
125
1/3 IX
1/2 IIMAX
Figure 5. Over Current Comparator
150
Vx (mV)
Over Current Protection
Figure 3. The Linearity of GMx
Figure 4 shows the time sharing technique of GM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
CH1:(5V/Div)
CH2:(5V/Div)
PWM
VSS
Time (25ms/Div)
Figure 6. The Over Current Protection in the soft start
interval
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DS9245-06 March 2007
RT9245
Over Current Protection
CH1:(5V/Div)
CH2:(5V/Div)
PWM
L
= (R1//R2) × C
DCR
Thus if
Then VC =
R2
× DCR × IL
R1+ R2
With internal current balance function, this phase would
share (R 1+R 2)/R 2 times current than other phases.
Figure 9 &10 show different settings for the power stages.
Figure 11 shows the performance of current ratio compared
with conventional current balance function in Figure 12.
VSS
Time (25ms/Div)
Figure 7. Over Current Protection at steady state
Current Ratio Setting
Figure 9. GM4 Setting for current ratio function
Figure 8. Application circuit for current ratio setting
Figure 10. GM1~3 Setting for current ratio function
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
Current Ratio Function
35
channels. Figure 8 shows the application circuit of GM for
current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch :
Look for its corresponding conditions :
dIL
dI
+ DCR × IL = (R1//R2)× C × DCR × L + DCR × IL
dt
dt
L
Let
= (R1//R2)× C
DCR
L
DS9245-06 March 2007
25
I L (A)
dV
dI
V
L L + DCR × IL = R1( C + C C ) + VC
dt
R2
dt
dVC R1 + R 2
VC
= R1C
+
dt
R2
R2
For VC =
DCR × IL
R1 + R 2
IL4
30
20
IL3
IL2
IL1
15
10
5
0
0
15
30
45
60
75
90
I OUT (A)
Figure 11
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RT9245
Current Balance Function
Assume the negative inductor valley current is −5A at no
load, then for
30
IL3
IL4
25
IL1
20
I L (A)
RCSN1 = 330Ω, RADJ = 160Ω, VOUT = 1.300
≥
RCSN2
IL2
15
1.3V
−5A × 1mΩ
330Ω
RCSN2 ≤ 85.8kΩ
10
Choose RCSN2 = 82kΩ
5
Load Line without dead zone at light loads
0
0
20
40
60
80
1.31
100
1.3
I OUT (A)
1.29
L
DCR
ESR
V
+ CSP
VCSN
GMx
V CORE (V)
Figure 12
1.28
1.27
RCSN2 open
1.26
RCSN2 = 82k
1.25
C
RCSN1
1.24
1.23
0
RCSN2
Figure13. Application circuit of GM
For load line design, with application circuit in Figure 13,
it can eliminate the dead zone of load line at light loads.
VCSP = VOUT +IL x DCR
VCSP = VCSN
V
I × DCR
IX = CSN + L
RCSN2
RCSN1
=
RCSN2
VOUT
RCSN2
+
+
IL × DCR
R CSN2
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14
20
25
VID on the Fly
With external pull up resistors tied to VID pins, RT9245
converters different VID codes from CPU into output
voltage. Figure 12 and Figure 13 show the waveforms of
VID on the fly function.
VID on the Fly (Falling)
PWM
V CORE
IL × DCR
VFB
RCSN1
+
IL × DCR
CH3:(500mV/Div)
CH4:(1V/Div)
CH1:(5V/Div)
CH2:(500mV/Div)
RCSN1
For the lack of sinking capability of GM, RCSN2 should be
small enough to compensate the negative inductor valley
current especially at light loads.
VCSN
I × DCR
≥ L
RCSN2
RCSN1
15
Figure 14
if GM holds input voltages equal, then
VOUT + IL × DCR
10
I OUT (A)
Ix
=
5
VID125
VDAC = 1.500, IOUT = 5A
Time (25μs/Div)
Figure 15
DS9245-06 March 2007
RT9245
Voltage Offset Function
VID on the Fly (Rising)
1.284
1.282
PWM
1.28
VFB
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
V CORE (V)
V CORE
1.278
1.276
1.274
1.272
1.27
VID125
VDAC = 1.500, IOUT = 5A
1.268
50
60
70
Time (25μs/Div)
90
100
110
ROSS (kΩ)
(kٛ )
Figure 16
Figure 18
PGOOD Waveform
1/4 IVOSS
RB1
80
CH1:(500mV/Div)
CH2:(5V/Div)
CH3:(5V/Div)
EA
+
VDAC-VADJ
Figure 17
V CORE
PGOOD
Output Voltage Offset Function
To meet Intel's requirement of initial offset of load line,
RT9245 provides programmable initial offset function. With
an external resistor RVOSS and voltage source at VOSS pin
to set offset current IVOSS. One quart of IVOSS flows through
RB1. Error amplifier would hold the inverting pin equal to
VDAC-V ADJ. Thus output voltage is subtracted from
VDAL − VADJ for a constant offset voltage.
PGOOD Function
To indicate the condition of multiphase converter, RT9245
provides PGOOD signal through an open drain connection.
The waveforms of PGOOD function are shown in Figure
15.
VSS
Time (10ms/Div)
Figure 19
VDD
RPGOOD
VPGOOD
Figure 20. PGOOD Test Circuit
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15
RT9245
EA Rising Slew Rate
Error Amplifier Characteristic
For fast response of converter to meet stringent output
current transient response, RT9245 provides large slew
rate capability and high gain-bandwidth performance.
VFB
EA Falling Slew Rate
VFB
CH1:(500mV/Div)
CH2:(2V/Div)
VCOMP
Time (250ns/Div)
VCOMP
CH1:(500mV/Div)
CH2:(2V/Div)
Figure 22. EA Falling Transient with 10pF Loading;
Slew Rate=8V/us
4.7k
Time (250ns/Div)
Figure 21. EA Rising Transient with 10pF Loading; Slew
Rate=10V/us
B 4.7k
EA
+
A
VREF
Figure 23. Gain-Bandwidth Measurement by signal A
divided by signal B
0dB
180°
Figure 24. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
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DS9245-06 March 2007
RT9245
Design Procedure Suggestion
1. Compensation Setting
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
a. Modulator Gain, Pole and Zero:
b.Error amplifier compensation & sawtooth wave amplitude (compensation network).
Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)
c.Kelvin sense for VCORE.
From the following formula:
where VRAMP : ramp amplitude of saw-tooth wave
LC Filter Pole = = 1.45kHz and
Current Loop Setting
ESR Zero =3.98kHz
a.GM amplifier S/H current (current sense component
DCR, CSN pin external resistor value).
b. EA Compensation Network:
b.Over-current protection trip point (RIMAX resistor).
VRM Load Line Setting
a.Droop amplitude (ADJ pin resistor).
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
use the Type 2 compensation scheme shown in Figure
25. By calculation, the FZ = 0.88kHz, FP = 322kHz and
Middle Band Gain is 3.19 (i.e 10.07dB).
b.No load offset (RCSN2)
C2 68pF
c.DAC offset voltage setting (VOSS pin & compen- sation
network resistor RB1).
RB2
RB1
Power Sequence & SS
4.7k
DVD pin external resistor and SS pin capacitor.
PCB Layout
C1
15k 12nF
EA
+
Figure 25. Type 2 compensation network of EA
a.Kelvin sense for current sense GM amplifier input.
b.Refer to layout guide for other items.
The bode plot of EA compensation is shown as Figure 26.
Voltage Loop Setting
The bode plot of power stage is shown as Figure 27. The
total loop gain is in Figure 28.
Design Example
3. Over-Current Protection Setting
Given:
Consider the temperature coefficient of copper
3900ppm/°C,
Apply for four phase converter
VIN = 12V
VCORE = 1.5V
ILOAD (MAX) = 100A
1 VIMAX
×
2 RIMAX
1 1.690V
×
2 RIMAX
⇔
⇔
1 IL × DCR
×
3 R COMMON
1 40A × 1.39m Ω
×
3
330Ω
VDROOP = 100mV at full load (1mΩ Load Line)
OCP trip point set at 40A for each channel (S/H)
Let RIMAX = 14kΩ
DCR = 1mΩ of inductor at 25°C
4. Soft-Start Capacitor Selection
L = 1.5μH
For most application cases, 0.1μF is a good engineering
value.
COUT = 8000μF with 5mΩ equivalent ESR.
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17
RT9245
0dB
-180°
Figure 26. The Frequency Response of the Compensator Network
0dB
-180°
Figure 27. The Frequency Response of Power Stage
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DS9245-06 March 2007
RT9245
0dB
-180°
Figure 28. The Loop Gain of Converter
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
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19
RT9245
L1
SW1
VOUT
VIN
RIN
COUT
CIN
RL
V
L2
SW2
Figure 29. Power Stage Ripple Current Path
Next to IC
+12V
+12V or +5V
0.1uF
VCC
PVCC
BST
CBP
VOSS
LO1
SW
RT9603
+5VIN
VCC
RT
CBOOT
DRVH
IN
PWM
VCORE
COUT
CIN
DRVL
Next to IC
SGND
COMP
CC
RCSN
RT9245
Kelvin
Sense
GND
RC
CSN
Locate next
to FB Pin
FB
RFB
CSPx
Locate near MOSFETs
ADJ
GND
For Thermal Couple
Figure 30. Layout Consideration
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DS9245-06 March 2007
RT9245
Figure 31. Layout of power stage
Test Conditions :
VIN : 12V
VOUT : 1.300V
FSW : 200kHz
IOUT : 80A
Phase Number : 4 Phases
U-MOSFET : IR3707 x 1 (9.5mΩ x 9.6nC)
L-MOSFET : IR8113 x 2 (6.0mΩ x 22nC)
L : 1.5uH
DCR : 1m
CIN : 1000uF x 8
COUT : 1000uF x 8
Snubber : 2R2+3.3nF
Air Speed : Using MAGIC MGA8012HS FAN with 5VDC drive.
P1
P1
P1
P1
P2
P2
P2
P2
Driver
M1
M2
M3
Driver
M4
M5
M6
55°C
58°C
58°C
56°C
56°C
60°C
60°C
60°C
P3
P3
P3
P3
P4
P4
P4
P4
Driver
M7
M8
M9
Driver
M10
M11
M12
55°C
64°C
64°C
65°C
59°C
69°C
66°C
61°C
Note: VIN= 10.835V; IIN = 10.6A; VOUT = 1.2127V; IOUT = 80A; η =84.47%
DS9245-06 March 2007
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21
RT9245
Outline Dimension
D
L
E1
E
e
A2
A
A1
b
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.850
1.200
0.033
0.047
A1
0.050
0.152
0.002
0.006
A2
0.800
1.050
0.031
0.041
b
0.178
0.305
0.007
0.012
D
9.601
9.804
0.378
0.386
e
0.650
0.026
E
6.300
6.500
0.248
0.256
E1
4.293
4.496
0.169
0.177
L
0.450
0.762
0.018
0.030
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: [email protected]
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22
DS9245-06 March 2007