ACTS373MS Radiation Hardened Octal Transparent Latch, Three-State April 1995 Features Pinouts 20 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C TOP VIEW • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD (Si) • Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) OE 1 Q0 2 19 Q7 • SEU LET Threshold >80 MEV-cm2/mg D0 3 18 D7 • Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse D1 4 17 D6 • Latch-Up Free Under Any Conditions Q1 5 16 Q6 • Military Temperature Range: -55oC to +125oC Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 LE • Significant Power Reduction Compared to ALSTTL Logic • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2V Min 20 VCC 20 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C TOP VIEW • Input Current ≤1µA at VOL, VOH Description The Intersil ACTS373MS is a radiation hardened octal transparent latch with three-state outputs. The outputs are transparent to the inputs when the latch enable (LE) is high. When the LE goes low, the data is latched. When the Output Enable (OE) is high, the outputs are in the high impedance state. The latch operation is independent of the state of the output enable. The ACTS373MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 LE GND Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE ACTS373DMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead SBDIP ACTS373KMSR -55oC to +125oC Intersil Class S Equivalent 20 Lead Ceramic Flatpack ACTS373D/Sample +25oC Sample 20 Lead SBDIP ACTS373K/Sample +25oC Sample 20 Lead Ceramic Flatpack ACTS373HMSR +25oC Die Die Truth Table OE L L L L H Functional Diagram LE H H L L X D H L I h X Q H L L H Z NOTE: L = Low Voltage Level X = Don’t Care H = High Voltage Level Z = High Impedance State I = Low voltage level one set-up time prior to the high to low latch enable transition h = High voltage level one set-up time prior to the high to low latch enable transition 1 OF 8 (3, 4, 7, 8, 13, 14, 17, 18) D COMMON CONTROLS OE D Q LE Q (2, 5, 6, 9, 12, 15, 16, 19) LE (11) OE (1) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 LATCH 518800 File Number 4000 Spec Number Specifications ACTS373MS Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±50mA Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (All Voltages Reference to VSS) Thermal Impedance θJA θJC DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72oC/W 24oC/W Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . 107oC/W 28oC/W Maximum Package Power Dissipation at +125oC DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5W Maximum Device Power Dissipation. . . . . . . . . . . . . . . . . . .(TBD)W Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Gates CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. Operating Conditions Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . VCC to VCC/2V Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . 10ns/V Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL ICC Output Current (Source) IOH Output Current (Sink) IOL Output Voltage High VOH Output Voltage Low Input Leakage Current Three-State Output Leakage Current Noise Immunity Functional Test (NOTE 1) CONDITIONS VOL IIN IOZ FN GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 20 µA - 400 µA -12 - mA -8 - mA 12 - mA 8 - mA VCC = 5.5V, VIN = VCC or GND 2, 3 VCC = VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0V, (Note 2) LIMITS +125oC, +25oC 1 2, 3 VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0V, (Note 2) +125oC, -55oC +25oC 1 2, 3 -55oC +125oC, -55oC VCC = 5.5V, VIH = 2.75V VIL = 0.8V, IOH = -50µA 1, 2, 3 +25oC, +125oC, -55oC VCC 0.1 - V VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOH = -50µA 1, 2, 3 +25oC, +125oC, -55oC VCC 0.1 - V VCC = 5.5V, VIH = 2.75V VIL = 0.8V, IOH = 50µA 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOH = 50µA 1, 2, 3 +25oC, +125oC, -55oC - 0.1 V 1 +25oC - ±0.5 µA - ±1.0 µA - ±1 µA - ±35 µA - - V VCC = 5.5V, VIN = VCC or GND 2, 3 VCC = 5.5V, Force Voltage = 0V or VCC VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, (Note 3) +125oC, +25oC 1 2, 3 7, 8A, 8B -55oC +125oC, +25oC, -55oC +125oC, -55oC NOTE: 1. All voltages referenced to device GND. 2. Force/measure functions may be interchanged. 3. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”. Spec Number 2 518800 Specifications ACTS373MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay (NOTES 1, 2) CONDITIONS SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TPZL1 TPLZ1 TPHZ1 TPZH1 GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +25oC 2 19 ns 2 21 ns 2 18 ns 2 20 ns 2 17 ns 2 18 ns VCC = 4.5V, VIH = 3.0V, VIL = 0V 10, 11 VCC = 4.5V, VIH = 3.0V, VIL = 0V 9 10, 11 VCC = 4.5V, VIH = 3.0V, VIL = 0V 9 10, 11 VCC = 4.5V, VIH = 3.0V, VIL = 0V VCC = 4.5V, VIH = 3.0V, VIL = 0V o +25 C o o +125 C, -55 C o +25 C +125 oC, -55oC o +25 C 2 17 ns +125oC, -55oC 2 19 ns 9 +25oC 2 18 ns 2 20 ns 2 18 ns 2 18 ns 2 19 ns 2 20 ns 2 17 ns 2 18 ns 10, 11 9 10, 11 VCC = 4.5V, VIH = 3.0V, VIL = 0V -55oC 9 9 VCC = 4.5V, VIH = 3.0V, VIL = 0V +125oC, 10, 11 10, 11 VCC = 4.5V, VIH = 3.0V, VIL = 0V LIMITS 9 10, 11 o o +125 C, -55 C +25 oC +125oC, -55oC +25oC o o +125 C, -55 C +25 oC +125oC, -55oC NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Capacitance Power Dissipation Input Capacitance Output Capacitance Pulse Width Time Setup Time Hold Time SYMBOL CPD CIN COUT TW TSU TH CONDITIONS VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz NOTE TEMP MIN TYP MAX UNITS 1 +25oC - 17 - pF +125oC - 21 - pF +25oC - - 10 pF +125oC - - 10 pF +25oC - - 20 pF +125oC - - 20 pF +25oC 7 - - ns +125oC 7 - - ns +25oC 5 - - ns +125oC 5 - - ns +25oC 3 - - ns +125oC 3 - - ns 1 VCC = 5.0V, VIH = 5.0V, VIL = 0V, f = 1MHz 1 VCC = 4.5V, VIH = 4.5V, VIL = 0V 1 VCC = 4.5V, VIH = 4.5V, VIL = 0V 1 VCC = 4.5V, VIH = 4.5V, VIL = 0V 1 NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Spec Number 3 518800 Specifications ACTS373MS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS RAD LIMITS PARAMETER (NOTE 1) CONDITIONS SYMBOL TEMP MIN MAX UNITS Supply Current ICC VCC = 5.5V, VIN = VCC or GND +25oC - 400 µA Output Current (Source) IOH VCC = VIH = 4.5V, VOUT = VCC -0.4V, VIL = 0 +25oC -8 - mA Output Current (Sink) IOL VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0 +25oC 8 - mA Output Voltage High VOH VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOH = -50µA +25oC VCC -0.1 - V VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOH = -50µA +25oC VCC -0.1 - V VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOH = 50µA +25oC - 0.1 V VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOH = 50µA +25oC - 0.1 V Output Voltage Low VOL Input Leakage Current IIN VCC = 5.5V, VIN = VCC or GND +25oC - ±1 µA Three-State Output Leakage Current IOZ VCC = 5.5V, Force Voltage = 0V or VCC +25oC - ±35 µA Noise Immunity Functional Test FN VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, (Note 2) +25oC - - V TPHL1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 21 ns TPLH1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 20 ns TPHL2 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 18 ns TPLH2 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 19 ns TPZL1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 20 ns TPLZ1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 18 ns TPHZ1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 20 ns TPZH1 VCC = 4.5V, VIH = 3.0V, VIL = 0V +25oC 2 18 ns Propagation Delay NOTES: 1. All voltages referenced to device GND. 2. For functional tests, VO ≥4.0V is recognized as a logic “1”, and VO ≤0.5V is recognized as a logic “0”. TABLE 5. DELTA PARAMETERS (+25oC) PARAMETER SYMBOL (NOTE 1) DELTA LIMIT UNITS Supply Current ICC ±4.0 µA Three-State Leakage Current IOZ ±200 nA Output Current IOL/IOH ±15 % NOTE: 1. All delta calculations are referenced to 0 hour readings or pre-life readings. Spec Number 4 518800 Specifications ACTS373MS TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP METHOD GROUP A SUBGROUPS Initial Test (Preburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test 1 (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H Interim Test 2 (Postburn-In) 100%/5004 1, 7, 9 ICC, IOL/H, IOZL/H PDA 100%/5004 1, 7, 9, Deltas Interim Test 3 (Postburn-In) 100%/5004 1, 7, 9 PDA 100%/5004 1, 7, 9, Deltas Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample/5005 1, 7, 9 Sample/5005 1, 7, 9 Group A (Note 1) Group B Group D READ AND RECORD ICC, IOL/H, IOZL/H Subgroups 1, 2, 3, 9, 10, 11 NOTE: 1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005. TABLE 7. TOTAL DOSE IRRADIATION TEST CONFORMANCE GROUPS Group E Subgroup 2 READ AND RECORD METHOD PRE RAD POST RAD PRE RAD POST RAD 5005 1, 7, 9 Table 4 1, 9 Table 4 (Note 1) NOTE: 1. Except FN test which will be performed 100% Go/No-Go. TABLE 8. BURN-IN TEST CONNECTIONS (+125oC < TA < 139oC) OSCILLATOR GROUND 1/2 VCC = 3V ±0.5V VCC = 6V ±0.5V 50kHz 25kHz 1, 3, 4, 7, 8, 10, 11, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 20 - - 10 2, 5, 6, 9, 12, 15, 16, 19 1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20 - - 1, 10 2, 5, 6, 9, 12, 15, 16, 19 20 11 3, 4, 7, 8, 13, 14, 17, 18 OPEN STATIC BURN-IN 1 (Note 1) STATIC BURN-IN 2 (Note 1) DYNAMIC BURN-IN (Note 1) NOTE: 1. Each pin except VCC and GND will have a series resistor of 500Ω ±5%. TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25oC, ±5oC) FUNCTION OPEN GROUND VCC = 5V ±0.5V Irradiation Circuit (Note 1) 2, 5, 6, 9, 12, 15, 16, 19 10 1, 3, 4, 7, 8, 11, 13, 14, 17, 18, 20 NOTE: 1. Each pin except VCC and GND will have a series resistor of 47kΩ ±5%. Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures. Spec Number 5 518800 Specifications ACTS373MS Intersil - Space Products MS Screening Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Interim Electrical Test 2 (Note 1) 100% Nondestructive Bond Pull Method 2023 100% Dynamic Burn-In Method 1015, 240 Hours at +125oC or 180 Hours at +135oC 100% Internal Visual Inspection Method 2010 100% Interim Electrical Test 3 (Note 1) 100% Temperature Cycling Method 1010 Condition C (-65o to +150oC) 100% Final Electrical Test 100% Constant Acceleration 100% Radiographics Method 2012 (2 Views) 100% PIND Testing 100% External Visual Method 2009 100% External Visual Inspection Group A (All Tests) Method 5005 (Class S) 100% Serialization Group B (Optional) Method 5005 (Class S) (Note 2) 100% Initial Electrical Test Group D (Optional) Method 5005 (Class S) (Note 2) 100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min CSI and/or GSI (Optional) (Note 2) 100% Interim Electrical Test 1 (Note 1) Data Package Generation (Note 3) 100% Fine and Gross Seal Method 1014 NOTES: 1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined, PDA = 3% for subgroup 7 failures). 2. These steps are optional, and should be listed on the purchase order if required. 3. Data Package Contents: Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity). Certificate of Conformance (as found on shipper). Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number). Variables Data (All Read, Record, and delta operations). Group A Attributes Data Summary. Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage. X-Ray Report and Film, including penetrometer measurements. GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose, Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil. Propagation Delay Timing Diagram and Load Circuit DUT VIH VS TEST POINT RL 500Ω CL 50pF INPUT VSS TPLH TPHL VOH VS OUTPUT AC VOLTAGE LEVELS VOL PARAMETER ACTS UNITS VCC 4.50 V VIH 3.00 V VS 1.30 V VIL 0 V GND 0 V Spec Number 6 518800 Specifications ACTS373MS Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger and AC Load Circuit INPUT VIH DUT TW TEST POINT RL 500Ω CL 50pF VS VIL TSU INPUT CP VIH TH TW PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS VS VIL ACTS 4.50 3.00 1.30 0 0 PARAMETER VCC VIH VS VIL GND TH = HOLD TIME TSU = SETUP TIME TW = PULSE WIDTH UNITS V V V V V Three-State High Timing Diagram and Load Circuit DUT VIH VS INPUT RL 500Ω CL 50pF VSS TPZH TEST POINT TPHZ VOH VT OUTPUT VW VOZ PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER VCC VIH VS VT VW GND ACTS UNITS 4.50 3.00 1.30 1.30 3.60 0 V V V V V V Three-State Low Timing Diagram and Load Circuit VCC VIH VS INPUT RL 500Ω VSS TPZL TPLZ VT OUTPUT TEST POINT DUT VOZ CL 50pF VW VOL PULSE WIDTH, SETUP, HOLD VOLTAGE LEVELS PARAMETER VCC VIH VS VT VW GND ACTS UNITS 4.50 3.00 1.30 1.30 0.90 0 V V V V V V Spec Number 7 518800 ACTS373MS Die Characteristics DIE DIMENSIONS: 102 mils x 102 mils 2,600mm x 2,600mm DIE ATTACH: Material: Silver Glass or JM 7000 after 7/1/95 WORST CASE CURRENT DENSITY: < 2.0 x 105A/cm2 METALLIZATION: Type: AlSiCu Metal 1 Thickness: 6.75kÅ (Min), 8.25kÅ (Max) Metal 2 Thickness: 9kÅ (Min), 11kÅ (Max) BOND PAD SIZE: > 4.3 mils x 4.3 mils > 110µm x 110µm GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ Metallization Mask Layout ACTS373MS D0 (3) Q0 (2) OE (1) VCC (20) Q7 (19) D7 (18) D1 (4) (17) D6 Q1 (5) (16) Q6 NC NC NC NC Q2 (6) (15) Q5 D2 (7) (14) D5 (8) D3 (9) Q3 (10) GND (11) CP (12) Q4 (13) D4 Spec Number 8 518800 ACTS373MS Ceramic Dual-In-Line Metal Seal Packages (SBDIP) -A- D20.3 MIL-STD-1835 CDIP2-T20 (D-8, CONFIGURATION C) 20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE LEAD FINISH c1 -D- BASE METAL E b1 M (b) M -Bbbb S C A - B S INCHES (c) SECTION A-A D S D BASE PLANE S2 Q -C- SEATING PLANE A L S1 eA A A b2 b e ccc M C A - B S D S eA/2 c aaa M C A - B S D S SYMBOL MIN MAX MIN MAX NOTES A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.060 - 26.92 - E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. MILLIMETERS 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. M - 0.0015 - 0.038 2 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. N 20 20 8 Rev. 0 4/94 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. Spec Number 9 518800 ACTS373MS Ceramic Metal Seal Flatpack Packages (Flatpack) K20.A MIL-STD-1835 CDFP4-F20 (F-9A, CONFIGURATION B) 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A e A INCHES PIN NO. 1 ID AREA -A- D -B- S1 b MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - E1 0.004 M H A-B S 0.036 M D S H A-B S D S C Q E -D- A -C- -HL E2 E3 SEATING AND BASE PLANE c1 L E3 (c) b1 M M - 0.540 - 13.72 3 E 0.245 0.300 6.22 7.62 - E1 - 0.330 - 8.38 3 E2 0.130 - 3.30 - - E3 0.030 - 0.76 - 7 e LEAD FINISH BASE METAL D 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 M - 0.0015 - 0.04 - N (b) 0.050 BSC 20 20 SECTION A-A Rev. 0 5/18/94 NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 10 518800