HA5320/883 High Speed Precision Sample and Hold Amplifier July 1994 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Gain, DC . . . . . . . . . . . . . . . . . . . . . . . . 2 x 106 V/V (Typ) The HA-5320/883 was designed for use in precision, high speed data acquisition systems. • Acquisition Time . . . . . . . . . . . . . . . 1.0µs (0.01%) (Typ) • Droop Rate . . . . . . . . . . . . . . . . 0.08µV/µs (+25oC) (Typ) 17µV/µs (Full Temperature) (Typ) • • • • • Aperture Time. . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Typ) Hold Step Error . . . . . . . . . . . . . . . . . . . . . . 1.0mV (Typ) Internal Hold Capacitor Fully Differential Input TTL Compatible Applications • • • • • High Bandwidth Precision Data Acquisition Systems Inertial Navigation and Guidance Systems Ultrasonics SONAR / RADAR Digital to Analog Converter Deglitcher Pinouts HA-5320/883 (CERDIP) TOP VIEW The circuit consists of an input transconductance amplifier capable of providing large amounts of charging current, a low leakage analog switch, and an output integrating amplifier. The analog switch sees virtual ground as its load; therefore, charge injection on the hold capacitor is constant over the entire input/ output voltage range. The pedestal voltage resulting from this charge injection can be adjusted to zero by use of the offset adjust inputs. The device includes a hold capacitor. However, if improved droop rate is required at the expense of acquisition time, additional hold capacitance may be added externally. This monolithic device is manufactured using the Intersil Dielectric Isolation Process, minimizing stray capacitance and eliminating SCR’s. This allows higher speed and latch-free operation. For further information, please see Application Note AN538. Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE -INPUT 1 14 S/H CONTROL +INPUT 2 13 SUPPLY GND HA1-5320/883 -55oC to +125oC 14 Lead CerDIP 12 NC HA4-5320/883 -55oC to +125oC 20 Lead Ceramic LCC OFFSET ADJ 3 OFFSET ADJ 4 11 CEXT V- 5 10 NC SIG GND 6 9 V+ OUTPUT 7 8 INT. BW Functional Diagram OFFSET ADJUST 3 +IN -IN NC S/H CNTL SUPPLY GND HA-5320/883 (CLCC) TOP VIEW 3 2 1 20 19 HA-5320/883 -INPUT 1 4 18 NC NC 5 17 NC OFFSET ADJ 6 16 CEXT NC 7 15 NC V- 8 14 NC - 7 OUTPUT + 13 SUPPLY GND 5 V- 6 SIG GND 8 INTEGRATOR BANDWIDTH 11 CEXT V+ INT. BW 100pF S/H CONTROL 14 9 10 11 12 13 NC 9 +INPUT 2 OFFSET ADJ SIG GND OUTPUT V+ 4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 7-3 Spec Number 511096-883 File Number 2927.3 Specifications HA-5320/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . .+8V, -15V Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . . .±20mA Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Thermal Resistance θJA θJC CerDIP Package . . . . . . . . . . . . . . . . . . . 66oC/W 16oC/W Ceramic LCC Package . . . . . . . . . . . . . . 57oC/W 9oC/W Package Power Dissipation at +75oC CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.75W Package Power Dissipation Derating Factor Above +75oC CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 17mW/oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Temperature Range . . . . . . . . . . . . . -55oC ≤ TA ≤ +125oC Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10V Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic Level High (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 100pF; Signal GND = Supply GND, Unless Otherwise Specified LIMITS PARAMETERS Input Offset Voltage Input Bias Current SYMBOL CONDITIONS VIO +IB -IB Input Offset Current Open Loop Voltage Gain IIO +AVS -AVS Common Mode Rejection Ratio +CMRR -CMRR Output Current +IO -IO RL = 1kΩ, VOUT = +10V RL = 1kΩ, VOUT = -10V V+ = 10V, V- = -20V, VOUT = -5V, VS/H = -4.2V, VGND = -5V V+ = 20V, V- = -10V, VOUT = +5V, VS/H = 5.8V, VGND = +5V VOUT = +10V VOUT = -10V GROUP A SUBGROUP TEMPERATURE MIN MAX UNITS 1 +25oC −1 +1 mV 2, 3 +125oC, -55oC −2 +2 mV 1 +25oC −200 +200 nA 2, 3 +125oC, -55oC −200 +200 nA 1 +25oC −200 +200 nA 2, 3 +125oC, -55oC −200 +200 nA 1 +25oC −100 +100 nA 2, 3 +125oC, -55oC −100 +100 nA 1 +25oC 120 - dB 2, 3 +125oC, -55oC 110 - dB 1 +25oC 120 - dB 2, 3 +125oC, -55oC 110 - dB 1 +25oC 80 - dB 2, 3 +125oC, -55oC 80 - dB 1 +25oC 80 - dB 2, 3 +125oC, -55oC 80 - dB 1 +25oC 10 - mA 2, 3 +125oC, -55oC 10 - mA 1 +25oC -10 - mA 2, 3 +125oC, -55oC -10 - mA CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed. 7-4 Spec Number 511096-883 Specifications HA-5320/883 TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = Internal = 100pF; Signal GND = Supply GND, Unless Otherwise Specified LIMITS PARAMETERS Output Voltage Swing SYMBOL +VOP -VOP Power Supply Current +ICC -ICC Power Supply Rejection Ratio +PSRR -PSRR Digital Input Current IINL IINH Digital Input Voltage CONDITIONS RL = 1kΩ RL = 1kΩ VOUT = 0V, IOUT = 0mA VOUT = 0V, IOUT = 0mA V+ = 14.5V, 15.5V V- = -15V, -15V V+ = +15V, +15V, V- = -14.5V, -15.5V VIN = 0V VIN = 5V VIL VIH Output Voltage Droop Rate VD VOUT = 0V GROUP A SUBGROUP TEMPERATURE MIN MAX UNITS 1 +25oC 10 - V 2, 3 +125oC, -55oC 10 - V 1 +25oC - -10 V 2, 3 +125oC, -55oC - -10 V 1 +25oC - 13 mA 2, 3 +125oC, -55oC - 13 mA 1 +25oC -13 - mA 2, 3 +125oC, -55oC -13 - mA 1 +25oC 80 - dB 2, 3 +125oC, -55oC 80 - dB 1 +25oC 65 - dB 2, 3 +125oC, -55oC 65 - dB 1 +25oC - 4 µA 2, 3 +125oC, -55oC - 10 µA 1 +25oC - 0.1 µA 2, 3 +125oC, -55oC - 0.1 µA 1 +25oC - 0.8 V 2, 3 +125oC, -55oC - 0.8 V 1 +25oC 2.0 - V 2, 3 +125oC, -55oC 2.0 - V 2 +125oC - 100 µV/µs NOTE: 1. Internal power dissipation may limit output current below 20mA. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. See AC Specifications in Table 3. CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed. 7-5 Spec Number 511096-883 Specifications HA-5320/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Hold Mode Feedthrough VHMF Hold Step Error NOTES TEMPERATURE MIN MAX UNITS VIN = 10VP-P , 100kHz 1 +25oC - 3 mV VIH = 3.5V, VIL = 0V, TRISE (VIL to VIH) = 10ns 1 +25oC -11 11 mV EN(SAMPLE) DC to 10MHz, VS/H = 0V, RLOAD = 2kΩ 1 +25oC - 200 µVRMS DC to 10MHz, VS/H = 5V, RLOAD = 2kΩ 1 +25oC - 200 µVRMS VERROR Sample Mode Noise Voltage CONDITIONS Hold Mode Noise Voltage EN(HOLD) Input Capacitance CIN VS/H = 0V 1 +25oC - 5 pF Input Resistance RIN VS/H = 0V, Delta VIN = 20V 1 +25oC 1 - MΩ Slew Rate +SR CL = 50pF, RL = 2kΩ, VOUT = -5V to +5V Step 10%, 90% pts 1 +25oC 30 - V/µs -SR CL = 50pF, RL = 2kΩ, VOUT = +5V to -5V Step 10%, 90% pts 1 +25oC 30 - V/µs TR CL = 50pF, RL = 2kΩ, VOUT = 0V to +200mV Step 10%, 90% pts 1 +25oC - 150 ns TF CL = 50pF, RL = 2kΩ, VOUT = 0V to -200mV Step 10%, 90% pts 1 +25oC - 150 ns +OS CL = 50pF, RL = 2kΩ, VOUT = 0V to +200mV Step 1 +25oC - 25 % -OS CL = 50pF, RL = 2kΩ, VOUT = 0V to -200mV Step 1 +25oC - 25 % CL = 50pF, RL = 2kΩ, VOUT = 0V to 10V Step 1 +25oC - 1.2 µs Rise and Fall Times Overshoot 0.1% Acquisition Time TACQ 0.1% NOTE: 1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1) Interim Electrical Parameters (Pre Burn-In) - Final Electrical Test Parameters 1(Note 1), 2, 3 Group A Test Requirements 1, 2, 3 Groups C and D Endpoints 1 NOTE: 1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA. Spec Number 7-6 511096-883 HA-5320/883 Die Characteristics DIE DIMENSIONS: 92 x 152 x 19 ± 1mils METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ GLASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kÅ ± 2kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ WORST CASE CURRENT DENSITY: 1.742 x 105 A/cm2 TRANSISTOR COUNT: 184 SUBSTRATE POTENTIAL: V- Metallization Mask Layout HA-5320/883 CEXT (11) SUPPLY GND (13) V+ (9) S/H CTRL (14) -INPUT (1) (8) INT BW (7) OUTPUT (6) SIG GND +INPUT (2) (3) (4) (5) VIO ADJ VIO ADJ V- Spec Number 7-7 511096-883 HA-5320/883 Burn-In Circuits HA-5320/883 DIP BURN-IN/LIFE TEST CIRCUIT R1 -V D2 C2 1 14 2 13 3 12 4 11 5 10 6 9 7 8 +V D1 C1 HA-5320/883 LCC BURN-IN/LIFE TEST CIRCUIT R1 3 2 1 20 19 4 18 5 17 6 16 7 15 14 8 -V D2 C2 9 10 11 12 13 +V C1 D1 NOTES: 1. R1 = 100kΩ, 5%, (per socket). 2. C1, C2 = 0.01µF minimum per socket or 0.1µF minimum per row. 3. D1, D2 = 1N4002 or equivalent (per board). 4. +V = +15.5V ±0.5V, -V = -15.5V ± 0.5V. Spec Number 7-8 511096-883 HA-5320/883 Packaging c1 LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE -D- -A- BASE METAL -Bbbb S C A-B S MIN MAX MIN MAX b1 A - 0.200 - 5.08 - M (b) b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 SECTION A-A D S D BASE PLANE Q A -C- SEATING PLANE α L S1 eA A A b2 b ccc M C A-B S e D S eA/2 MILLIMETERS SYMBOL E M INCHES (c) c aaa M C A - B S D S NOTES c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 S2 0.005 - 0.13 - - α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. N NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 14 0.038 14 2 8 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: Inch. 11. Materials: Compliant to MIL-I-38535. Spec Number 7-9 511096-883 HA-5320/883 Packaging (Continued) D J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER D3 j x 45o INCHES E3 B E SYMBOL MIN MAX MIN MAX NOTES A 0.060 0.100 1.52 2.54 6, 7 A1 0.050 0.088 1.27 2.23 7 B - - - - 4 B1 0.022 0.028 0.56 0.71 2, 4 B2 h x 45o A A1 PLANE 2 PLANE 1 e 0.022 0.15 0.56 - 0.342 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC - D2 0.100 BSC 2.54 BSC - D3 - 0.358 - 9.09 2 E 0.342 0.358 8.69 9.09 - E1 0.200 BSC 5.08 BSC - E2 0.100 BSC 2.54 BSC - E3 - h B3 B1 L2 B2 0.358 - 0.050 BSC 0.015 9.09 1.27 BSC - 0.38 0.040 REF 0.020 REF 2 - - 2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 ND E2 - 0.006 j E1 1.83 REF D e1 L3 0.072 REF B3 e L MILLIMETERS 5 0.38 5 3 NE 5 5 3 N 20 20 3 NOTES: L1 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. D2 e1 D1 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.381mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals shall be ellectrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Maximum limits allows for 0.007 inch solder thickness on pads. 8. Materials: Compliant to MIL-I-38535. Spec Number 7-10 511096-883 HA5320 Semiconductor DESIGN INFORMATION High Speed Precision Sample and Hold Amplifier August 1999 The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Applying the HA-5320 The HA-5320 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note 517 for a collection of circuit ideas. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01 to 0.1µF, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13. The ideal ground connections are pin 6 (SIG. Ground) directly to the system Signal Ground, and pin 13 (Supply Ground) directly to the system Supply Common. Hold Capacitor The HA-5320 includes a 100pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 7 and 11. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. If an external hold capacitor CEXT is used, then a noise band- width capacitor of value 0.1CEXT should be connected from pin 8 to ground. Exact value and type are not critical. The hold capacitor CEXT should have high insulation resistance and low dielectric absorption, to minimize droop errors. Polystyrene dielectric is a good choice for operating temperatures up to +85oC. Teflon and glass dielectrics offer good performance to +125oC and above. The hold capacitor terminal (pin 11) remains at virtual ground potential. Any PC connection to this terminal should be kept short and “guarded” by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. Teflon is a registered Trademark of Dupont Corporation. Applications Figure 1 shows the HA-5320 connected as a unity gain noninverting amplifier – its most widely used configuration. As an input device for a fast successive – approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The application may call for an external hold capacitor CEXT as shown. As mentioned earlier, 0.1CEXT is then recommended at pin 8 to reduce output noise in the Hold mode. The HA-5320 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. -15V +15V 10kΩ OFFSET ADJUST ±15mV CEXT 3 4 5 9 11 HI-574A 100pF 1 VIN 2 S/H CONTROL H S 14 - 7 - + + 6 CONVERT 8 0.1CEXT SYSTEM POWER GROUND INPUT DIGITAL OUTPUT HA-5320 13 13 SYSTEM SIGNAL GROUND 5 R/C 9 ANALOG COMMON FIGURE 1. TYPICAL HA-5320/883 CONNECTIONS; NONINVERTING UNITY GAIN MODE NOTE: Pin Numbers Refer to DIP Package Only. Spec Number 7-11 511096-883 HA-5320 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Test Circuits CHARGE TRANSFER AND DRIFT CURRENT 1 7 -INPUT 2 8 +INPUT S/H CONTROL INPUT VO OUTPUT 14 N.C. 11 S/H CONTROL N.C. HA-5320 (CH = 100pF) CHARGE TRANSFER TEST 1. Observe the “hold step” voltage Vp: DRIFT CURRENT TEST 1. Observe the voltage “droop”, ∆VO/∆T: HOLD (+3.5V) S/H CONTROL HOLD (4.0V) S/H CONTROL SAMPLE (0V) SAMPLE (0V) VO ∆VO VO Vp ∆T 2. Compute charge transfer: Q = VpCH 2. Measure the slope of the output during hold, ∆VO /∆T, and compute drift current: ID = CH ∆VO/∆T. HOLD MODE FEED THROUGH ATTENUATION +V VIN ANALOG MUX OR SWITCH HA-5320 9 1 10Vp-p 100kHz SINE WAVE S/H CONTROL INPUT 2 AIN -V 14 5 VOUT -IN +IN OUT 7 S/H CONTROL SUPPLY CEXT GND REF COM INT. COMP. 13 6 8 11 TO SUPPLY COMMON Feedthrough in dB = 20 Log N.C. TO SIGNAL GND N.C. VOUT where: VIN VOUT = Voltsp-p, Hold Mode, VIN = Voltsp-p. Spec Number 7-12 511096-883 HA-5320 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. VSUPPLY = ±15VDC Performance Curves TYPICAL SAMPLE AND HOLD PERFORMANCE AS FUNCTION OF HOLDING CAPACITOR DRIFT CURRENT vs TEMPERATURE ACQUISITION TIME FOR 10V STEP TO +0.01%(µs) 10 5 CH = 100pF, INTERNAL 1000 0.5 IDRIFT (pA) VOLTAGE DROOP DURING HOLD MODE (mV/100ms) 1.0 100 10 0.1 1.0 0.05 SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR (mV) 0.01 100 1000 10K CH VALUE (pF) -25 0 +25 +50 +75 +100 +125 TEMPERATURE (oC) 100K OPEN LOOP GAIN AND PHASE RESPONSE 100 0 80 45 60 90 θ (CH = 100pF) G 40 135 G (CH = 1100pF) 20 PHASE (DEGREES) GAIN (dB) 120 180 0 10 100 1K 10K FREQUENCY (Hz) 100K 1M 10M TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR HOLD STEP vs. INPUT VOLTAGE HOLD STEP vs. LOGIC (VIH) VOLTAGE 2.0 CH = 100pF TA = +25oC -10 -8 -6 -4 1.0 CH = 100pF 0.1 CH = 1000pF 0.01 CH = 0.01µF -2 2 4 6 8 HOLD STEP VOLTAGE (mV) HOLD STEP VOLTAGE (mV) 10 1.5 +75oC 1.0 +25oC 0.5 DC INPUT (V) 0.0 2 3 4 LOGIC LEVEL HIGH (V) Spec Number 7-13 5 511096-883 HA-5320 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Glossary of Terms Acquisition Time See Performance Curves. The time required following a “sample” command, for the output to reach its final value within ±0.1% or ±0.01%. This is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and settling time. Effective Aperture Delay Time (EADT) Charge Transfer The small charge transferred to the holding capacitor from the inter-electrode capacitance of the switch when the unit is switched to the HOLD mode. Charge transfer is directly proportional to sample-to-hold offset pedestal error, where: EADT may be positive, negative or zero. If zero, the S/H amplifier will output a voltage equal to VIN at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of pedestal and droop errors) will correspond to a value of VIN that occurred before the Hold command. Aperture Uncertainty Charge Transfer (pC) = CH (pF) x Offset Error (V) Aperture Time The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier circuitry. The switch opening time is the interval between the conditions of 10% open and 90% open. Hold Step Error Hold Step Error is the output error due to Charge Transfer (see above). It may be calculated from Charge Transfer, using the following relationship: HOLD STEP (V) = The difference between propagation time from the analog input to S/H switch, and digital delay time between the Hold command and opening of the switch. The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data. Drift Current The net leakage current from the hold capacitor during the hold mode. Drift current can be calculated from the droop rate using the formula: ID (pA) = CH (pF) x CHARGE TRANSFER (pC) ∆V (V/s) ∆T HOLD CAPACITANCE (pF) TYPICAL PERFORMANCE CHARACTERISTICS TEMPERATURE TYP UNITS Input Voltage Range PARAMETER Full ±10 V Offset Voltage Drift Full 5 µV/oC Av = +1, VO = 200mVP-P, RL = 2K, CL = 50pF +25oC 2 MHz Gain Bandwidth Product (CH = 1000pF) Av = +1, VO = 200mVP-P, RL = 2K, CL = 50pF +25oC 0.18 MHz Full Power Bandwidth VO = 20VP-P, RL = 2K, CL = 50pF +25oC 600 kHz +25oC 1.0 Ω 0.8 µs Gain Bandwidth Product (CH = 100pF) CONDITIONS Output Resistance (Hold Mode) 0.1% Acquisition Time VO = 10V Step, RL = 2K, CL = 50pF +25oC 0.01% Acquisition Time VO = 10V Step, RL = 2K, CL = 50pF +25oC 1.0 µs Effective Aperture Delay Time +25oC -25 ns Aperture Uncertainty +25oC 0.3 ns 0.01% Hold Mode Settling Time +25oC 165 ns All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 7-14 511096-883