INTERSIL HFA1130883

HFA1130/883
TM
Output Clamping,
850MHz Current Feedback Amplifier
July 1994
Features
Description
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
The HFA1130/883 is a high speed, wideband current feedback amplifier featuring programmable output clamps. Built
with Intersil’ proprietary complementary bipolar UHF-1 process, it is the fastest monolithic amplifier available from any
semiconductor manufacturer.
• User Programmable Output Voltage Clamps
• Low Distortion (HD3, 30MHz) . . . . . . . . . . -84dBc (Typ)
• Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ)
• Very High Slew Rate . . . . . . . . . . . . . . . 2300V/µs (Typ)
• Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 11ns (Typ)
• Excellent Gain Flatness (to 50MHz) . . . . . 0.05dB (Typ)
• High Output Current . . . . . . . . . . . . . . . . . . 65mA (Typ)
• Fast Overdrive Recovery . . . . . . . . . . . . . . . <1ns (Typ)
Applications
• Residue Amplifier
This amplifier is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra
fast overdrive recovery times. The output clamp function
allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The sub-nanosecond overdrive
recovery time quickly returns the amplifier to linear operation
following an overdrive condition.
The HFA1130/883’s wide bandwidth, fast settling characteristic, and low output impedance, coupled with the output
clamping ability, make this amplifier ideal for driving fast A/D
converters.
Component and composite video systems will also benefit
from this amplifier’s performance, as indicated by the excellent gain flatness, and 0.03%/0.05 Degree Differential Gain/
Phase specifications (RL = 75Ω).
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
Ordering Information
• RF/IF Signal Processing
PART NUMBER
• Flash A/D Driver
• Medical Imaging Systems
TEMPERATURE
RANGE
o
o
PACKAGE
HFA1130MJ/883
-55 C to +125 C
8 Lead CerDIP
HFA1130ML/883
-55oC
20 Lead Ceramic LCC
to
+125oC
Pinouts
HFA1130/883
(CLCC)
TOP VIEW
3
6
OUT
V-
4
5
VL
-
+
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
204
NC
4
-IN
5
NC
+IN
3
2
1
20
19
18 VH
17 V+
-
16 NC
NC
6
+IN
7
15 OUT
NC
8
14 NC
+
9
10
11
12
13
NC
V+
NC
7
NC
2
NC
-IN
VL
VH
NC
8
V-
1
NC
NC
NC
HFA1130/883
(CERDIP)
TOP VIEW
Spec Number
511082-883
FN3625.1
Specifications HFA1130/883
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VVoltage at VH or VL Terminal . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . . ±55mA
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . < 2000V
Storage Temperature Range . . . . . . . . . . . . . . -65oC ≤ TA ≤ +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
θJC
Thermal Resistance
θJA
CerDIP Package . . . . . . . . . . . . . . . . . . . 115oC/W
30oC/W
Ceramic LCC Package . . . . . . . . . . . . . .
75oC/W
23oC/W
Maximum Package Power Dissipation at +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W
Package Power Dissipation Derating Factor above +75oC
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC
Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V
Operating Temperature Range. . . . . . . . . . . . .-55oC ≤ TA ≤ +125oC
RL Š≥ 50Ω
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Tested at: V SUPPLY = ±5V, AV = +1, RF = 510Ω, RSOURCE = 0Ω, R L = 100Ω, VOUT = 0V, Unless Otherwise Specified.
PARAMETERS
Input Offset Voltage
SYMBOL
VIO
Common Mode
Rejection Ratio
CMRR
Power Supply
Rejection Ratio
PSRRP
PSRRN
Non-Inverting Input
(+IN) Current
+IN Current Common
Mode Sensitivity
+IN Resistance
Inverting Input (-IN)
Current
IBSP
CMSIBP
+RIN
IBSN
TEMPERATURE
MIN
MAX
1
+25oC
-6
6
mV
2, 3
+125oC, -55oC
-10
10
mV
1
+25oC
40
-
dB
38
-
dB
VCM = 0V
∆VCM = ±2V
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
∆VSUP = ±1.25V
V+ = 6.25V, V- = -5V
V+ = 3.75V, V- = -5V
∆VSUP = ±1.25V
V+ = 5V, V- = -6.25V
V+ = 5V, V- = -3.75V
VCM = 0V
∆VCM = ±2V
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
Note 1
VCM = 0V
CMSIBN
-IN Current Power
Supply Sensitivity
PPSSIBN
NPSSIBN
VOP100
VON100
∆VCM = ±2V
V+ = 3V, V- = -7V
V+ = 7V, V- = -3V
∆VSUP = ±1.25V
V+ = 6.25V, V- = -5V
V+ = 3.75V, V- = -5V
∆VSUP = ±1.25V
V+ = 5V, V- = -6.25V
V+ = 5V, V- = -3.75V
AV = -1
RL =100Ω
AV = -1
RL =100Ω
o
o
UNITS
2, 3
+125 C, -55 C
1
+25oC
45
-
dB
2, 3
+125oC, -55oC
42
-
dB
1
+25oC
45
-
dB
2, 3
+125oC, -55oC
42
-
dB
1
+25oC
-40
40
µA
2, 3
+125oC, -55oC
-65
65
µA
1
+25oC
-
40
µA/V
2, 3
+125oC, -55oC
-
50
µA/V
1
+25oC
25
-
kΩ
2, 3
+125oC, -55oC
20
-
kΩ
1
+25oC
-50
50
µA
oC,
-55oC
-75
75
µA
1
+25oC
-
7
µA/V
2, 3
+125oC, -55oC
-
10
µA/V
1
+25oC
-
15
µA/V
2, 3
+125oC, -55oC
-
27
µA/V
1
+25oC
-
15
µA/V
-
27
µA/V
2, 3
-IN Current Common
Mode Sensitivity
Output Voltage Swing
CONDITIONS
LIMITS
GROUP A
SUBGROUPS
+125
o
o
2, 3
+125 C, -55 C
VIN = 3.5V
1
+25oC
3
-
V
VIN = -3V
2, 3
+125oC, -55oC
2.5
-
V
VIN =+3.5V
1
+25oC
-
-3
V
VIN = +3V
2, 3
+125oC, -55oC
-
-2.5
V
Spec Number
205
511082-883
Specifications HFA1130/883
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Tested at: V SUPPLY = ±5V, AV = +1, RF = 510Ω, RSOURCE = 0Ω, R L = 100Ω, VOUT = 0V, Unless Otherwise Specified.
PARAMETERS
SYMBOL
Output Voltage Swing
VOP50
AV = -1
RL = 50Ω
AV = -1
RL = 50Ω
VON50
Output Current
UNITS
+25oC, +125oC
2.5
-
V
VIN = -2V
3
-55oC
1.5
-
V
VIN = +3V
1, 2
+25oC, +125oC
-
-2.5
V
VIN = +2V
3
-55oC
-
-1.5
V
1, 2
+25oC, +125oC
50
-
mA
mA
o
3
-55 C
30
-
1, 2
+25oC, +125oC
-
-50
mA
3
-55oC
-
-30
mA
1
+25oC
14
26
mA
oC,
2, 3
RL = 100Ω
VHCLMP
AV = -1, VIN = -2V
VH = 1V
VLCLMP
Clamp Input Current
MAX
1, 2
VIN = -3V
RL = 100Ω
ICC
IEE
Clamp Accuracy
MIN
Note 2
-IOUT
Quiescent Power
Supply Current
TEMPERATURE
Note 2
+IOUT
AV = -1, VIN = +2V
VL = -1V
VHBIAS
VH = 1V
VLBIAS
LIMITS
GROUP A
SUBGROUPS
CONDITIONS
VL = -1V
+125
-55oC
-
33
mA
-26
-14
mA
1
+25oC
2, 3
+125oC, -55oC
-33
-
mA
1
+25oC
-125
125
mV
2, 3
+125oC, -55oC
-200
200
mV
1
+25oC
-125
125
mV
2, 3
+125oC, -55oC
-200
200
mV
1
+25oC
-
200
µA
µA
o
o
2, 3
+125 C, -55 C
-
300
1
+25oC
-200
-
µA
2, 3
+125oC, -55oC
-300
-
µA
MIN
MAX
UNITS
NOTES:
1. Guaranteed from +IN Common Mode Rejection Test, by: +RIN = 1/CMSIBP .
2. Guaranteed from VOUT Test with RL = 50Ω, by: IOUT = VOUT/50Ω.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
Table 2 Intentionally Left Blank.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±5V, AV = +2, RF = 360Ω, RL = 100Ω, Unless Otherwise Specified.
LIMITS
PARAMETERS
-3dB Bandwidth
Gain Flatness
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
o
BW(-1)
AV = -1, RF = 430Ω
VOUT = 200mV P-P
1
+25 C
300
-
MHz
BW(+1)
AV = +1, R F = 510Ω
VOUT = 200mV P-P
1
+25oC
550
-
MHz
BW(+2)
AV = +2, VOUT = 200mVP-P
1
+25oC
350
-
MHz
GF30
AV = +2, RF = 510Ω, f ≤
30MHz
VOUT = 200mV P-P
1
+25oC
-
±0.04
dB
GF50
AV = +2, R F = 510Ω, f ≤ 50MHz
VOUT = 200mV P-P
1
+25oC
-
±0.10
dB
GF100
AV = +2, RF = 510Ω, f ≤
100MHz, VOUT = 200mVP-P
1
+25oC
-
±0.30
dB
Spec Number
206
511082-883
Specifications HFA1130/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±5V, AV = +2, RF = 360Ω, RL = 100Ω, Unless Otherwise Specified.
LIMITS
PARAMETERS
SYMBOL
Slew Rate
NOTES
TEMPERATURE
MIN
MAX
UNITS
+SR(+1)
AV = +1, R F = 510Ω
VOUT = 5VP-P
1, 2
+25oC
1200
-
V/µs
-SR(+1)
AV = +1, R F = 510Ω
VOUT = 5VP-P
1, 2
+25oC
1100
-
V/µs
+SR(+2)
AV = +2, VOUT = 5VP-P
1, 2
+25oC
1650
-
V/µs
-SR(+2)
Rise and Fall Time
TR
Overshoot
Settling Time
2nd Harmonic
Distortion
3rd Harmonic
Distortion
CONDITIONS
o
AV = +2, VOUT = 5VP-P
1, 2
+25 C
1500
-
V/µs
AV = +2, VOUT = 0.5VP-P
1, 2
+25oC
-
1
ns
TF
AV = +2, VOUT = 0.5VP-P
1, 2
+25oC
-
1
ns
+OS
AV = +2, VOUT = 0.5VP-P
1, 3
+25oC
-
25
%
-OS
AV = +2, VOUT = 0.5VP-P
1, 3
+25oC
-
20
%
TS(0.1)
AV = +2, RF = 510Ω
VOUT = 2V to 0V, to 0.1%
1
+25oC
-
20
ns
TS(0.05)
AV = +2, R F = 510Ω
VOUT = 2V to 0V, to 0.05%
1
+25oC
-
33
ns
HD2(30)
AV = +2, f = 30MHz
VOUT = 2VP-P
1
+25oC
-
-48
dBc
HD2(50)
AV = +2, f = 50MHz
VOUT = 2VP-P
1
+25oC
-
-45
dBc
HD2(100)
AV = +2, f = 100MHz
VOUT = 2VP-P
1
+25oC
-
-35
dBc
HD3(30)
AV = +2, f = 30MHz
VOUT = 2VP-P
1
+25oC
-
-65
dBc
HD3(50)
AV = +2, f = 50MHz
VOUT = 2VP-P
1
+25oC
-
-60
dBc
HD3(100)
AV = +2, f = 100MHz
VOUT = 2VP-P
1
+25oC
-
-40
dBc
NOTES:
1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization
based upon data from multiple production runs which reflect lot-to-lot and within lot variation.
2. Measured between 10% and 90% points.
3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for A V = +1. Please refer to
Performance Curves.
TABLE 4.
ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS
SUBGROUPS (SEE TABLE 1)
Interim Electrical Parameters (Pre Burn-In)
1
Final Electrical Test Parameters
1 (Note 1), 2, 3
Group A Test Requirements
1, 2, 3
Groups C and D Endpoints
1
NOTE:
1. PDA applies to Subgroup 1 only.
Spec Number
207
511082-883
HFA1130/883
Die Characteristics
DIE DIMENSIONS:
63 x 44 x 19 mils ± 1 mils
1600 x 1130 x 483µm ± 25.4µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ± 0.4kÅ
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ± 0.8kÅ
GLASSIVATION:
Type: Nitride
Thickness: 4kÅ ± 0.5kÅ
WORST CASE CURRENT DENSITY:
2.0 x 105 A/cm2 at 47.5mA
TRANSISTOR COUNT: 52
SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)
Metallization Mask Layout
HFA1130/883
+IN
-IN
V-
BAL
VL
VH
BAL
V+
OUT
Spec Number
208
511082-883
HFA1130/883
Test Circuit (Applies to Table 1)
NC
K3
VL
0.1
50
0.1
V+
+
10
ICC
0.1
510
VIN
K1 NC
0.1
0.1
K2 = POSITION 1:
0.1
VX
VIO =
100
VX
x100
+
-
470pF
VX
50K
5
-
510
2
K2
+IBIAS =
7
2
1
510
4
8
100
100
K5
0.1
100K (0.01%)
10
+
NC
0.1
K4
+
VZ
VOUT
50
200pF
VZ
100K
1K
6
DUT
3 +
K2 = POSITION 2:
-IBIAS =
510
0.1 100
IEE
0.1
0.1
HA-5177
V-
NOTE:
VH
All Resistors = ±1% (Ω)
All Capacitors = ±10% (µF)
Unless Otherwise Noted
Chip Components Recommended
Terminal Numbers Refer to CDIP Package
Test Waveforms
SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3)
AV = +1 TEST CIRCUIT
AV = +2 TEST CIRCUIT
V+
VIN
VOUT
+
-
RS
50Ω
V+
50Ω
RF
VIN
2
RS
50Ω
50Ω
VOUT
+
-
RF
50Ω
360Ω
510Ω
V-
V-
LARGE SIGNAL WAVEFORM
SMALL SIGNAL WAVEFORM
VOUT
VOUT
90%
90%
+SR
-2.5V
RG
360Ω
NOTE: VS = ±5V, AV = +2
RS = 50Ω
RL=100Ω For Small and Large Signals
NOTE: VS = ±5V, AV = +1
RS = 50Ω
RL = 100Ω For Small and Large Signals
+2.5V
2
50Ω
+2.5V
+250mV
-SR
10%
10%
90%
90%
TF , -OS
TR , +OS
-2.5V
-250mV
10%
10%
Spec Number
209
+250mV
-250mV
511082-883
HFA1130/883
Burn-In Circuits
HFA1130MJ/883 CERAMIC DIP
R3
1
R2
8
2
R1
+
3
D4
6
4
VD2
D3
V+
7
-
C1
D1
5
C2
NOTES:
R1 = R2 = 1kΩ, ±5% (Per Socket)
R3 = 10kΩ, ±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ± 0.5V
V- = -5.5V ± 0.5V
HFA1130ML/883 CERAMIC LCC
R3
3
2
1 20 19
18
4
R2
5
6
R1
16
+
7
D3
17
-
V+
C1
D1
15
14
8
9 10 11 12 13
D4
VD2
C2
NOTES:
R1 = R2 = 1kΩ, ±5% (Per Socket)
R3 = 10kΩ, ±5% (Per Socket)
C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
D1 = D2 = 1N4002 or Equivalent (Per Board)
D3 = D4 = 1N4002 or Equivalent (Per Socket)
V+ = +5.5V ± 0.5V
V- = -5.5V ± 0.5V
Spec Number
210
511082-883
HFA1130/883
Packaging
BASE
METAL
E
M
-BC A-B S
(c)
-C-
SEATING
PLANE
Q
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
M
(b)
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.405
-
10.29
5
E
0.220
0.310
5.59
7.87
5
A
L
S1
α
eA
A A
b2
e
b
C A-B S
D S
eA/2
MILLIMETERS
SYMBOL
SECTION A-A
D S
INCHES
b1
D
BASE
PLANE
ccc M
MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)
8 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE
-D-
-A-
bbb S
F8.3A
LEAD FINISH
c1
c
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
S2
0.005
-
0.13
-
-
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
N
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
NOTES
8
8
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b1.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling Dimension: Inch
11. Lead Finish: Type A.
12. Materials: Compliant to MIL-I-38535.
Spec Number
211
511082-883
HFA1130/883
Packaging (Continued)
D
J20.A
MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER
D3
j x 45o
INCHES
E3
B
h x 45
E
MIN
MAX
MIN
MAX
NOTES
A
0.060
0.100
1.52
2.54
6, 7
A1
0.050
0.088
1.27
2.23
7
B
-
-
-
-
4
B1
0.022
0.028
0.56
0.71
2, 4
B2
o
A
A1
e
0.15
0.56
-
D
0.342
0.358
8.69
9.09
-
D1
0.200 BSC
5.08 BSC
-
D2
0.100 BSC
2.54 BSC
-
D3
-
0.358
-
9.09
2
E
0.342
0.358
8.69
9.09
-
E1
0.200 BSC
5.08 BSC
E2
0.100 BSC
2.54 BSC
PLANE 1
e1
B3
E1
-
0.022
PLANE 2
B1
1.83 REF
0.006
E3
L3
0.072 REF
B3
e
L
MILLIMETERS
SYMBOL
-
0.358
-
0.050 BSC
0.015
-
9.09
1.27 BSC
-
0.38
2
-
-
2
h
0.040 REF
1.02 REF
5
j
0.020 REF
0.51 REF
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.90
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
5
5
NE
5
5
3
3
N
20
20
3
NOTES:
E2
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
L2
B2
L1
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.381mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
D2
e1
D1
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals
shall be ellectrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Maximum limits allows for 0.007 inch solder thickness on pads.
8. Lead Finish: Type A.
9. Materials: Compliant to MIL-I-38535.
Spec Number
212
511082-883
HFA1130
TM
DESIGN INFORMATION
Output Clamping, Ultra High Speed
Current Feedback Amplifier
February 2002
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
SMALL SIGNAL PULSE RESPONSE
LARGE SIGNAL PULSE RESPONSE
AV = +2
120
90
0.9
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
A V = +2
1.2
60
30
0
-30
-60
0.6
0.3
0
-0.3
-0.6
-90
-0.9
-120
-1.2
5ns/DIV
5ns/DIV
UNCLAMPED PERFORMANCE
CLAMPED PERFORMANCE
IN
0V TO 0.5V
IN
0V TO 1V
OUT
0V TO 1V
OUT
0V TO 1V
AV = +2, VH = 2V, VL = -2V
AV = +2, VH = 1V, VL = -1V, 2X OVERDRIVE
10ns/DIV
10ns/DIV
Spec Number
213
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
NON-INVERTING FREQUENCY RESPONSE
AV = +2
AV = +6
AV = +11
-12
PHASE
0
0.3
1
AV = +1
-90
AV = +2
-180
AV = +6
AV = +11
-270
-12
0.3
PHASE
RL = 50Ω
RL = 100Ω
0
-90
RL = 1kΩ
-180
RL = 100Ω
RL = 1kΩ
0.3
1
GAIN (dB) NORMALIZED
RL = 50Ω
-6
10
100
FREQUENCY (MHz)
AV = +1
-360
1K
GAIN (dB) NORMALIZED
1.63VP-P
1
-90
-180
1K
10
100
FREQUENCY (MHz)
10
100
FREQUENCY (MHz)
RL = 1kΩ
GAIN
0
-3
RL = 100Ω
-6
PHASE
RL = 50Ω
0
RL = 50Ω
RL = 100Ω
+20
0.160VP-P
-30
0.3
0
-90
RL = 1kΩ
RL = 100Ω
-180
-270
1
-360
1K
10
100
FREQUENCY (MHz)
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
0.920VP-P
-20
+3
0.3
0.500VP-P
-10
AV = -5
RL = 1kΩ
+10
0
1
-270
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
+20
90
FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
PHASE (DEGREES)
GAIN (dB)
RL = 100Ω
-3
AV = -1
AV = +2, VOUT = 200mVP-P
GAIN
0
180
AV = -20
RL = 1kΩ
+3
AV = -20
PHASE
AV = +1, VOUT = 200mVP-P
+6
AV = -10
AV = -10
FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
GAIN (dB)
VOUT = 200mVP-P
-9
-360
1K
10
100
FREQUENCY (MHz)
AV = -5
-6
PHASE (DEGREES)
VOUT = 200mVP-P
AV = -1
-3
PHASE (DEGREES)
-6
GAIN (dB) NORMALIZED
AV = +1
PHASE (DEGREES)
-3
-9
GAIN
0
GAIN
0
GAIN (dB) NORMALIZED
INVERTING FREQUENCY RESPONSE
+10
0
0.32VP-P
1.00VP-P
-10
1.84VP-P
-20
3.26VP-P
-30
0.3
1K
AV = +2
1
10
100
FREQUENCY (MHz)
Spec Number
214
1K
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES
AV = +1
AV = +6
+20
+10
950
BANDWIDTH (MHz)
GAIN (dB) NORMALIZED
-3dB BANDWIDTH vs TEMPERATURE
0
0.96VP-P
TO
3.89VP-P
-10
-20
-30
900
850
800
750
700
0.3
1
10
100
FREQUENCY (MHz)
-50
1K
-25
0
+25
+50
+75 +100 +125
TEMPERATURE (oC)
GAIN FLATNESS
DEVIATION FROM LINEAR PHASE
AV = +2
+2.0
AV = +2
DEVIATION (DEGREES)
+1.5
GAIN (dB)
0
-0.05
-0.10
-0.15
-0.20
+1.0
+0.5
0
-0.5
-1.0
-1.5
-2.0
1
10
FREQUENCY (MHz)
0
100
SETTLING RESPONSE
15
30
45 60 75 90 105 120 135 150
FREQUENCY (MHz)
3rd ORDER INTERMODULATION INTERCEPT
40
2-TONE
35
0.6
INTERCEPT POINT (dBm)
SETTLING ERROR (%)
AV = +2, VOUT = 2V
0.4
0.2
0
-0.2
-0.4
-0.6
30
25
20
15
10
5
0
-4
1
6
11
16 21 26
TIME (ns)
31
36
41
46
0
100
200
300
FREQUENCY (MHz)
Spec Number
215
400
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
3rd HARMONIC DISTORTION vs POUT
-30
-35
-40
100MHz
-40
DISTORTION (dBc)
DISTORTION (dBc)
2nd HARMONIC DISTORTION vs POUT
-30
-45
50MHz
-50
-55
-60
30MHz
-65
-70
-5
-3
-1
1
3
-50
100MHz
-60
-70
50MHz
-80
-90
30MHz
-100
5
7
9
11
13
-110
15
-5
-3
-1
OUTPUT POWER (dBm)
7
9
11
RF = 360Ω
VOUT = 2VP-P
30
VOUT = 1VP-P
VOUT = 0.5VP-P
VOUT = 2VP-P
25
RF = 360Ω
20
13
15
10
0
100 200 300 400 500 600 700 800 900 1000
INPUT RISE TIME (ps)
VOUT = 0.5VP-P
AV = +2
RF = 360Ω
VOUT = 1VP-P
15
5
RF = 510Ω
VOUT = 2VP-P
RF =510Ω
VOUT = 1VP-P
VOUT = 0.5VP-P
RF = 510Ω
100 200 300 400 500 600 700 800 900 1000
INPUT RISE TIME (ps)
SUPPLY CURRENT vs TEMPERATURE
25
AV = +2, tR = 200ps, VOUT = 2VP-P
24
SUPPLY CURRENT (mA)
OVERSHOOT (%)
5
35
AV = +1
OVERSHOOT vs FEEDBACK RESISTOR
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
3
OVERSHOOT vs INPUT RISE TIME
OVERSHOOT (%)
OVERSHOOT (%)
OVERSHOOT vs INPUT RISE TIME
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
1
OUTPUT POWER (dBm)
23
22
21
20
19
360
400
440 480 520 560 600
FEEDBACK RESISTOR (Ω)
640
18
680
-60
-40
-20
0 +20 +40 +60 +80 +100 +120
TEMPERATURE (o C)
Spec Number
216
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Typical Performance Curves
VSUPPLY = ±5V, RF = 510Ω, TA = +25oC, RL = 100Ω, Unless Otherwise Specified.
(Continued)
6
7
8
9
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
10
+IBIAS
VIO
-IBIAS
-60 -40 -20
OUTPUT VOLTAGE vs TEMPERATURE
300
275
3.4
NOISE VOLTAGE (nV/√Hz)
+VOUT
3.3
| - VOUT |
3.1
3.0
2.9
2.8
2.7
25
250
225
20
200
175
15
150
125
100
10
75
5
ENI
INIINI+
2.6
2.5
-60 -40 -20
0
100
0 +20 +40 +60 +80 +100 +120
1K
TEMPERATURE (oC)
10K
100K
50
25
0
FREQUENCY (Hz)
NON-LINEARITY NEAR CLAMP VOLTAGE
20
15
VOUT - (AV * VIN) (mV)
OUTPUT VOLTAGE (V)
30
AV = -1, RL = 50Ω
3.5
3.2
0 +20 +40 +60 +80 +100+120
TEMPERATURE (oC)
INPUT NOISE vs FREQUENCY
3.7
3.6
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
NOISE CURRENT (pA/√Hz)
5
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
BIAS CURRENTS (µA)
VIO AND BIAS CURRENTS vs TEMPERATURE
INPUT OFFSET VOLTAGE (mV)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs SUPPLY VOLTAGE
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
VL = -3V VL = -2V VL = -1V
AV = -1, R L = 100Ω
10
5
0
VH = 1V
-5
VH = 2V VH = 3V
-10
-15
-20
-3
-2
-1
0
1
2
3
AV * VIN (V)
Spec Number
217
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Application Information
recommended that the ground plane be removed under
traces connected to -IN, and connections to -IN should be
kept as short as possible.
Optimum Feedback Resistor
The enclosed plots of inverting and non-inverting frequency
response illustrate the performance of the HFA1130 in
various gains. Although the bandwidth dependency on
closed loop gain isn’t as severe as that of a voltage feedback
amplifier, there can be an appreciable decrease in
bandwidth at higher gains. This decrease may be minimized
by taking advantage of the current feedback amplifier’s
unique relationship between bandwidth and RF . All current
feedback amplifiers require a feedback resistor, even for
unity gain applications, and RF , in conjunction with the
internal compensation capacitor, sets the dominant pole of
the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF . The HFA1130 design is
optimized for a 510Ω RF at a gain of +1. Decreasing RF in a
unity gain application decreases stability, resulting in
excessive peaking and overshoot. At higher gains the
amplifier is more stable, so RF can be decreased in a tradeoff of stability for bandwidth.
The table below lists recommended R F values for various
gains, and the expected bandwidth.
RF (Ω)
BANDWIDTH
(MHz)
-1
430
580
+1
510
850
+2
360
670
+5
150
520
+10
180
240
+19
270
125
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and C L combinations for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of
850MHz. By decreasing RS as CL increases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to the right along the curve. For example, at
AV = +1, RS = 50Ω, CL = 30pF, the overall bandwidth is limited to 300MHz, and bandwidth drops to 100MHz at AV = +1,
RS = 5Ω, CL = 340pF.
50
45
40
AV = +1
35
RS (Ω)
GAIN
(ACL )
An example of a good high frequency layout is the Evaluation Board shown in Figure 2.
30
PC Board Layout
25
20
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
15
10
5 A = +2
V
0
0
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. To this end, it is
40
80
120
160
200
240
280
320
360 400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1130 may be evaluated using
the HFA11XX Evaluation Board.
The layout and schematic of the board are shown in Figure
2. To order evaluation boards, please contact your local
sales office.
Spec Number
218
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
V+
TOP LAYOUT
QP3
QP4
VH
QN2
1
QP1
+IN
+IN
OUT V+
VL VGND
R1
Z
ICLAMP
VV+
+1
VH
QN1
QN5
QP2
BOTTOM LAYOUT
50K
(30K
FOR VL)
QN6
QP6
QN3
QN4
QP5
V-
-IN
RF
(EXTERNAL)
VOUT
FIGURE 3. HFA1130 SIMPLIFIED VH CLAMP CIRCUITRY
Clamp Circuitry
500
500
VH
R1
50Ω
IN
10µF
0.1µF
Figure 3 shows a simplified schematic of the HFA1130 input
stage, and the high clamp (VH) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (QX1 - QX2)
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
1
8
2
7
3
6
4
5
-5V
GND
(V-IN - V OUT)/ RF + V-IN / RG
10µF
0.1µF
where RG is the gain setting resistor from -IN to GND. This
current is mirrored onto the high impedance node (Z) by
QX3 - QX4, where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
by QP4 and QN4. Note that when the output reaches it’s quiescent value, the current flowing through -IN is reduced to
only that small current (-IBIAS) required to keep the output at
the final voltage.
+5V
50Ω
OUT
GND
VL
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
Clamp Operation
General
The HFA1130 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
by applying voltages to the VH and VL terminals (DIP pins 8
and 5) of the amplifier. VH sets the upper output limit, while
VL sets the lower clamp level. If the amplifier tries to drive
the output above VH, or below V L, the clamp circuitry limits
the output voltage at VH or V L (± the clamp accuracy),
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
Tracing the path from V H to Z illustrates the effect of the
clamp voltage on the high impedance node. VH decreases
by 2V BE (QN6 and QP6) to set up the base voltage on QP5.
QP5 begins to conduct whenever the high impedance node
reaches a voltage equal to QP5’s base voltage + 2VBE (QP5
and QN5). Thus, QP5 clamps node Z whenever Z reaches
VH . R1 provides a pull-up network to ensure functionality
with the clamp inputs floating. A similar description applies to
the symmetrical low clamp circuitry controlled by V L.
Spec Number
219
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
When the output is clamped, the negative input continues to
source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must
sink this current while clamping, because the -IN current is
always mirrored onto the high impedance node. The clamping
current is calculated as:
ICLAMP = (V-IN - VOUT CLAMPED) / RF + V-IN / RG.
As an example, a unity gain circuit with VIN = 2V, VH = 1V, and
RF = 510Ω would have ICLAMP = (2V - 1V) / 510Ω + 2V / ∞ =
1.96mA. Note that Icc will increase by ICLAMP when the output
is clamp limited.
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
voltage applied to VH or VL Offset errors, mostly due to VBE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to Figure
3, it can be seen that one component of clamp accuracy is the
VBE mismatch between the QX6 transistors, and the QX5
transistors. If the transistors always ran at the same current
level there would be no VBE mismatch, and no contribution to
the inaccuracy. The QX6 transistors are biased at a constant
current, but as described earlier, the current through QX5 is
equivalent to ICLAMP . VBE increases as ICLAMP increases,
causing the clamped output voltage to increase as well.
ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT
CLAMPED) and RF , so clamp accuracy degrades as the overdrive increases, and as RF decreases. As an example, the
specified accuracy of ±60mV for a 2X overdrive with
RF = 510Ω degrades to ±220mV for RF = 240Ω at the same
overdrive, or to ±±250mV for a 3X overdrive with RF = 510Ω.
Clamp Range
Unlike some competitor devices, both VH and VL have usable
ranges that cross 0V. While VH must be more positive than
VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the
HFA1130 could be limited to ECL output levels by setting VH
= -0.8V and VL = -1.8V. VH and VL may be connected to the
same voltage (GND for instance) but the result won’t be in a
DC output voltage from an AC input signal. A 150mV - 200mV
AC signal will still be present at the output.
Recovery from Overdrive
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
below the overdrive level (VCLAMP / AVCL) the amplifier will
return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear
operation. The plots of “Unclamped Performance” and
“Clamped Performance” highlight the HFA1130’s subnanosecond recovery time. The difference between the
unclamped and clamped propagation delays is the overdrive
recovery time. The appropriate propagation delays are 4.0ns
for the unclamped pulse, and 4.8ns for the clamped (2X
overdrive) pulse yielding an overdrive recovery time of
800ps. The measurement uses the 90% point of the output
transition to ensure that linear operation has resumed. Note:
The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1130
propagation delay is 500ps.
Consideration must also be given to the fact that the clamp
voltages have an effect on amplifier linearity. The “Nonlinearity Near Clamp Voltage” curve in the data sheet illustrates the
impact of several clamp levels on linearity.
Spec Number
220
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS
Device Characterized at: VSUPPLY = ±5V, RF = 360Ω, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified
PARAMETERS
CONDITIONS
TEMPERATURE
TYPICAL
UNITS
+25oC
2
mV
Full
10
µV/oC
∆VCM = ±2V
+25oC
46
dB
VIO PSRR
∆VS = ±1.25V
+25oC
50
dB
+Input Current *
VCM = 0V
+25oC
25
µA
Full
40
nA/oC
Input Offset Voltage *
VCM = 0V
Average Offset Voltage Drift
Versus Temperature
VIO CMRR
Average +Input Current Drift Versus Temperature
-Input Current *
VCM = 0V
Average -Input Current Drift
Versus Temperature
+Input Resistance
∆VCM = ±2V
-Input Resistance
+25oC
12
µA
Full
40
nA/oC
+25oC
50
kΩ
+25oC
16
Ω
o
+25 C
2.2
pF
Input Noise Voltage *
f = 100kHz
+25oC
4
nV/√Hz
+Input Noise Current *
f = 100kHz
+25oC
18
pA/√Hz
+25 C
21
pA/√Hz
Full
±3.0
V
500
kΩ
Input Capacitance
-Input Noise Current *
o
f = 100kHz
Input Common Mode Range
Open Loop
Transimpedance
AV = -1
+25oC
Output Voltage
AV = -1, RL = 100Ω
+25oC
±3.3
V
AV = -1, RL = 100Ω
Full
±3.0
V
±65
mA
±50
mA
0.1
Ω
Full
24
mA
AV = -1, RF = 430Ω, VOUT = 200mV P-P
+25oC
580
MHz
AV = +1, RF = 510Ω, VOUT = 200mVP-P
+25oC
850
MHz
Output Current *
+25oC
AV = -1, RL = 50Ω
-55oC to 0oC
AV = -1, RL = 50Ω
DC Closed Loop Output
Resistance
Quiescent Supply Current *
-3dB Bandwidth *
Slew Rate
Full Power Bandwidth
Gain Flatness *
to
+125oC
+25
RL = Open
oC
o
AV = +2, RF = 360Ω, VOUT = 200mVP-P
+25 C
670
MHz
AV = +1, RF = 510Ω, VOUT = 5VP-P
+25oC
1500
V/µs
AV = +2, VOUT = 5VP-P
+25oC
2300
V/µs
VOUT = 5VP-P
+25oC
220
MHz
o
To 30MHz, RF = 510Ω
+25 C
±0.014
dB
To 50MHz, RF = 510Ω
+25oC
±0.05
dB
To 100MHz, RF = 510Ω
+25oC
±0.14
dB
o
Linear Phase Deviation *
To 100MHz, RF = 510Ω
+25 C
±0.6
Degrees
2nd Harmonic Distortion *
30MHz, VOUT = 2VP-P
+25oC
-55
dBc
3rd Harmonic Distortion *
o
50MHz, VOUT = 2V P-P
+25 C
-49
dBc
100MHz, VOUT = 2VP-P
+25oC
-44
dBc
30MHz, VOUT = 2VP-P
+25oC
-84
dBc
50MHz, VOUT = 2VP-P
+25oC
-70
dBc
100MHz, VOUT = 2VP-P
+25oC
-57
dBc
Spec Number
221
511082-883
HFA1130
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Device Characterized at: VSUPPLY = ±5V, RF = 360Ω, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified
PARAMETERS
TEMPERATURE
TYPICAL
UNITS
100MHz, RF = 510Ω
CONDITIONS
+25oC
30
dBm
1dB Compression
100MHz, RF = 510Ω
+25oC
20
dBm
Reverse Isolation (S12)
40MHz, RF = 510Ω
+25oC
-70
dB
3rd Order Intercept *
Rise & Fall Time
Overshoot *
Settling Time *
Differential Gain
o
100MHz, RF = 510Ω
+25 C
-60
dB
600MHz, RF = 510Ω
+25oC
-32
dB
VOUT = 0.5VP-P
+25oC
500
ps
VOUT = 2VP-P
+25oC
800
ps
VOUT = 0.5VP-P, Input tR/tF = 550ps
+25oC
11
%
o
To 0.1%, VOUT = 2V to 0V, RF = 510Ω
+25 C
11
ns
To 0.05%, VOUT = 2V to 0V, R F = 510Ω
+25oC
19
ns
To 0.02%, VOUT = 2V to 0V, R F = 510Ω
+25oC
34
ns
AV = +2, RL = 75Ω, NTSC
+25oC
0.03
%
o
Differential Phase
AV = +2, RL = 75Ω, NTSC
+25 C
0.05
Degrees
Overdrive Recovery Time
(2X Overdrive)
RF = 510Ω, VIN = ±1V, VH = +1V, VL = -1V
+25oC
750
ps
Clamp Accuracy
AV = -1, RF = 510Ω, VIN = ±2V, VH = +1V,
VL = -1V
+25oC
±60
mV
Clamped Overshoot
RF = 510Ω, VIN = ±1V, VH = +1V, VL = -1V,
Input tR / tF = 2ns
+25oC
4
%
Negative Clamp Range (VL)
RF = 510Ω
+25oC
-5.0 to +2.0
V
Positive Clamp Range (VH)
RF = 510Ω
+25oC
-2.0 to +5.0
V
Clamp Input Bias Current
VH = +1V, VL = -1V
+25oC
50
µA
Clamp Input Bandwidth
VIN = ±100mV, VH or VL = 100mVP-P
+25oC
500
MHz
*See Typical Performance Curves For More Information
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Spec Number
222
511082-883