Programmable VCOM Calibrator with EEPROM and Output Buffer ISL24211 Features The ISL24211 is an 8-bit programmable current sink that can be used in conjunction with an external voltage divider to generate a voltage source (VCOM) positioned between the analog supply voltage and ground. The current sink’s full-scale range is controlled by an external resistor, RSET. With the appropriate choice of external resistors R1 and R2, the VCOM voltage range can be controlled between any arbitrary voltage range. The ISL24211 has an 8-bit data register and 8-bit EEPROM for storing both a volatile and a permanent value for its output, with an I2C interface to read and write to the register and EEPROM. After the part is programmed, the I2C interface is no longer needed; on power-up the EEPROM contents are automatically transferred to the data register, and the pre-programmed output voltage appears on the VCOM_OUT pin. • 8-bit, 256-Step, Adjustable Sink Current Output • 60MHz VCOM Buffer/Amplifier • 4.5V to 19.0V Analog Supply Range for Normal Operation (10.8V Minimum Analog Supply Voltage for Programming) • 2.25V to 3.6V Logic Supply Voltage Operating Range • 400kHz, I2C Interface • On-Chip 8-Bit EEPROM • Guaranteed Monotonic Over-Temperature • Compatible with applications using the 7-bit ISL45041 • Pb-free (RoHS-compliant) • Ultra-Thin 10 Ld TDFN (3 x 3 x 0.8mm max) The ISL24211 also features an integrated, wide-bandwidth, high output drive buffer amplifier that can directly drive the VCOM input of an LCD panel. Applications The ISL24211 is available in an 10 Ld 3mm x 3mm TDFN package. This package has a maximum height of 0.8mm for very low profile designs. The ambient operating temperature range is -40°C to +85°C. • Electrophoretic Display VCOM Generator • LCD Panel VCOM Generator Related Literature • AN1627 “ISL24211IRTZ-EVALZ Evaluation Board User Guide” Typical Application 3.3V VDD 6 AVDD 3 R1 7 MICROCONTROLLER I2C PORT DVR_OUT SDA 1 8 SCL I/O PIN 4 2 ISL24211 R2 INN LCD PANEL 10 VCOM VCOM_OUT WP SET 9 RSET 5 FIGURE 1. TYPICAL ISL24211 APPLICATION February 23, 2011 FN7585.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL24211 Block Diagram AVDD VDD 3 6 SDA SCL WP 7 8 VCOM BUFFER AMPLIFER ANALOG DCP AND CURRENT SINK DAC REGISTERS I2C INTERFACE 2 Q1 10 A2 DVR_OUT VCOM_OUT A1 4 1 8-Bit EEPROM INN CS 9 SET 5 GND FIGURE 2. BLOCK DIAGRAM OF THE ISL24211 Pin Descriptions Pin Configuration ISL24211 (10 LD TDFN) TOP VIEW AVDD 3 PIN NUMBER INN 1 Negative (inverting) input of the VCOM buffer op amp. This pin is used to provide feedback from the end point of the VCOM trace. DVR_OUT 2 Adjustable Sink Current Output Pin. The current sunk into the DVR_OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 256. See the “SET” pin function description below (pin 9) for the maximum adjustable sink current setting. Also tied to the non-inverting input of buffer amp. AVDD 3 Analog Power Supply Input. Bypass to GND with 0.1µF capacitor. WP 4 EEPROM Write Protect. Active Low. 0 = Programming disabled; 1 = Programming allowed. GND 5 Ground connection. VDD 6 Digital power supply input. Bypass to GND with 0.1µF capacitor. SDA 7 I2C Serial Data Input SCL 8 I2C Clock Input SET 9 Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the DVR_OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET. VCOM_OUT 10 Output of the buffer amplifier PAD - 10 VCOM_OUT INN 1 DVR_OUT 2 PIN NAME EXPOSED THERMAL PAD* 9 SET 8 SCL WP 4 7 SDA GND 5 6 VDD (*THERMAL PAD CONNECTS TO GND) 2 FUNCTION Thermal pad should be connected to system ground plane to optimize thermal performance. FN7585.0 February 23, 2011 ISL24211 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL24211IRTZ 211Z ISL24211IRTZ-EVALZ Evaluation Board INTERFACE TEMP RANGE (°C) I2C -40 to +85 PACKAGE (Pb-Free) 10 Ld 3x3 TDFN PKG. DWG. # L10.3x3A NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page ISL24211. For more information on MSL please see techbrief TB363. 3 FN7585.0 February 23, 2011 ISL24211 Absolute Maximum Ratings Thermal Information Supply Voltage AVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V Input Voltage with respect to Ground SET, INN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V SCL, SDA and WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..VDD + 0.3V Output Voltage with respect to Ground DVR_OUT, VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVDD Continuous Output Current DVR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA VCOM_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mA ESD Ratings Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 7kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 2kV Latch Up (Tested per JESD 78, Class II, Level A). . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld TDFN Package (Notes 4, 5) . . . . . . . 53 11 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Range AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 19V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 3.6V Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS DC CHARACTERISTICS VDD VDD Supply Range - Operating 2.25 3.6 V AVDD AVDD Supply Range Supporting EEPROM Programming 10.8 19 V AVDD AVDD Supply Range for Wide-Supply Operation (not supporting EEPROM Programming) 4.5 19 V IDD VDD Supply Current WP = SCL = SDA = VDD 95 300 µA IAVDD AVDD Supply Current WP = SCL = SDA = VDD 3.8 6.5 mA DVR_OUT CHARACTERISTICS ZSESET SET Zero-Scale Error ±3 LSB FSESET SET Full-Scale Error ±8 LSB TCVSET SET Voltage Drift 7 VDVR_OUT DVR_OUT Voltage Range IDVR_OUT Maximum DVR_OUT Sink Current IDVR_OUT < 0.5mA VSET + 0.4 µV/°C AVDD V 4 mA INL Integral Non-Linearity ±2 LSB DNL Differential Non-Linearity ±1 LSB OUTPUT AMPLIFIER CHARACTERISTICS VOS TCVOS IB Input Offset Voltage ±2 Input Offset Voltage Drift -6.3 Input Bias Current 0.001 ±15 mV µV/°C ±1 µA CMRR Common-Mode Rejection Ratio 55 75 dB PSRR Power Supply Rejection Ratio 60 82 dB AVOL Open Loop Gain VOL Output Swing Low 55 IL = -5mA 4 75 50 dB 150 mV FN7585.0 February 23, 2011 ISL24211 Electrical Specifications Test Conditions: VDD = 3.3V, AVDD = 18V, RSET = 5kΩ, R1 = 10kΩ, R2 = 10kΩ, (See Figure 5), VCOM_OUT pin connected to INN, unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER VOH Output Swing High ISC Short Circuit Current (Sinking) TEST CONDITIONS IL = 5mA Short Circuit Current (Sourcing) SR tS BW MIN (Note 6) TYP MAX (Note 6) 17.85 17.9 V 300 430 mA UNITS 450 555 mA Slew Rate (Rising) 1kΩ || 8pF Load 70 116 V/µs Slew Rate (Falling) 1kΩ || 8pF Load 50 93 V/µs Settling Time to 0.2% 150 ns -3dB Bandwidth 60 MHz I2C INPUTS AND OUTPUT VIH_I2C SDA, SCL Logic 1 Input Voltage VIL_I2C SDA, SCL Logic 0 Input Voltage VHYS_I2C IL_I2C V 0.55 SDA, SCL Hysteresis 260 SDA, SCL Input Leakage Current VOL_I2C SDA Output Logic Low VIH_WP WP Input Logic High VIL_WP WP Input Logic Low VHYS_WP WP Input Hysteresis IL_WP 1.44 I = -3mA mV ±1 µA 0.4 V 0.7VDD V 0.3VDD 260 WP Input Leakage Current -0.20 V -0.5 V mV -1 µA 400 kHz I2C TIMING fCLK I2C Clock Frequency tSCH I2C Clock High Time 0.6 µs tSCL I2C Clock Low Time 1.3 µs tDSP I2C Spike Rejection Filter Pulse Width tSDS I2C Data Set Up Time 250 ns tSDH I2C Data Hold Time 250 ns tBUF I2C Time Between Stop and Start 200 µs tSTS I2C Repeated Start Condition Set-up 0.6 µs tSTH I2C Repeated Start Condition Hold 0.6 µs 0.6 0 50 ns tSPS I2C Stop Condition Set-up CSDA SDA Pin Capacitance 10 pF CSCL SCL Pin Capacitance 10 pF tWR EEPROM Write Cycle Time 100 ms µs NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5 FN7585.0 February 23, 2011 ISL24211 Application Information AVDD LCD panels have a VCOM (common voltage) that must be precisely set to minimize flicker. Figure 3 shows a typical VCOM adjustment circuit using a mechanical potentiometer, and the equivalent circuit replacement using the ISL24211. Having a digital I2C interface enables automatic, digital flicker minimization during production test and alignment. After programming, the I2C interface has no further use therefore, the ISL24211 automatically powers up with the correct VCOM voltage programmed previously. The ISL24211 uses a digitally controllable potentiometer (DCP), with 256 steps of resolution (see Figure 4) to change the current drawn at the DVR_OUT pin, which then changes the voltage created by the R1 to R2 resistor divider (see Figure 5). The DVR_OUT voltage is then buffered by A2 to generate a buffered output voltage at the VCOM_OUT pin, capable of directly driving the VCOM input of an LCD panel. The amount of current sunk is controlled by the setting of the DCP, which is recalled at power-up from the ISL24211’s internal EEPROM. The EEPROM is typically programmed during panel manufacture. As noted in the Electrical Specifications on page 4, the ISL24211 requires a minimum AVDD voltage of 10.8V for EEPROM programming, but will work in normal operation (with no EEPROM programming) down to 4.5V. AVDD REGISTER VALUE 19R 255 AVDD 20 254 253 VDCP 252 R 251 2 1 0 FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP Output Current Sink Figure 5 shows the schematic of the DVR_OUT current sink. The combination of amplifier A1, transistor Q1, and resistor RSET forms a voltage-controlled current source, with the voltage determined by the DCP setting. AVDD RA RB VCOM R1 I DVR_OUT DVR_ OUT AVDD R1 = RA R2 = RB+RC R2 RC RSET = RARB + RARC 20RB VDCP VCOM_OUT Q1 A2 VOUT A1 AVDD VDD R1 ISL24211 IOUT R2 AVDD VCOM_OUT DVR_OUT VSAT VCOM GND IOUT RSET VSET = VDCP = IOUT * RSET RSET FIGURE 5. CURRENT SINK CIRCUIT FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT DCP (Digitally Controllable Potentiometer) The DCP controls the voltage that ultimately controls the SET current. Figure 4 shows the relationship between the register value and the DCP’s tap position. Note that a register value of 0 selects the first step of the resistor string. The output voltage of the DCP is given in Equation 1: 6 SET INN SET RegisterValue + 1 AV DD V DCP = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞ ⎝ ⎠ ⎝ 20 ⎠ 256 INN The external RSET resistor sets the full-scale (maximum) sink current that can be pulled from the DVR_OUT node. The relationship between IDVR_OUT and Register Value is shown in Equation 2. V DCP RegisterValue + 1 AV DD 1 I DVROUT = ------------- = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞ ⎛ -------------⎞ ⎝ ⎠ ⎝ 20 ⎠ ⎝ R ⎠ 256 R SET SET (EQ. 2) (EQ. 1) FN7585.0 February 23, 2011 ISL24211 The maximum value of IDVR_OUT can be calculated by substituting the maximum register value of 255 into Equation 2, resulting in Equation 3: A VDD I DVROUT ( MAX ) = -------------------20R SET (EQ. 3) Equation 2 can also be used to calculate the unit sink current step size per Register Code, resulting in Equation 4: AV DD I STEP = ---------------------------------------------( 256 ) ( 20 ) ( R SET ) (EQ. 4) Determination of RSET The ultimate goal for the ISL24211 is to generate an adjustable voltage between two endpoints, VCOM_MIN and VCOM_MAX, with a fixed power supply voltage, AVDD. This is accomplished by choosing the correct values for RSET, R1 and R2. The exact value of RSET is not critical. Values from 1k to more than 100k will work under most conditions. The following expression calculates the minimum RSET value: AV DD ⎛ ⎞ -------------⎜ ⎟ 16 R SET ( MIN ) = ⎜ ------------------------------------------------------⎟ ( kΩ ) ⎜ AV DD ⎟ ⎜⎛V – --------------⎞ ⎟ ⎝ ⎝ OUT ( MIN ) 20 ⎠ ⎠ (EQ. 5) Note that this is the absolute minimum value for RSET. Larger RSET values reduce quiescent power, since R1 and R2 are proportional to RSET. The ISL24211 is tested with a 5kΩ RSET. Determination of R1 and R2 With AVDD, VCOM(MIN) and VCOM(MAX) known and RSET chosen per the above requirements, R1 and R2 can be determined using Equations 6 and 7: ⎛ V COM ( MAX ) – V COM ( MIN ) ⎞ R 1 = 5120 ⋅ R SET ⎜ ---------------------------------------------------------------------------------⎟ ⎝ 256 ⋅ V COM ( MAX ) – V COM ( MIN )⎠ (EQ. 6) V COM ( MAX ) – V COM ( MIN ) ⎛ ⎞ R 2 = 5120 ⋅ R SET ⎜ ---------------------------------------------------------------------------------------------------------------------⎟ 255 AV ⋅ ⎝ DD + V COM ( MIN ) – 256 ⋅ V COM ( MAX )⎠ (EQ. 7) Final Transfer Function The voltage at DVR_OUT can be calculated from Equation 8: ⎛ R2 ⎞ ⎛ RegisterValue + 1 ⎛ R 1 ⎞ ⎞ V DVROUT = AV DD ⎜ --------------------⎟ ⎜ 1 – --------------------------------------------------- ⎜ --------------------⎟ ⎟ R + R 256 ⎝ 20R SET⎠ ⎠ ⎝ 1 2⎠ ⎝ (EQ. 8) With amplifier A2 in the unity-gain configuration (VCOM_OUT tied to INN as shown in Figure 5), VDVROUT = VCOM_OUT = VCOM. Example As an example, suppose the AVDD supply is 15V, the desired VCOM_MIN= 6.5V and the desired VCOM_MAX = 8.5V. RSET is arbitrarily chosen to be 7.5kΩ. 7 First, verify that our chosen RSET meets the minimum requirement described in Equation 5: 15 ⎛ ⎞ ⎛ ⎞ ------⎜ ⎟ ⎜ ⎟ 16 ( 7.5kΩ ) > ⎜ R SET ( MIN ) = ⎜ ------------------------------⎟ = 0.163kΩ⎟ 15 ⎜ ⎛ 6.5V – -------⎞ ⎟ ⎜ ⎟ ⎝⎝ ⎝ ⎠ 20⎠ ⎠ (EQ. 9) Using Equations 6 and 7, calculate the values of R1 and R2: 8.5 – 6.5 R 1 = 5120 ⋅ 7500 ⋅ ⎛ --------------------------------------⎞ = 35.4kΩ ⎝ 256 ⋅ 8.5 – 6.5⎠ (EQ. 10) 8.5 – 6.5 R 2 = 5120 ⋅ 7500 ⋅ ⎛ ------------------------------------------------------------------⎞ = 46.4kΩ ⎝ 255 ⋅ 15 + 6.5 – 256 ⋅ 8.5⎠ (EQ. 11) Table 1 shows the resulting VCOM voltage as a function of register value for these conditions. TABLE 1. EXAMPLE VDVR_OUT vs REGISTER VALUE REGISTER VALUE VDVR_OUT (V) 0 8.49 20 8.34 40 8.18 60 8.02 80 7.87 100 7.71 120 7.55 127 7.50 140 7.40 160 7.24 180 7.09 200 6.93 220 6.77 240 6.62 255 6.50 Output Voltage Span Calculation It is also possible to calculate VCOM(MIN) and VCOM(MAX) from the existing resistor values. VCOM_MIN occurs when the greatest current, IDVR(MAX), is drawn from the middle node of the R1/R2 divider. Substituting RegisterValue = 255 into Equation 8 gives the following: ⎛ R1 ⎞ ⎞ ⎛ R2 ⎞ ⎛ V COM ( MIN ) = AV DD ⎜ --------------------⎟ ⎜ 1 – ⎜ --------------------⎟ ⎟ ⎝ 20R SET⎠ ⎠ ⎝ R1+ R2 ⎠ ⎝ (EQ. 12) Similarly, RegisterValue = 0 for VCOM(MAX): ⎛ R2 ⎞ ⎛ 1 ⎛ R1 ⎞ ⎞ V COM ( MAX ) = AV DD ⎜ --------------------⎟ ⎜ 1 – ---------- ⎜ --------------------⎟ ⎟ R + R 256 ⎝ 20R SET⎠ ⎠ ⎝ 1 2⎠ ⎝ (EQ. 13) FN7585.0 February 23, 2011 ISL24211 By finding the difference of Equation 13 and Equation 12, the total span of VCOM can be found: ⎛ R2 ⎞ 1 ⎛ R1 ⎞ V COM SPAN = AV DD ⎜ --------------------⎟ ⎛ 1 – ----------⎞ ⎜ --------------------⎟ ⎝ ⎠ ⎝ 20R R + R 256 ⎝ 1 2⎠ SET⎠ (EQ. 14) Assuming that the IDVROUT(MIN) = 0 instead of ISTEP, the expression in Equation 14 simplifies to: ⎛ R 1 ⋅ R 2 ⎞ ⎛ AV DD ⎞ ⎛ R1 ⋅ R2 ⎞ V COM SPAN = ⎜ --------------------⎟ ⎜ --------------------⎟ = ⎜ --------------------⎟ I DVROUT ( MAX ) ⎝ R 1 + R 2⎠ ⎝ 20R SET⎠ ⎝ R 1 + R 2⎠ (EQ. 15) DVR_OUT Pin Leakage Current REGISTER = 255 4 6 8 10 12 14 16 OUT PIN VOLTAGE (V) FIGURE 6. DVR_OUT PIN LEAKAGE CURRENT FIGURE 7. POWER SUPPLY SEQUENCE Operating and Programming Supply Voltage and Current 18 20 2.7mA VDD Programming Current 0.05 2 tVS During EEPROM programming, IDD and IAVDD will temporarily be higher than their quiescent currents. Figure 8 shows a typical IDD and IAVDD current profile during EEPROM programming. The current pulses are Erase and Write cycles. The EEPROM programming algorithm is shown in Figure 9. The algorithm attempts up to 4 erase cycles and 4 programming cycles, however typical parts only require 1 cycle of each, sometimes 2 when AVDD is near the minimum 10.8V limit. SET PIN CURRENT 0.10 0.00 0 AVDD 200µA 50µA ~1ms 90µA AVDD Programming Current CURRENT (mA) 0.20 0.15 Do not remove VDD or AVDD within 100ms of the start of the EEPROM programming cycle. Removing power before the EEPROM programming cycle is completed may result in corrupted data in the EEPROM. To program the EEPROM, AVDD must be ≥10.8V. If programming is not required, the ISL24211 will operate over an AVDD range of 4.5V to 19V. OUT PIN CURRENT 0.25 The recommended power supply sequencing is shown in Figure 7. When applying power, VDD should be applied before or at the same time as AVDD. The minimum time for tVS is 0µs. When removing power, the sequence of VDD and AVDD is not important. VDD When the voltage on the DVR_OUT pin is greater than 10V, an additional leakage current flows into the pin in addition to the ISET current. Figure 6 shows the ISET current and the DVR_OUT pin current for DVR_OUT pin voltage up to 19V. In applications where the voltage on the DVR_OUT pin will be greater than 10V, the actual output voltage will be lower than the voltage calculated by Equation 8. The graph in Figure 6 was measured with RSET = 4.99kΩ. 0.30 Power Supply Sequence IP 25µA 100ms Max FIGURE 8. IDD AND IAVDD CURRENT PROFILE DURING EEPROM PROGRAMMING 8 FN7585.0 February 23, 2011 ISL24211 ISL24211 Programming Start EEPROM Programming The ISL24211 accepts I2C bus address and data when the WP pin is high. The ISL24211 ignores the I2C bus when the WP pin is low. Figure 10 shows the serial data format for writing the register and programming the EEPROM. Figure 11 shows the serial data format for reading the DAC register. Table 2 shows the truth table for reading and writing the device. Erase Pulse TABLE 2. ISL24211 READ AND WRITE CONTROL Are EEPROM Cells Erased? No Yes WP PIN R/W P 0 1 X Read Register. 0 0 1 Will acknowledge I2C transactions. Will not write to register. 0 0 0 Will acknowledge I2C transactions. Will not write to EEPROM. 1 1 X Read DAC Register. 1 0 1 Write DAC Register. 1 0 0 Program EEPROM. Write Pulse Are EEPROM Cells Programmed? No Yes EEPROM Programming Complete FIGURE 9. EEPROM PROGRAMMING FLOWCHART FUNCTION Programming the EEPROM memory transfers the current DAC register value to the EEPROM and occurs when the control bits select the programming mode and the AVDD voltage is >10.8V. After the EEPROM programming cycle is started, the WP pin can be returned to logic low while the EEPROM write completes, which takes a maximum of 100ms. The ISL24211 uses a 6-bit I2C address, which is “100111yx” for the first transmitted byte. Bit x is the R/W bit, and Bit y is the LSB (D0) of the DCP register code to be written. The complete read and write protocol is shown in Figures 10 and 11. I2C Bus Signals The ISL24211 uses fixed voltages for its I2C thresholds, rather than the percentage of VDD described in the I2C specification (see Table 3). This should not cause a problem in most systems, but the I2C logic levels in a specific design should be checked to ensure they are compatible with the ISL24211. TABLE 3. ISL24211 I2C BUS LOGIC LEVELS SYMBOL 9 ISL24211 I2C STANDARD VIL_I2C 0.55V 0.3*VDD VIH_I2C 1.44V 0.7*VDD FN7585.0 February 23, 2011 I2C Read and Write Format ISL24211 I2C Write Byte 1 Byte 2 Data R/W LSB 6 bit Address Start 10 MSB Start 1 ACK LSB 0 0 1 1 1 D0 0 Data P D7 Stop ACK Stop LSB MSB ACK ACK D6 D5 D4 D3 D2 D1 P When R/W = 0 P = 0: Program EEPROM P = 1: Write Register R/W = 0 = Write R/W = 1 = Read ISL24211 I2C Read Byte 2 Byte 1 X 6 bit Address Start MSB Start 1 R/W ACK Start LSB 0 0 1 1 1 X 1 Data MSB ACK Start D7 ACK Stop ACK Stop LSB D6 R/W = 0 = Write R/W = 1 = Read FIGURE 11. I2C READ FORMAT D5 D4 D3 D2 D1 D0 ISL24211 FIGURE 10. I2C WRITE FORMAT FN7585.0 February 23, 2011 ISL24211 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 2/23/11 FN7585.0 CHANGE Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL24211 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/sear For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN7585.0 February 23, 2011 ISL24211 Package Outline Drawing L10.3x3A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 3.00 A 2.0 REF 6 PIN 1 INDEX AREA B 8X 0.50 BSC 5 1 6 PIN 1 INDEX AREA 10X 0 . 30 3.00 1.50 0.15 (4X) 10 0.10 M C A B 0.05 M C 5 4 10 X 0.25 TOP VIEW 2.30 ( 2.30 ) BOTTOM VIEW 0 .80 MAX SEE DETAIL "X" 0.10 C C (2.90) SEATING PLANE 0.08 C (1.50) SIDE VIEW (10 X 0.50) 0 . 2 REF 5 C ( 8X 0 .50 ) ( 10X 0.25 ) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 Angular ±2.50° 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. 12 Compliant to JEDEC MO-229-WEED-3 except exposed pad length (2.30mm). FN7585.0 February 23, 2011