XMC4300 Microcontroller Series for Industrial Applications XMC4000 Family ARM® Cortex®-M4 32-bit processor core Data Sheet V1.0 2016-02 Microcontrollers Edition 2016-02 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. XMC4300 Microcontroller Series for Industrial Applications XMC4000 Family ARM® Cortex®-M4 32-bit processor core Data Sheet V1.0 2016-02 Microcontrollers XMC4300 XMC4000 Family XMC4300 Data Sheet Revision History: V1.0 2016-02 Previous Versions: Page Subjects Initial version. Trademarks C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG. ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of ARM, Limited. CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are trademarks of ARM, Limited. Synopsys™ is a trademark of Synopsys, Inc. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Data Sheet V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Table of Contents Table of Contents 1 1.1 1.2 1.3 1.4 1.5 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 2.1 2.2 2.2.1 2.2.2 2.2.2.1 2.3 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 20 21 25 3 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.8.1 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog to Digital Converters (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital to Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 27 27 27 28 29 32 33 34 34 41 45 48 50 51 53 57 61 63 63 64 65 67 68 70 72 73 73 Data Sheet 5 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Table of Contents 3.3.8.2 3.3.8.3 3.3.8.4 3.3.9 3.3.10 3.3.10.1 3.3.10.2 3.3.10.3 3.3.11 3.3.11.1 3.3.11.2 3.3.11.3 3.3.11.4 3.3.11.5 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EtherCAT (ECAT) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECAT Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . ETH Management Signal Parameters (MCLK, MDIO) . . . . . . . . . . . MII Timing TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MII Timing RX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sync/Latch Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 78 80 89 90 90 91 92 93 93 93 94 96 97 4 4.1 4.1.1 4.2 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Data Sheet 6 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family About this Document About this Document This Data Sheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC4300 series devices. The document describes the characteristics of a superset of the XMC4300 series devices. For simplicity, the various device types are referred to by the collective term XMC4300 throughout this manual. XMC4000 Family User Documentation The set of user documentation includes: • • • Reference Manual – decribes the functionality of the superset of devices. Data Sheets – list the complete ordering designations, available features and electrical characteristics of derivative devices. Errata Sheets – list deviations from the specifications given in the related Reference Manual or Data Sheets. Errata Sheets are provided for the superset of devices. Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions of those documents. Data Sheet 7 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Summary of Features 1 Summary of Features The XMC4300 devices are members of the XMC4000 Family of microcontrollers based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial Control, Power Conversion, Sense & Control. EtherCAT System Masters System Slaves SCU CPU RTC ARM Cortex-M4 ERU0 GPDMA0 System DCode Ethernet WDT USB OTG ICode FCE Bus Matrix Data Code PMU ROM & Flash PSRAM USIC0 DSRAM1 CCU80 PBA0 LEDTS0 Peripherals 0 ERU1 Figure 1 VADC PORTS DAC PBA1 Peripherals 1 CCU40 CCU41 SDMMC USIC1 MultiCAN System Block Diagram CPU Subsystem • • • • • • • CPU Core – High Performance 32-bit ARM Cortex-M4 CPU – 16-bit and 32-bit Thumb2 instruction set – DSP/MAC instructions – System timer (SysTick) for Operating System support Floating Point Unit Memory Protection Unit Nested Vectored Interrupt Controller General Purpose DMA with up-to 8 channels Event Request Unit (ERU) for programmable processing of external and internal service requests Flexible CRC Engine (FCE) for multiple bit error detection Data Sheet 8 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Summary of Features On-Chip Memories • • • • 16 KB on-chip boot ROM 64 KB on-chip high-speed program memory 64 KB on-chip high speed data memory 256 KB on-chip Flash Memory with 8 KB instruction cache Communication Peripherals • • • • • • • Ethernet MAC module capable of 10/100 Mbit/s transfer rates EtherCATSlave interface (ECAT) capable of 100 Mbit/s transfer rates with 2 MII ports, 8 Fieldbus Memory Management Units (FMMU), 8 Sync Manager, 64 bit distributed clocks Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 2 nodes, 64 message objects (MO), data rate up to 1 MBaud Four Universal Serial Interface Channels (USIC),providing 4 serial channels, usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces LED and Touch-Sense Controller (LEDTS) for Human-Machine interface SD and Multi-Media Card interface (SDMMC) for data storage memory cards Analog Frontend Peripherals • • Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with input out-of-range comparators Digital-Analog Converter (DAC) with two channels of 12-bit resolution Industrial Control Peripherals • • • • • • One Capture/Compare Units 8 (CCU8) for motor control and power conversion Two Capture/Compare Units 4 (CCU4) for use as general purpose timers Window Watchdog Timer (WDT) for safety sensitive applications Die Temperature Sensor (DTS) Real Time Clock module with alarm support System Control Unit (SCU) for system configuration and control Input/Output Lines • • • • • Programmable port driver control module (PORTS) Individual bit addressability Tri-stated in input mode Push/pull or open drain output mode Boundary scan test support over JTAG interface Data Sheet 9 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Summary of Features On-Chip Debug Support • • Full support for debug features: 8 breakpoints, CoreSight, trace Various interfaces: ARM-JTAG, SWD, single wire trace 1.1 Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies: • • • • • <DDD> the derivatives function set <Z> the package variant – E: LFBGA – F: LQFP – Q: VQFN <PPP> package pin count <T> the temperature range: – F: -40°C to 85°C – K: -40°C to 125°C <FFFF> the Flash memory size. For ordering codes for the XMC4300 please contact your sales representative or local distributor. This document describes several derivatives of the XMC4300 series, some descriptions may not apply to a specific product. Please see Table 1. For simplicity the term XMC4300 is used for all derivatives throughout this document. 1.2 Device Types These device types are available and can be ordered through Infineon’s direct and/or distribution channels. Table 1 Synopsis of XMC4300 Device Types 1) Derivative Package Flash Kbytes SRAM Kbytes XMC4300-F100x256 PG-LQFP-100 256 128 1) x is a placeholder for the supported temperature range. 1.3 Device Type Features The following table lists the available features per device type. Data Sheet 10 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Summary of Features Table 2 Features of XMC4300 Device Types 1) Derivative LED TS Intf. SD MMC Intf. ETH Intf. ECAT Slave Intf. USB Intf. XMC4300-F100x256 1 1 RMII 2 x MII 1 USIC Chan. MultiCAN Nodes, MO 2x2 N0, N1 MO[0..63] 1) x is a placeholder for the supported temperature range. Table 3 Features of XMC4300 Device Types 1) Derivative ADC Chan. DAC Chan. CCU4 Slice CCU8 Slice XMC4300-F100x256 16 2 2x4 1x4 1) x is a placeholder for the supported temperature range. 1.4 Definition of Feature Variants The XMC4300 types are offered with several memory sizes and number of available VADC channels. Table 4 describes the location of the available Flash memory, Table 5 describes the location of the available SRAMs, Table 6 the available VADC channels. Table 4 Flash Memory Ranges Total Flash Size Cached Range Uncached Range 256 Kbytes 0800 0000H − 0803 FFFFH 0C00 0000H − 0C03 FFFFH Table 5 SRAM Memory Ranges Total SRAM Size Program SRAM System Data SRAM 128 Kbytes 1FFF 0000H − 1FFF FFFFH 2000 0000H − 2000 FFFFH Table 6 ADC Channels1) Package VADC G0 VADC G1 PG-LQFP-100 CH0..CH7 CH0..CH7 1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table. Data Sheet 11 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Summary of Features 1.5 Identification Registers The identification registers allow software to identify the marking. Table 7 XMC4300 Identification Registers Register Name Value Marking SCU_IDCHIP 0004 3001H AA JTAG IDCODE 101D F083H AA Data Sheet 12 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information 2 General Device Information This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping. 2.1 Logic Symbols VAREF VAGND VDDA VSSA (1) (1) (1) (1) VDDC VDDP VSS (4) (4) (1) Exp. Die Pad (VSS) VBAT (1) RTC_XTAL1 (1) VSSO RTC_XTAL2 Port 0 13 bit HIB_IO_0 HIB_IO_1 Port 1 16 bit XTAL1 Port 2 13 bit XTAL2 USB_DP Port 3 7 bit USB_DM VBUS Port 4 2 bit Port 14 14 bit Port 5 4 bit Port 15 4 bit PORST TCK JTAG 3 bit TMS Figure 2 Data Sheet SWD 1 bit via Port Pins XMC4300 Logic Symbol PG-LQFP-100 13 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information 2.2 Pin Configuration and Definition 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P 0.2 P 0.3 P 0.4 P 0.5 P 0.6 P 0.11 P 0.12 P 3.3 P 3.4 P 3.5 P 3.6 P 0.7 P 0.8 V DDP V DDC P 4.0 P 4.1 P 1.6 P 1.7 P 1.8 P 1.9 P 1.0 P 1.1 P 1.2 P 1.3 The following figures summarize all pins, showing their locations on the four sides of the different packages. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 XMC4300 (Top View) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1. 4 P1. 5 P1. 10 P1. 11 P1. 12 P1. 13 P1. 14 P1. 15 TCK TMS P ORS T V DDC VSSO X TA L2 X TA L1 V DDP VSS P5. 0 P5. 1 P5. 2 P5. 7 P2. 6 P2. 7 P2. 0 P2. 1 P 14.5 P 14.4 P 14.3 P 14.2 P 14.1 P 14.0 V A GND VA REF V SS A VDDA P 14.9 P 14.8 P 15.9 P 15.8 P 2.15 P 2.14 V DDC VDDP P 2.10 P 2.9 P 2.8 P 2.5 P 2.4 P 2.3 P 2.2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P0. 1 P0. 0 P0. 10 P0. 9 P3. 2 P3. 1 P3. 0 US B_DM US B_DP V B US V DDP V DDC HIB _IO _1 HIB _IO _0 RTC_X TA L2 RTC_X TA L1 VBAT P15. 3 P15. 2 P14. 15 P14. 14 P14. 13 P14. 12 P14. 7 P14. 6 Figure 3 Data Sheet XMC4300 PG-LQFP-100 Pin Configuration (top view) 14 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information 2.2.1 Package Pin Summary The following general scheme is used to describe each pin: Table 8 Package Pin Mapping Description Function Package A Package B ... Pad Type Name N Ax ... A2 Notes The table is sorted by the “Function” column, starting with the regular Port pins (Px.y), followed by the dedicated pins (i.e. PORST) and supply pins. The following columns, titled with the supported package variants, lists the package pin number to which the respective function is mapped in that package. The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad, In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about the pad properties are defined in the Electrical Parameters. In the “Notes”, special information to the respective pin/function is given, i.e. deviations from the default configuration after reset. Per default the regular Port pins are configured as direct input with no internal pull device active. Table 9 Package Pin Mapping Function LQFP-100 Pad Type P0.0 2 A1+ P0.1 1 A1+ P0.2 100 A2 P0.3 99 A2 P0.4 98 A2 P0.5 97 A2 Notes P0.6 96 A2 P0.7 89 A2 After a system reset, via HWSEL this pin selects the DB.TDI function. P0.8 88 A2 After a system reset, via HWSEL this pin selects the DB.TRST function, with a weak pull-down active. P0.9 4 A2 P0.10 3 A1+ P0.11 95 A1+ P0.12 94 A1+ Data Sheet 15 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information Table 9 Package Pin Mapping (cont’d) Function LQFP-100 Pad Type P1.0 79 A1+ P1.1 78 A1+ P1.2 77 A2 P1.3 76 A2 P1.4 75 A1+ P1.5 74 A1+ P1.6 83 A2 P1.7 82 A2 P1.8 81 A2 P1.9 80 A2 P1.10 73 A1+ P1.11 72 A1+ P1.12 71 A2 P1.13 70 A2 P1.14 69 A2 P1.15 68 A2 P2.0 52 A2 P2.1 51 A2 P2.2 50 A2 P2.3 49 A2 P2.4 48 A2 P2.5 47 A2 P2.6 54 A1+ P2.7 53 A1+ P2.8 46 A2 P2.9 45 A2 P2.10 44 A2 P2.14 41 A2 P2.15 40 A2 P3.0 7 A2 P3.1 6 A2 Data Sheet Notes After a system reset, via HWSEL this pin selects the DB.TDO function. 16 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information Table 9 Package Pin Mapping (cont’d) Function LQFP-100 Pad Type P3.2 5 A2 P3.3 93 A1+ P3.4 92 A1+ P3.5 91 A2 P3.6 90 A2 Notes P4.0 85 A2 P4.1 84 A2 P5.0 58 A1+ P5.1 57 A1+ P5.2 56 A1+ P5.7 55 A1+ P14.0 31 AN/DIG_IN P14.1 30 AN/DIG_IN P14.2 29 AN/DIG_IN P14.3 28 AN/DIG_IN P14.4 27 AN/DIG_IN P14.5 26 AN/DIG_IN P14.6 25 AN/DIG_IN P14.7 24 AN/DIG_IN P14.8 37 AN/DAC/DIG_IN P14.9 36 AN/DAC/DIG_IN P14.12 23 AN/DIG_IN P14.13 22 AN/DIG_IN P14.14 21 AN/DIG_IN P14.15 20 AN/DIG_IN P15.2 19 AN/DIG_IN P15.3 18 AN/DIG_IN P15.8 39 AN/DIG_IN P15.9 38 AN/DIG_IN Data Sheet 17 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information Table 9 Package Pin Mapping (cont’d) Function LQFP-100 Pad Type Notes HIB_IO_0 14 A1 special At the first power-up and with every reset of the hibernate domain this pin is configured as open-drain output and drives "0". As output the medium driver mode is active. HIB_IO_1 13 A1 special At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active. USB_DP 9 special USB_DM 8 special TCK 67 A1 Weak pull-down active. TMS 66 A1+ Weak pull-up active. As output the strong-soft driver mode is active. PORST 65 special Weak pull-up permanently active, strong pull-down controlled by EVR. XTAL1 61 clock_IN XTAL2 62 clock_O RTC_XTAL1 16 clock_IN RTC_XTAL2 15 clock_O VBAT 17 Power VBUS 10 special VAREF 33 AN_Ref VAGND 32 AN_Ref VDDA 35 AN_Power VSSA 34 AN_Power VDDC 12 Power VDDC 42 Power VDDC 64 Power VDDC 86 Power VDDP 11 Power Data Sheet When VDDP is supplied VBAT has to be supplied as well. 18 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information Table 9 Package Pin Mapping (cont’d) Function LQFP-100 Pad Type VDDP 43 Power VDDP 60 Power VDDP 87 Power VSS 59 Power VSSO 63 Power VSS Exp. Pad Power Data Sheet Notes Exposed Die Pad The exposed die pad is connected internally to VSS. For proper operation, it is mandatory to connect the exposed pad directly to the common ground on the board. For thermal aspects, please refer to the Data Sheet. Board layout examples are given in an application note. 19 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family General Device Information 2.2.2 Port I/O Functions The following general scheme is used to describe each Port pin: Table 10 Port I/O Function Description Function Outputs ALT1 ALTn P0.0 Pn.y Inputs HWO0 HWI0 Input MODA.OUT MODB.OUT MODB.INA MODA.OUT Input MODC.INA MODA.INA MODC.INB Pn.y XMC4000 Control Logic PAD Input 0 MODA.INA MODA MODB VDDP ... Input n HWI0 HWI1 Pn.y SW MODB.OUT ALT1 ... ALTn HWO0 HWO1 Figure 4 GND Simplified Port Structure Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value. Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective module, with the pin characteristics controlled by the port registers (within the limits of the connected pad). The port pin input can be connected to multiple peripherals. Most peripherals have an input multiplexer to select between different possible input sources. The input path is also active while the pin is configured as output. This allows to feedback an output to on-chip resources without wasting an additional external pin. By Pn_HWSEL it is possible to select between different hardware “masters” (HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control overrules settings in the respective port pin registers. Data Sheet 20 V1.0, 2016-02 Subject to Agreement on the Use of Product Information Data Sheet 2.2.2.1 Port I/O Function Table Table 11 Port I/O Functions Function Output Input ALT1 ALT2 ALT3 ALT4 HWO0 HWI0 Input Input Input P0.0 ECAT0. PHY_RST CAN. N0_TXD CCU80. OUT21 LEDTS0. COL2 U1C1. DX0D ETH0. CLK_RMIIB ERU0. 0B0 P0.1 USB. DRIVEVBUS U1C1. DOUT0 CCU80. OUT11 LEDTS0. COL3 ETH0. CRS_DVB ERU0. 0A0 P0.2 ECAT0. P1_TXD2 U1C1. SELO1 CCU80. OUT01 U1C0. DOUT3 U1C0. HWIN3 ETH0. RXD0B P0.3 ECAT0. P1_TXD3 CCU80. OUT20 U1C0. DOUT2 U1C0. HWIN2 ETH0. RXD1B Input Input ETH0. TX_EN CCU80. OUT10 U1C0. DOUT1 U1C0. HWIN1 U1C0. DX0A ETH0. TXD0 U1C0. DOUT0 CCU80. OUT00 U1C0. DOUT0 U1C0. HWIN0 U1C0. DX0B ECAT0. P1_RX_CLKA ECAT0. P1_RXD2A 21 U1C0. SELO0 CCU80. OUT30 ERU0. 3B2 CCU80. IN2B WWDT. SERVICE_OUT U0C0. SELO0 ECAT0. LED_ERR DB. TDI U0C0. DX2B ERU0. 2B1 CCU80. IN0A P0.8 SCU. EXTCLK U0C0. SCLKOUT ECAT0. LED_RUN DB. TRST U0C0. DX1B ERU0. 2A1 CCU80. IN1B U1C1. SELO0 CCU80. OUT12 LEDTS0. COL0 ETH0. MDIA U1C1. DX2A U1C1. SCLKOUT CCU80. OUT02 LEDTS0. COL1 P0.11 ECAT0. P1_LINK_ACT U1C0. SCLKOUT CCU80. OUT31 SDMMC. RST CCU40. OUT3 ECAT0. MDO U0C0. SELO0 CCU40. OUT3 ERU1. PDOUT3 U0C0. SCLKOUT CCU40. OUT2 ERU1. PDOUT2 CCU40. OUT1 ERU1. PDOUT1 ERU1. PDOUT0 ECAT0. P0_TXD3 P1.3 ECAT0. P0_TX_ENA U0C0. MCLKOUT CCU40. OUT0 P1.4 WWDT. SERVICE_OUT CAN. N0_TXD CCU80. OUT33 P1.5 CAN. N1_TXD U0C0. DOUT0 CCU80. OUT23 P1.6 ECAT0. P0_TXD0 U0C0. SCLKOUT ETH0. RXERB ECAT0. MDIA SDMMC. SDWC U0C0. DOUT3 ECAT0. P1_RXD1A CCU80. IN1A CCU80. IN2A ERU0. 1B0 ECAT0. P1_RX_DVA ERU0. 1A0 ECAT0. P1_TX_CLKA U1C0. DX1A ERU0. 3A2 ECAT0. P1_RXD0A U1C1. DX2B ERU0. 2B2 CCU80. IN3A U0C0. DX2A ERU0. 3B0 CCU40. IN3A ECAT0. P0_TX_CLKA U0C0. DX1A ERU0. 3A0 CCU40. IN2A ECAT0. P0_RX_CLKA U0C0. HWIN3 U0C0. DOUT2 U0C0. HWIN2 U0C0. DOUT1 U0C0. HWIN1 U0C0. DX0B CAN. N1_RXDD ERU0. 2B0 U0C0. DOUT0 U0C0. HWIN0 U0C0. DX0A CAN. N0_RXDA ERU0. 2A0 SDMMC. DATA1_OUT SDMMC. DATA1_IN ERU1. 2B0 CCU40. IN1A ERU1. 2A0 CCU40. IN0A ERU1. 0A0 CCU41. IN0C ECAT0. P0_RXD0A CCU41. IN1C ECAT0. P0_RXD1A XMC4300 XMC4000 Family P1.0 USB. ID U1C1. DX1A U1C1. SELO0 P1.1 P1.2 V1.0, 2016-02 Subject to Agreement on the Use of Product Information ETH0. TXD1 ETH0. MDO ETH0. RXDVB ECAT0. P1_RXD3A ERU1. 3A0 P0.6 P0.12 U1C0. DX2A ERU0. 2B3 P0.7 ETH0. MDC Input ETH0. CLKRXB ERU1. 3B0 P0.4 P0.9 Input ERU0. 3B3 P0.5 P0.10 Input Data Sheet Table 11 Port I/O Functions Function (cont’d) Output ALT1 ALT2 P1.7 ECAT0. P0_TXD1 P1.8 ECAT0. P0_TXD2 ALT3 Input ALT4 HWO0 HWI0 U0C0. DOUT0 U1C1. SELO2 SDMMC. DATA2_OUT SDMMC. DATA2_IN U0C0. SELO1 U1C1. SCLKOUT SDMMC. DATA4_OUT SDMMC. DATA4_IN U1C1. DOUT0 SDMMC. DATA5_OUT 22 P1.9 U0C0. SCLKOUT P1.10 ETH0. MDC U0C0. SCLKOUT ECAT0. LED_ERR P1.11 ECAT0. LED_STATE_R UN U0C0. SELO0 ECAT0. LED_RUN P1.12 ETH0. TX_EN CAN. N1_TXD P1.13 ETH0. TXD0 P1.14 ETH0. TXD1 P1.15 SCU. EXTCLK P2.0 CAN. N0_TXD Input Input Input Input Input Input SDMMC. DATA5_IN Input ECAT0. P0_RX_DVA SDMMC. SDCD CCU41. IN2C ECAT0. P0_RXD2A ETH0. MDO ETH0. MDIC CCU41. IN3C ECAT0. P0_RXD3A ECAT0. P0_LINK_ACT SDMMC. DATA6_OUT SDMMC. DATA6_IN U0C1. SELO3 ECAT0. PHY_CLK25 SDMMC. DATA7_OUT SDMMC. DATA7_IN U0C1. SELO2 ECAT0. SYNC0 CAN. N1_RXDC U1C0. DX0E U1C0. DOUT0 P2.1 ERU1. 1A0 LEDTS0. COL1 ETH0. MDO LEDTS0. COL0 DB.TDO/ TRACESWO ETH0. MDIB ERU0. 0B3 ETH0. CLK_RMIIA ECAT0. P0_LINKB CCU40. IN1C ERU1. 0B0 CCU40. IN0C VADC. EMUX00 CCU41. OUT3 LEDTS0. LINE0 LEDTS0. EXTENDED0 LEDTS0. TSIN0A ETH0. RXD0A U0C1. DX0A ERU0. 1B2 CCU41. IN3A P2.3 VADC. EMUX01 U0C1. SELO0 CCU41. OUT2 LEDTS0. LINE1 LEDTS0. EXTENDED1 LEDTS0. TSIN1A ETH0. RXD1A U0C1. DX2A ERU0. 1A2 CCU41. IN2A P2.4 VADC. EMUX02 U0C1. SCLKOUT CCU41. OUT1 LEDTS0. LINE2 LEDTS0. EXTENDED2 LEDTS0. TSIN2A ETH0. RXERA U0C1. DX1A ERU0. 0B2 CCU41. IN1A P2.5 ETH0. TX_EN LEDTS0. EXTENDED3 LEDTS0. TSIN3A ETH0. RXDVA U0C1. DOUT0 CCU41. OUT0 LEDTS0. LINE3 ERU1. PDOUT3 CCU80. OUT13 LEDTS0. COL3 U0C1. DX0B ERU0. 0A2 CCU41. IN0A CAN. N1_RXDA ERU0. 1B3 CCU40. IN3C ETH0. CRS_DVA ECAT0. P0_RX_ERRB P2.7 ETH0. MDC CAN. N1_TXD CCU80. OUT03 LEDTS0. COL2 P2.8 ETH0. TXD0 ERU1. PDOUT1 CCU80. OUT32 LEDTS0. LINE4 LEDTS0. EXTENDED4 LEDTS0. TSIN4A DAC. TRIGGER5 CCU40. IN0B CCU40. IN1B CCU40. IN2B CCU40. IN3B LEDTS0. EXTENDED5 LEDTS0. TSIN5A DAC. TRIGGER4 CCU41. IN0B CCU41. IN1B CCU41. IN2B CCU41. IN3B P2.9 ETH0. TXD1 ERU1. PDOUT2 CCU80. OUT22 LEDTS0. LINE5 P2.10 VADC. EMUX10 ERU1. PDOUT0 ECAT0. PHY_RST ECAT0. SYNC1 P2.14 VADC. EMUX11 U1C0. DOUT0 CCU80. OUT21 P2.15 VADC. EMUX12 ECAT0. P1_TXD3 CCU80. OUT11 ERU1. 1B0 ETH0. CLKRXA U1C0. DX0D LEDTS0. LINE6 LEDTS0. EXTENDED6 LEDTS0. TSIN6A ETH0. COLA U1C0. DX0C CCU40. IN2C XMC4300 XMC4000 Family V1.0, 2016-02 Subject to Agreement on the Use of Product Information P2.2 P2.6 Input Data Sheet Table 11 Port I/O Functions Function ALT1 ALT2 ALT3 P3.0 U0C1. SCLKOUT P3.1 U0C1. SELO0 ECAT0. P1_TXD0 CAN. N0_TXD ECAT0. P1_TXD1 P3.2 (cont’d) Output USB. DRIVEVBUS Input ALT4 HWO0 HWI0 ECAT0. P1_TX_ENA Input Input LEDTS0. COLA ERU0. 0B1 CCU80. IN1C ERU0. 0A1 CCU80. IN0C U1C1. SELO1 P3.4 U1C1. SELO2 P3.5 U1C1. SELO3 U0C1. DOUT0 SDMMC. CMD_OUT SDMMC. CMD_IN ERU0. 3B1 P3.6 U1C1. SELO4 U0C1. SCLKOUT SDMMC. CLK_OUT SDMMC. CLK_IN ERU0. 3A1 SDMMC. LED SDMMC. BUS_POWER CCU80. IN0B P4.0 ECAT0. PHY_CLK25 U1C0. SCLKOUT SDMMC. DATA0_OUT SDMMC. DATA0_IN U1C1. MCLKOUT U0C1. SELO0 SDMMC. DATA3_OUT SDMMC. DATA3_IN 23 U0C0. DOUT0 P5.7 ECAT0. P0_LINK_ACT ECAT0. SYNC0 Input Input U1C1. DX1C ECAT0. P1_LINKA ECAT0. P1_RX_ERRA U0C1. DX0E ECAT0. P0_RX_ERRA ECAT0. P0_LINKA ERU1. PDOUT0 ETH0. RXD0D ERU1. PDOUT1 ETH0. RXD1D ECAT0. P0_RXD1B ERU1. PDOUT2 ETH0. CRS_DVD ECAT0. P0_RXD2B LEDTS0. COLA U0C0. DX0D ECAT0. P0_RXD0B ETH0. RXDVD ECAT0. P0_RXD3B P14.0 VADC. G0CH0 P14.1 VADC. G0CH1 P14.2 VADC. G0CH2 VADC. G1CH2 P14.3 VADC. G0CH3 VADC. G1CH3 P14.4 VADC. G0CH4 ECAT0. LATCH1A P14.5 VADC. G0CH5 ECAT0. LATCH0A CAN. N0_RXDB P14.6 VADC. G0CH6 G0ORC6 ECAT0. P1_RX_CLKB P14.7 VADC. G0CH7 G0ORC7 ECAT0. P1_RXD0B P14.8 DAC. OUT_0 VADC. G1CH0 ETH0. RXD0C P14.9 DAC. OUT_1 VADC. G1CH1 ETH0. RXD1C XMC4300 XMC4000 Family V1.0, 2016-02 Subject to Agreement on the Use of Product Information P5.2 Input CCU80. IN3B P4.1 P5.1 Input CCU80. IN2C P3.3 P5.0 Input U0C1. DX1B U0C1. DX2B ECAT0. MCLK Input Data Sheet Table 11 Port I/O Functions Function (cont’d) Output ALT1 ALT2 ALT3 Input ALT4 HWO0 HWI0 Input Input Input Input Input Input Input Input P14.12 VADC. G1CH4 ECAT0. P1_RXD1B P14.13 VADC. G1CH5 ECAT0. P1_RXD2B P14.14 VADC. G1CH6 G1ORC6 ECAT0. P1_RXD3B P14.15 VADC. G1CH7 G1ORC7 ECAT0. P1_RX_DVB P15.2 ECAT0. P1_RX_ERRB P15.3 ECAT0. P1_LINKB P15.8 P15.9 HIB_IO_0 HIBOUT WWDT. SERVICE_OUT WAKEUPA HIB_IO_1 HIBOUT WWDT. SERVICE_OUT WAKEUPB ETH0. CLK_RMIIC ETH0. CLKRXC ETH0. CRS_DVC ETH0. RXDVC 24 USB_DP USB_DM TMS DB.TCK/ SWCLK DB.TMS/ SWDIO PORST XTAL1 U0C0. DX0F U0C1. DX0F U1C0. DX0F U1C1. DX0F XTAL2 RTC_XTAL1 ERU0. 1B1 RTC_XTAL2 XMC4300 XMC4000 Family V1.0, 2016-02 Subject to Agreement on the Use of Product Information TCK XMC4300 XMC4000 Family 2.3 Power Connection Scheme Figure 5. shows a reference power connection scheme for the XMC4300. XMC4000 VBAT Hibernate domain 2.1...3.6 V Hibernate control Retention Memory RTC 32 kHz Clock GND M x VDDC Core Domain 100 nF x M Dig. Peripherals GPIOs 10 µF x 1 CPU RAMs Level shift. GND 3.3V N x VDDP 100 nF x N EVR FLASH VSS 10 µF x 1 Exp. Die Pad VSS GND Reference VAREF 100 nF VAGND 3.3V AGND 100 nF PAD Domain Analog Domain ADC DAC Out-of-range comparator VDDA VSSA GND Figure 5 Power Connection Scheme Every power supply pin needs to be connected. Different pins of the same supply need also to be externally connected. As example, all VDDP pins must be connected externally to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each supply pin against VSS. An additional 10 µF capacitor is connected to the VDDP nets and an additional 10 uF capacitor to the VDDC nets. Data Sheet 25 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family The XMC4300 has a common ground concept, all VSS, VSSA and VSSO pins share the same ground potential. In packages with an exposed die pad it must be connected to the common ground as well. VAGND is the low potential to the analog reference VAREF. Depending on the application it can share the common ground or have a different potential. In devices with shared VDDA/VAREF and VSSA/VAGND pins the reference is tied to the supply. Some analog channels can optionally serve as “Alternate Reference”; further details on this operating mode are described in the Reference Manual. When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g. battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP. Data Sheet 26 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3 Electrical Parameters Attention: All parameters in this chapter are preliminary target values and may change based on characterization results. 3.1 General Parameters 3.1.1 Parameter Interpretation The parameters listed in this section partly represent the characteristics of the XMC4300 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are marked with a two-letter abbreviation in column “Symbol”: • • CC Such parameters indicate Controller Characteristics, which are a distinctive feature of the XMC4300 and must be regarded for system design. SR Such parameters indicate System Requirements, which must be provided by the application system in which the XMC4300 is designed in. Data Sheet 27 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.1.2 Absolute Maximum Ratings Stresses above the values listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 12 Absolute Maximum Rating Parameters Parameter Symbol Values Min. Typ. Max. – 150 °C – − 150 °C – – 4.3 V – – VDDP + 1.0 or max. 4.3 V whichever is lower VAIN -1.0 – VAREF SR IIN SR -10 – VDDP + 1.0 or max. 4.3 V whichever is lower +10 mA +25 mA +100 mA TST SR -65 Junction temperature TJ SR -40 Voltage at 3.3 V power supply VDDP SR – pins with respect to VSS Voltage on any Class A and VIN SR -1.0 Storage temperature dedicated input pin with respect to VSS Voltage on any analog input pin with respect to VAGND Input current on any pin during overload condition Unit Note / Test Con dition Absolute maximum sum of all ΣIIN input circuit currents for one port group during overload condition1) SR -25 Absolute maximum sum of all ΣIIN input circuit currents during overload condition SR -100 – – 1) The port groups are defined in Table 16. Figure 6 explains the input voltage ranges of VIN and VAIN and its dependency to the supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the overload conditions in Section 3.1.3. Data Sheet 28 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters V V 4.3 VDDP + 1.0 VDDP A B Figure 6 3.1.3 V SS VSS -1.0 -1.0 A Abs. max. input voltage VIN with VDDP > 3.3 V B Abs. max. input voltage VIN with VDDP ≤ 3.3 V Absolute Maximum Input Voltage Ranges Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification. Table 13 defines overload conditions that will not cause any negative reliability impact if all the following conditions are met: • • full operation life-time is not exceeded Operating Conditions are met for – pad supply levels (VDDP or VDDA) – temperature If a pin current is outside of the Operating Conditions but within the overload conditions, then the parameters of this pin as stated in the Operating Conditions can no longer be guaranteed. Operation is still possible in most cases but with relaxed parameters. Note: An overload condition on one or more pins does not require a reset. Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery. Data Sheet 29 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 13 Overload Parameters Parameter Symbol Min. Values Typ. Max. Unit Note / Test Condition -5 – 5 mA Input current on any port pin during overload condition IOV SR Absolute sum of all input circuit currents for one port group during overload condition1) IOVG SR – – 20 mA – – 20 mA Absolute sum of all input circuit currents during overload condition IOVS SR – – 80 mA Σ|IOVx|, for all IOVx < 0 mA Σ|IOVx|, for all IOVx > 0 mA ΣIOVG 1) The port groups are defined in Table 16. Figure 7 shows the path of the input currents during overload via the ESD protection structures. The diodes against VDDP and ground are a simplified representation of these ESD protection structures. VDDP VDDP Pn.y IOVx GND ESD Figure 7 GND Pad Input Overload Current via ESD structures Table 14 and Table 15 list input voltages that can be reached under overload conditions. Note that the absolute maximum input voltages as defined in the Absolute Maximum Ratings must not be exceeded during overload. Data Sheet 30 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 14 Pad Type A1 / A1+ A2 AN/DIG_IN Table 15 Pad Type A1 / A1+ A2 AN/DIG_IN Table 16 PN-Junction Characterisitics for positive Overload IOV = 5 mA, TJ = -40 °C VIN = VDDP + 1.0 V VIN = VDDP + 0.7 V VIN = VDDP + 1.0 V PN-Junction Characterisitics for negative Overload IOV = 5 mA, TJ = -40 °C VIN = VSS - 1.0 V VIN = VSS - 0.7 V VIN = VDDP - 1.0 V IOV = 5 mA, TJ = 150 °C VIN = VSS - 0.75 V VIN = VSS - 0.6 V VIN = VDDP - 0.75 V Port Groups for Overload and Short-Circuit Current Sum Parameters Group Pins 1 P0.[12:0], P3.[6:0] 2 P14.[15:0], P15.[9:2] 3 P2.[15:0], P5.[7:0] 4 P1.[15:0], P4.[1:0] Data Sheet IOV = 5 mA, TJ = 150 °C VIN = VDDP + 0.75 V VIN = VDDP + 0.6 V VIN = VDDP + 0.75 V 31 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.1.4 Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and their basic characteristics. Table 17 Pad Driver and Pad Classes Overview Class Power Type Supply Sub-Class Speed Grade Load A A1 (e.g. GPIO) 6 MHz 100 pF No A1+ (e.g. serial I/Os) 25 MHz 50 pF Series termination recommended A2 (e.g. ext. Bus) 80 MHz 15 pF Series termination recommended 3.3 V LVTTL I/O Termination V VDDP F E e oltag igh V ut H Outp D C B VOH A VOL w ut Lo Outp ge Volta VSS t Strong – sharp drive strength D B Strong – medium drive strength E Medium drive strength C Strong – soft drive strength F Weak drive strength A A B C C Figure 8 D E F Class A2 Pads E F Class A1+ Pads E F Class A1 Pads Strong – slow drive strength Output Slopes with different Pad Driver Modes Figure 8 is a qualitative display of the resulting output slope performance with different output driver modes. The detailed input and output characteristics are listed in Section 3.2.1. Data Sheet 32 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.1.5 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation and reliability of the XMC4300. All parameters specified in the following sections refer to these operating conditions, unless noted otherwise. Table 18 Operating Conditions Parameters Parameter Symbol Values Min. Note / Test Condition 85 °C Temp. Range F − 125 °C Temp. Range K 3.3 3.63 2) V 1.3 − − − Max. SR -40 − -40 Ambient Temperature TA Digital supply voltage VDDP SR 3.131) VDDC −1) Core Supply Voltage Unit Typ. V CC Digital ground voltage ADC analog supply voltage VSS SR 0 VDDA SR 3.0 Analog ground voltage for VSSA SR -0.1 Generated internally V 2) 3.3 3.6 V 0 0.1 V − 3.63 V − 144 MHz − 5 mA VDDA Battery Supply Voltage for VBAT SR 1.953) Hibernate Domain System Frequency Short circuit current of digital outputs fSYS SR − ISC SR -5 Absolute sum of short circuit currents per pin group4) ΣISC_PG SR − − 20 mA Absolute sum of short circuit currents of the device ΣISC_D SR − − 100 mA When VDDP is supplied VBAT has to be supplied as well. 1) See also the Supply Monitoring thresholds, Section 3.3.2. 2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime. 3) To start the hibernate domain it is required that VBAT ≥ 2.1 V, for a reliable start of the oscillation of RTC_XTAL in crystal mode it is required that VBAT ≥ 3.0 V. 4) The port groups are defined in Table 16. Data Sheet 33 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2 DC Parameters 3.2.1 Input/Output Pins The digital input stage of the shared analog/digital input pins is identical to the input stage of the standard digital input/output pins. The Pull-up on the PORST pin is identical to the Pull-up on the standard digital input/output pins. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 19 Standard Pad Parameters Parameter Symbol Pull-Up current Unit − 10 pF |IPDL| SR 150 − μA 1) − 10 μA 2) |IPUH| SR − 10 μA 100 − μA − V HYSA 0.1 × CC VDDP PORST spike filter always blocked pulse duration tSF1 CC − 10 ns PORST spike filter pass-through pulse duration tSF2 CC 100 − ns PORST pull-down current |IPPD| CC 13 − mA Input Hysteresis for pads of all A classes3) Note / Test Condition Max. Pin capacitance (digital CIO CC inputs/outputs) Pull-down current Values Min. VIN ≥ 0.6 × VDDP VIN ≤ 0.36 × VDDP 2) VIN ≥ 0.6 × VDDP 1) VIN ≤ 0.36 × VDDP VIN = 1.0 V 1) Current required to override the pull device with the opposite logic level (“force current”). With active pull device, at load currents between force and keep current the input state is undefined. 2) Load current at which the pull device still maintains the valid logic level (“keep current”). With active pull device, at load currents between force and keep current the input state is undefined. 3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise. Data Sheet 34 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters V VDDP XMC4000 IN IPDL A IPDL ≥ 150 μA B IPDL ≤ 10 μA A Valid High 0.6 x VDDP Invalid digital input 0.36 x VDDP B Valid Low GND VSS Pull-down active V VDDP VDDP B Valid High 0.6 x VDDP B IN XMC4000 IPUH A IPUH ≤ 10 μA Invalid digital input 0.36 x VDDP IPUH ≥ 100 μA A Valid Low VSS Pull-up active Figure 9 Pull Device Input Characteristics Figure 9 visualizes the input characteristics with an active internal pull device: • • in the cases “A” the internal pull device is overridden by a strong external driver; in the cases “B” the internal pull device defines the input logical state against a weak external load. Data Sheet 35 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 20 Standard Pads Class_A1 Parameter Symbol Values Min. Input leakage current Input high voltage Input low voltage Output high voltage, POD1) = weak IOZA1 CC VIHA1 SR VILA1 SR VOHA1 CC Output high voltage, POD1) = medium Output low voltage VOLA1 Unit Max. nA Note / Test Condition 0 V ≤ VIN ≤ VDDP -500 500 0.6 × VDDP max. 3.6 V -0.3 VDDP + 0.3 V 0.36 × VDDP V VDDP - 0.4 − V 2.4 − V VDDP - 0.4 − V IOH ≥ -400 μA IOH ≥ -500 μA IOH ≥ -1.4 mA IOH ≥ -2 mA IOL ≤ 500 μA; 2.4 − V − 0.4 V POD1) = weak CC − 0.4 V IOL ≤ 2 mA; POD1) = medium tFA1 CC Fall time tRA1 CC Rise time − 150 ns CL = 20 pF; POD1) = weak − 50 ns CL = 50 pF; POD1) = medium − 150 ns CL = 20 pF; POD1) = weak − 50 ns CL = 50 pF; POD1) = medium Unit Note / Test Condition μA 0 V ≤ VIN ≤ VDDP 1) POD = Pin Out Driver Table 21 Standard Pads Class_A1+ Parameter Symbol Values Input leakage current IOZA1+ CC -1 VIHA1+ SR 0.6 × VDDP VILA1+ SR -0.3 Min. Input high voltage Input low voltage Data Sheet Max. 36 1 VDDP + 0.3 V 0.36 × VDDP V max. 3.6 V V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 21 Standard Pads Class_A1+ Parameter Symbol Values Min. Unit Note / Test Condition IOH ≥ -400 μA IOH ≥ -500 μA IOH ≥ -1.4 mA IOH ≥ -2 mA IOH ≥ -1.4 mA IOH ≥ -2 mA IOL ≤ 500 μA; Max. VOHA1+ VDDP - 0.4 − V CC 2.4 − V Output high voltage, POD1) = medium VDDP - 0.4 − V 2.4 − V Output high voltage, POD1) = strong VDDP - 0.4 − V 2.4 − V − 0.4 V Output high voltage, POD1) = weak Output low voltage VOLA1+ POD1) = weak CC − 0.4 V IOL ≤ 2 mA; POD1) = medium − 0.4 V IOL ≤ 2 mA; POD1) = strong Fall time tFA1+ CC − 150 ns CL = 20 pF; POD1) = weak − 50 ns CL = 50 pF; POD1) = medium − 28 ns CL = 50 pF; POD1) = strong; edge = slow − 16 ns CL = 50 pF; POD1) = strong; edge = soft; Rise time tRA1+ CC − 150 ns CL = 20 pF; POD1) = weak − 50 ns CL = 50 pF; POD1) = medium − 28 ns CL = 50 pF; POD1) = strong; edge = slow − 16 ns CL = 50 pF; POD1) = strong; edge = soft 1) POD = Pin Out Driver Data Sheet 37 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 22 Standard Pads Class_A2 Parameter Symbol Input Leakage current IOZA2 CC Input high voltage VIHA2 Values Unit Note / Test Condition Min. Max. -6 6 μA 0 V ≤ VIN < 0.5*VDDP - 1 V; 0.5*VDDP + 1 V <VIN ≤ VDDP -3 3 μA 0.5*VDDP - 1 V < VIN < 0.5*VDDP +1V 0.6 × VDDP VDDP + 0.3 V max. 3.6 V SR Input low voltage 0.36 × VILA2 SR -0.3 V VDDP VOHA2 VDDP - 0.4 − V CC 2.4 − V Output high voltage, POD = medium VDDP - 0.4 − V 2.4 − V Output high voltage, POD = strong VDDP - 0.4 − V 2.4 − V − 0.4 V IOH ≥ -400 μA IOH ≥ -500 μA IOH ≥ -1.4 mA IOH ≥ -2 mA IOH ≥ -1.4 mA IOH ≥ -2 mA IOL ≤ 500 μA Output low voltage, POD = medium − 0.4 V IOL ≤ 2 mA Output low voltage, POD = strong − 0.4 V IOL ≤ 2 mA Output high voltage, POD = weak Output low voltage, POD = weak Data Sheet VOLA2 CC 38 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 22 Parameter Fall time Rise time Data Sheet Standard Pads Class_A2 Symbol tFA2 CC Values Unit Note / Test Condition 150 ns CL = 20 pF; POD = weak − 50 ns CL = 50 pF; POD = medium − 3.7 ns CL = 50 pF; POD = strong; edge = sharp − 7 ns CL = 50 pF; POD = strong; edge = medium − 16 ns CL = 50 pF; POD = strong; edge = soft 150 ns CL = 20 pF; POD = weak − 50 ns CL = 50 pF; POD = medium − 3.7 ns CL = 50 pF; POD = strong; edge = sharp − 7.0 ns CL = 50 pF; POD = strong; edge = medium − 16 ns CL = 50 pF; POD = strong; edge = soft Min. Max. − tRA2 CC − 39 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 23 HIB_IO Class_A1 special Pads Parameter Input leakage current Symbol IOZHIB Values Unit Note / Test Condition 500 nA 0 V ≤ VIN ≤ VBAT 0.6 × VBAT VBAT + 0.3 V max. 3.6 V -0.3 0.36 × VBAT V Min. Max. -500 CC Input high voltage VIHHIB SR Input low voltage VILHIB SR HYSHIB 0.1 × VBAT − V CC 0.06 × − V VBAT ≥ 3.13 V VBAT < 3.13 V Output high voltage, POD1) = medium VOHHIB VBAT VBAT - 0.4 − V IOH ≥ -1.4 mA Output low voltage VOLHIB − 0.4 V IOL ≤ 2 mA tFHIB CC − 50 ns 100 ns 50 ns 100 ns VBAT ≥ 3.13 V CL = 50 pF VBAT < 3.13 V CL = 50 pF VBAT ≥ 3.13 V CL = 50 pF VBAT < 3.13 V CL = 50 pF Input Hysteresis for HIB_IO pins1) CC CC Fall time − Rise time tRHIB CC − − 1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise. Data Sheet 40 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.2 Analog to Digital Converters (VADC) Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 24 VADC Parameters (Operating Conditions apply) Parameter Symbol Analog reference voltage5) VAREF SR Analog reference ground5) VAGND SR Analog reference voltage range2)5) VAREF VAGND Values Unit Min. Typ. Max. VAGND − +1 VDDA + V 0.051) VSSM - − VAREF - V 0.05 1 − 1 Note / Test Condition VDDA + V 0.1 SR Analog input voltage Input leakage at analog inputs3) VAIN SR IOZ1 CC VAGND − VDDA V -100 − 200 nA 0.03 × VDDA < VAIN < 0.97 × VDDA -500 − 100 nA 0 V ≤ VAIN ≤ 0.03 × VDDA -100 − 500 nA 0.97 × VDDA ≤ VAIN ≤ VDDA Input leakage current at VAREF IOZ2 CC -1 − 1 μA 0 V ≤ VAREF ≤ VDDA Input leakage current at VAGND IOZ3 CC -1 − 1 μA 0 V ≤ VAGND ≤ VDDA Internal ADC clock fADCI CC 2 CAINSW − − 36 MHz VDDA = 3.3 V 4 6.5 pF − 12 20 pF CAREFSW − 15 30 pF 20 40 pF Switched capacitance at the analog voltage inputs4) CC Total capacitance of an analog input Switched capacitance at the positive reference voltage input5)6) CAINTOT CC CC Total capacitance of the CAREFTOT − voltage reference inputs5) CC Data Sheet 41 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 24 VADC Parameters (Operating Conditions apply) Parameter Symbol Values Min. Total Unadjusted Error Differential Non-Linearity Error8) 8) Gain Error Unit Note / Test Condition 12-bit resolution; VDDA = 3.3 V; VAREF = VDDA7) Typ. Max. − 4 LSB − 3 LSB -4 − 4 LSB EAINLCC -3 EAOFF -4 − 3 LSB − 4 LSB − 1.5 2 mA during conversion VDDP = 3.6 V, TJ = 150 oC − 30 − pC 0 V ≤ VAREF ≤ VDDA9) 600 1 200 Ohm 180 550 900 Ohm − 700 1 700 Ohm TUE CC -4 EADNL -3 CC EAGAIN CC Integral Non-Linearity8) Offset Error 8) CC Worst case ADC VDDA power supply current per active converter IDDAA Charge consumption on VAREF per conversion5) QCONV ON resistance of the analog input path RAIN CC − CC CC ON resistance for the ADC RAIN7T test (pull down for AIN7) CC Resistance of the reference voltage input path RAREF CC 1) A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot). 2) If the analog reference voltage is below VDDA, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k. 3) The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The numerical values defined determine the characteristic points of the given continuous linear approximation they do not define step function (see Figure 12). 4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment. Because of the parasitic elements, the voltage measured at AINx can deviate from VAREF/2. 5) Applies to AINx, when used as alternate reference input. 6) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead, smaller capacitances are successively switched to the reference voltage. 7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16. Never less than ±1 LSB. 8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE. 9) The resulting current for a conversion can be calculated with IAREF = QCONV / tc. The fastest 12-bit post-calibrated conversion of tc = 459 ns results in a typical average current of IAREF = 65.4 µA. Data Sheet 42 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters V VDDA + 0.05 VDDA Precise conversion range (12 bit) VAREF e.g. VAREF = 4/5 of VDDA Valid V AREF Conversion error increases by 5/4 VAGND + 1 Minimum VAREF - VAGND is 1 V VAGND VSSA t Figure 10 VADC Reference Voltage Range The power-up calibration of the VADC requires a maximum number of 4 352 fADCI cycles. REXT VAIN = Analog Input Circuitry RAIN, On ANx CEXT CAINSW CAINTOT - CAINSW VAGNDx RAIN7T Reference Voltage Input Circuitry RAREF, On VAREFx VAREF CAREFTOT - CAREFSW CAREFSW VAGNDx Analog_InpRefDiag Figure 11 Data Sheet VADC Input Circuits 43 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters IOZ1 Single ADC Input 500 nA 200 nA 100 nA V IN [% VD D A] -100 nA 3% 97% 100% -500 nA ADC-Leakage.vsd Figure 12 VADC Analog Input Leakage Current Conversion Time Table 25 Conversion Time (Operating Conditions apply) Parameter Symbol Values Conversion time tC • • • Unit Note CC 2 × TADC + (2 + N + STC + PC +DM) × TADCI μs N = 8, 10, 12 for N-bit conversion TADC = 1 / fPERIPH TADCI = 1 / fADCI STC defines additional clock cycles to extend the sample time PC adds two cycles if post-calibration is enabled DM adds one cycle for an extended conversion time of the MSB Conversion Time Examples System assumptions: fADC = 144 MHz i.e. tADC = 6.9 ns, DIVA = 3, fADCI = 36 MHz i.e. tADCI = 27.8 ns According to the given formulas the following minimum conversion times can be achieved (STC = 0, DM = 0): 12-bit post-calibrated conversion (PC = 2): tCN12C = (2 + 12 + 2) × tADCI + 2 × tADC = 16 × 27.8 ns + 2 × 6.9 ns = 459 ns 12-bit uncalibrated conversion: tCN12 = (2 + 12) × tADCI + 2 × tADC = 14 × 27.8 ns + 2 × 6.9 ns = 403 ns 10-bit uncalibrated conversion: tCN10 = (2 + 10) × tADCI + 2 × tADC = 12 × 27.8 ns + 2 × 6.9 ns = 348 ns 8-bit uncalibrated: tCN8 = (2 + 8) × tADCI + 2 × tADC = 10 × 27.8 ns + 2 × 6.9 ns = 292 ns Data Sheet 44 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.3 Digital to Analog Converters (DAC) Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 26 DAC Parameters (Operating Conditions apply) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition per active DAC channel, without load currents of DAC outputs RMS supply current IDD − 2.5 4 mA Resolution RES CC − fURATE_ACC − 12 − Bit Update rate 2 Msam data rate, where ple/s DAC can follow 64 LSB code jumps to ± 1LSB accuracy Update rate fURATE_F CC − 5 Msam data rate, where ple/s DAC can follow 64 LSB code jumps to ± 4 LSB accuracy Settling time tSETTLE CC − 1 2 μs Slew rate SR CC VOUT_MIN 2 5 − V/μs − 0.3 − V code value unsigned: 000H; signed: 800H − 2.5 − V code value unsigned: FFFH; signed: 7FFH CC -5.5 ±2.5 5.5 LSB RL ≥ 5 kOhm, CL ≤ 50 pF CC -2 ±1 2 LSB RL ≥ 5 kOhm, CL ≤ 50 pF Minimum output voltage Maximum output voltage CC VOUT_MAX CC Integral non-linearity INL Differential nonlinearity Data Sheet CC DNL 45 at full scale jump, output voltage reaches target value ± 20 LSB V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 26 DAC Parameters (Operating Conditions apply) (cont’d) Parameter Symbol Values Min. Offset error Gain error Startup time 3dB Bandwidth of Output Buffer Output sourcing current Typ. Unit Max. Note / Test Condition EDOFF CC EDG_IN CC -6.5 tSTARTUP CC − -1.5 3 % 15 30 μs time from output enabling till code valid ±16 LSB fC1 5 − MHz verified by design -30 − mA − 0.6 − mA CC 2.5 IOUT_SOURCE − ±20 mV CC Output sinking current IOUT_SINK Output resistance ROUT RL CL CC − 50 − Ohm SR 5 − − kOhm SR − − 50 pF Signal-to-Noise Ratio SNR CC − 70 − dB examination bandwidth < 25 kHz Total Harmonic Distortion THD CC − 70 − dB examination bandwidth < 25 kHz Power Supply Rejection Ratio PSRR CC − 56 − dB to VDDA verified by design Load resistance Load capacitance CC Conversion Calculation Unsigned: DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) Signed: DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048 Data Sheet 46 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters DAC output VOUT_MAX +/- 4LSB +/- 1LSB 64 LSBs 64 LSBs VOUT_MIN fURATE_A (max) fURATE_F (max) DAC output 20 LSBs VOUT_MAX tSETTLE tSETTLE 20 LSBs VOUT_MIN Figure 13 Data Sheet DAC Conversion Examples 47 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.4 Out-of-Range Comparator (ORC) The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service request trigger (GxORCOUTy). Note: These parameters are not subject to production test, but verified by design and/or characterization. The parameters in Table 27 apply for the maximum reference voltage VAREF = VDDA + 50 mV. Table 27 ORC Parameters (Operating Conditions apply) Parameter Symbol Values Min. DC Switching Level VODC Hysteresis CC 100 Max. 125 210 mV − VODC mV CC 50 − 450 ns 45 − 105 ns − − ns − − ns VOHYS CC 50 Detection Delay of a tODD persistent Overvoltage Unit Note / Test Condition Typ. Always detected Overvoltage Pulse tOPDD CC 440 Never detected Overvoltage Pulse tOPDN CC − − 45 ns − − 30 ns Release Delay tORD tOED CC 65 − 105 ns CC − 100 200 ns Enable Delay 90 VAIN ≥ VAREF + VODC VAIN ≥ VAREF + 210 mV VAIN ≥ VAREF + 400 mV VAIN ≥ VAREF + 210 mV VAIN ≥ VAREF + 400 mV VAIN ≥ VAREF + 210 mV VAIN ≥ VAREF + 400 mV VAIN ≤ VAREF 1) Always the standard VADC reference, alternate references do not apply to the ORC. Data Sheet 48 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family VODC VOHYS Electrical Parameters VAREF VSS GxORCy GxORCOUTy tODD Figure 14 tORD GxORCOUTy Trigger Generation VAIN (V) T < tOPDN tOPDN < T < tOPDD T > tOPDD VAREF + 400 mV T < tOPDN VAREF + 200 mV tOPDN < T < tOPDD T > tOPDD T > tOPDN VAREF + 100 mV VAREF Never detected Overvoltage Pulse (Too low) Never Overvoltage detected may be Overvoltage detected Pulse (level uncertain) (Too short) Overvoltage may be detected Always detected Overvoltage Pulse Never detected Overvoltage Pulse (Too short) Overvoltage may be detected Always detected Overvoltage Pulse t Figure 15 Data Sheet ORC Detection Ranges 49 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.5 Die Temperature Sensor The Die Temperature Sensor (DTS) measures the junction temperature TJ. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 28 Die Temperature Sensor Parameters Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition − 150 °C Linearity Error ΔTLE CC − (to the below defined formula) ±1 − °C per ΔTJ ≤ 30 °C ΔTOE CC − ±6 − °C ΔTOE = TJ - TDTS tM CC − tTSST SR − − 100 μs − 10 μs Temperature sensor range Offset Error Measurement time Start-up time after reset inactive TSR SR -40 VDDP ≤ 3.3 V1) 1) At VDDP_max = 3.63 V the typical offset error increases by an additional ΔTOE = ±1 °C. The following formula calculates the temperature measured by the DTS in [oC] from the RESULT bit field of the DTSSTAT register. Temperature TDTS = (RESULT - 605) / 2.05 [°C] This formula and the values defined in Table 28 apply with the following calibration values: • • DTSCON.BGTRIM = 8H DTSCON.REFTRIM = 4H Data Sheet 50 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.6 USB OTG Interface DC Characteristics The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification and the OTG Specification Rev. 1.3. High-Speed Mode is not supported. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 29 USB OTG VBUS and ID Parameters (Operating Conditions apply) Parameter Symbol Values Min. Unit Typ. Max. VBUS input voltage range VIN CC 0.0 − 5.25 V A-device VBUS valid threshold VB1 CC 4.4 − − V A-device session valid VB2 threshold CC 0.8 − 2.0 V B-device session valid VB3 threshold CC 0.8 − 4.0 V B-device session end threshold VB4 CC 0.2 − 0.8 V VBUS input resistance to ground RVBUS_IN − 100 kOhm − − Ohm − − Ohm 14 − 25 kOhm − − 150 μA 40 CC RVBUS_PU 281 B-device VBUS pullup resistor CC B-device VBUS pulldown resistor CC USB.ID pull-up resistor CC VBUS input current IVBUS_IN RVBUS_PD 656 RUID_PU CC Data Sheet Note / Test Condition 51 Pull-up voltage = 3.0 V 0 V ≤ VIN ≤ 5.25 V: TAVG = 1 ms V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 30 USB OTG Data Line (USB_DP, USB_DM) Parameters (Operating Conditions apply) Parameter Symbol Values Min. Unit Typ. Max. Note / Test Condition SR − − 0.8 V SR 2.0 − − V Input high voltage (floating) 1) VIHZ SR 2.7 − 3.6 V Differential input sensitivity VDIS CC 0.2 − − V Differential common mode range VCM CC 0.8 − 2.5 V Output low voltage VOL CC 0.0 − 0.3 V 1.5 kOhm pullup to 3.6 V Output high voltage VOH CC 2.8 − 3.6 V 15 kOhm pulldown to 0 V DP pull-up resistor (idle RPUI CC 900 bus) − 1 575 Ohm Input low voltage Input high voltage (driven) VIL VIH DP pull-up resistor (upstream port receiving) RPUA CC 1 425 − 3 090 Ohm DP, DM pull-down resistor RPD CC 14.25 − 24.8 kOhm Input impedance DP, DM ZINP CC 300 − − kOhm 0 V ≤ VIN ≤ VDDP − 44 Ohm Driver output resistance ZDRV CC 28 DP, DM 1) Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at Bconnector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM. Data Sheet 52 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.7 Oscillator Pins Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal or ceramic resonator supplier. Note: These parameters are not subject to production test, but verified by design and/or characterization. The oscillator pins can be operated with an external crystal (see Figure 16) or in direct input mode (see Figure 17). XTAL1 f OSC GND XTAL2 Damping resistor may be needed for some crystals V VPPX_min VPPX VPPX_min ≤ VPPX ≤ VPPX_max tOSCS t Figure 16 Data Sheet Oscillator in Crystal Mode 53 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters External Clock Source Direct Input Mode XTAL1 not connected XTAL2 V VIHBX_max Inpu ltage h Vo t Hig tH Inpu igh V e oltag VIHBX_min VILBX_max VSS VILBX_min g Volta t Low Inpu e t Figure 17 Data Sheet Oscillator in Direct Input Mode 54 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 31 OSC_XTAL Parameters Parameter Symbol Values Min. Input frequency Unit Note / Test Condition Typ. Max. fOSC SR 4 − 40 MHz Direct Input Mode selected 4 − 25 MHz External Crystal Mode selected − − 10 ms Oscillator start-up time1)2) tOSCS Input voltage at XTAL1 VIX SR -0.5 CC − VDDP + V 0.5 Input amplitude (peakto-peak) at XTAL12)3) Input high voltage at XTAL14) VPPX SR 0.4 × VDDP VIHBXSR 1.0 − VDDP + V 1.0 − VDDP + V 0.5 VILBX SR -0.5 − 0.4 V Input leakage current at IILX1 CC -100 XTAL1 − 100 nA Input low voltage at XTAL14) Oscillator power down 0 V ≤ VIX ≤ VDDP 1) tOSCS is defined from the moment the oscillator is enabled wih SCU_OSCHPCTRL.MODE until the oscillations reach an amplitude at XTAL1 of 0.4 * VDDP. 2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers. 3) If the shaper unit is enabled and not bypassed. 4) If the shaper unit is bypassed, dedicated DC-thresholds have to be met. Data Sheet 55 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 32 RTC_XTAL Parameters Parameter Symbol Values Min. Input frequency Oscillator start-up time1)2)3) fOSC SR − tOSCS − Typ. Unit Max. 32.768 − kHz − 5 s CC Input voltage at RTC_XTAL1 VIX SR -0.3 − VBAT + V Input amplitude (peakto-peak) at RTC_XTAL12)4) VPPX SR 0.4 − − Input high voltage at RTC_XTAL15) VIHBXSR 0.6 × VBAT VILBX SR -0.3 − VBAT + V Input low voltage at RTC_XTAL15) Input Hysteresis for RTC_XTAL15)6) Note / Test Condition 0.3 V 0.3 − 0.36 × V VBAT VHYSX 0.1 × CC VBAT − 0.03 × V 3.0 V ≤ − V VBAT < 3.6 V VBAT < 3.0 V 100 nA VBAT Input leakage current at IILX1 CC -100 RTC_XTAL1 − Oscillator power down 0 V ≤ VIX ≤ VBAT 1) tOSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the oscillations reach an amplitude at RTC_XTAL1 of 400 mV. 2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and amplitude as recommended and specified by crystal suppliers. 3) For a reliable start of the oscillation in crystal mode it is required that VBAT ≥ 3.0 V. A running oscillation is maintained across the full VBAT voltage range. 4) If the shaper unit is enabled and not bypassed. 5) If the shaper unit is bypassed, dedicated DC-thresholds have to be met. 6) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not be guaranteed that it suppresses switching due to external system noise. Data Sheet 56 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.8 Power Supply Current The total power supply current defined below consists of a leakage and a switching component. Application relevant values are typically lower than those given in the following tables, and depend on the customer's system operating conditions (e.g. thermal connection or used application configurations). Note: These parameters are not subject to production test, but verified by design and/or characterization. If not stated otherwise, the operating conditions for the parameters in the following table are: VDDP = 3.3 V, TA = 25 oC Table 33 Power Supply Parameters Parameter Symbol Values Min. 1)11) Active supply current Peripherals enabled Frequency: fCPU / fPERIPH / fCCU in MHz Unit Note / Test Condition Typ. Max. IDDPA CC − 135 − − 125 − 144 / 72 / 72 − 97 − 72 / 72 / 144 − 80 − 24 / 24 / 24 − 68 − 1/1/1 mA 144 / 144 / 144 Active supply current Code execution from RAM Flash in Sleep mode IDDPA CC − 108 − − 98 − Active supply current2) Peripherals disabled Frequency: fCPU / fPERIPH / fCCU in MHz IDDPA CC − 86 − − 85 − 144 / 72 / 72 − 70 − 72 / 72 / 144 − 55 − 24 / 24 / 24 − 50 − 1/1/1 IDDPS CC − 127 − − 115 − 144 / 72 / 72 − 93 − 72 / 72 / 144 − 57 − 24 / 24 / 24 − 47 − 1/1/1 − 48 − 100 / 100 / 100 3) Sleep supply current Peripherals enabled Frequency: fCPU / fPERIPH / fCCU in MHz fCPU / fPERIPH / fCCU in kHz Data Sheet 57 mA 144 / 144 / 144 144 / 72 / 72 mA mA 144 / 144 / 144 144 / 144 / 144 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 33 Power Supply Parameters Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. IDDPS CC − 77 − − 76 − 144 / 72 / 72 − 65 − 72 / 72 / 144 − 53 − 24 / 24 / 24 − 46 − 1/1/1 − 47 − 100 / 100 / 100 IDDPD CC − 11 − − 7.0 − 4/4/4 − 6.6 − 1/1/1 fCPU / fPERIPH / fCCU in kHz − 7.6 − 100 / 100 / 100 Hibernate supply current RTC on7) IDDPH CC − 8.7 − − 6.5 − − 5.7 − Hibernate supply current RTC off8) IDDPH CC − 8.0 − − 6.0 − − 5.0 − Hibernate off9) IDDPH CC − 4.4 − − 3.5 − − 3.1 − Sleep supply current4) Peripherals disabled Frequency: fCPU / fPERIPH / fCCU in MHz fCPU / fPERIPH / fCCU in kHz Deep Sleep supply current5) Flash in Sleep mode Frequency: fCPU / fPERIPH / fCCU in MHz mA mA 144 / 144 / 144 24 / 24 / 24 6) μA μA μA VBAT = 3.3 V VBAT = 2.4 V VBAT = 2.0 V VBAT = 3.3 V VBAT = 2.4 V VBAT = 2.0 V VBAT = 3.3 V VBAT = 2.4 V VBAT = 2.0 V IDDPA CC − − VDDA power supply current IDDA CC − IDDP current at PORST Low IDDP_PORST − − −12) mA 5 10 mA VDDP = 3.3 V, TJ = 25 oC 13 55 mA VDDP = 3.6 V, TJ = 150 oC − 1.4 W VDDP = 3.6 V, TJ = 150 oC Worst case active supply current10) 250 mA 11) CC − Power Dissipation Data Sheet PDISS CC − 58 VDDP = 3.6 V, TJ = 150 oC V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 33 Power Supply Parameters Parameter Symbol Values Min. Unit Note / Test Condition Typ. Max. CC − 6 − cycles Wake-up time from Deep Sleep to Active mode − − − ms Defined by the wake-up of the Flash module, see Section 3.2.9 Wake-up time from Hibernate mode − − − ms Wake-up via power-on reset event, see Section 3.3.2 Wake-up time from Sleep to tSSA Active mode 1) CPU executing code from Flash, all peripherals idle. 2) CPU executing code from Flash. 3) CPU in sleep, all peripherals idle, Flash in Active mode. 4) CPU in sleep, Flash in Active mode. 5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM. 6) To wake-up the Flash from its Sleep mode, fCPU ≥ 1 MHz is required. 7) OSC_ULP operating with external crystal on RTC_XTAL 8) OSC_ULP off, Hibernate domain operating with OSC_SI clock 9) VBAT supplied, but Hibernate domain not started; for example state after factory assembly 10) Test Power Loop: fSYS = 144 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in 500kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE, DTS measurements and FPU calculations. The power consumption of each customer application will most probably be lower than this value, but must be evaluated separately. 11) IDDP decreases typically by approximately 5 mA when fSYS decreases by 10 MHz, at constant TJ 12) Sum of currents of all active converters (ADC and DAC) Data Sheet 59 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Peripheral Idle Currents Default test conditions: • • • • • fsys and derived clocks at 144 MHz VDDP = 3.3 V, Ta =25 °C all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit of the SCU) the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control Unit of the SCU no I/O activity The given values are a result of differential measurements with asserted and deasserted peripheral reset as well as disabled and enabled clock of the peripheral under test. The tested peripheral is left in the state after the peripheral reset is deasserted, no further initialisation or configuration is done. E.g. no timer is running in the CCUs, no communication active in the USICs, etc. Table 34 Peripheral Idle Currents Parameter Symbol Values Min. Unit Typ. Max. IPER CC − ≤ 0.3 − MultiCAN ERU LEDTSCU0 ETH CCU4x1), CCU8x1) − ≤ 1.0 − DAC (digital)2) − 1.3 − USICx SDMMC − 3.0 − VADC (digital)2) − 4.5 − DMA0, USB, EtherCAT − 6.0 − PORTS FCE WDT Note / Test Condition mA 1) Enabling the fCCU clock for the CCU4x/CCU8x modules adds approximately IPER = 4.8 mA, disregarding which and how many of those peripherals are enabled. 2) The current consumption of the analog components are given in the dedicated Data Sheet sections of the respective peripheral. Data Sheet 60 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.2.9 Flash Memory Parameters Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 35 Flash Memory Parameters Parameter Symbol Values Erase Time per 256 Kbyte Sector tERP CC − Min. Unit Typ. Max. 5 5.5 s Erase Time per 64 Kbyte tERP CC − Sector 1.2 1.4 s Erase Time per 16 Kbyte tERP CC − Logical Sector 0.3 0.4 s Program time per page1) tPRP CC − 5.5 11 ms − 15 ms − − μs Erase suspend delay tFL_ErSusp − Note / Test Condition CC Wait time after margin change tFL_Margin 10 Del CC − − 270 μs 22 − − ns For operation with 1 / fCPU < ta wait states must be configured2) Data Retention Time, Physical Sector3)4) tRET CC 20 − − years Max. 1000 erase/program cycles Data Retention Time, Logical Sector3)4) tRETL CC 20 − − years Max. 100 erase/program cycles Data Retention Time, tRTU CC 20 User Configuration Block (UCB)3)4) − − years Max. 4 erase/program cycles per UCB − − cycles Cycling distributed over life time5) Wake-up time Read access time Endurance on 64 Kbyte Physical Sector PS4 Data Sheet tWU CC ta CC NEPS4 10000 CC 61 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The reprogramming takes an additional time of 5.5 ms. 2) The following formula applies to the wait state configuration: FCON.WSPFLASH × (1 / fCPU) ≥ ta. 3) Storage and inactive time included. 4) Values given are valid for an average weighted junction temperature of TJ = 110°C. 5) Only valid with robust EEPROM emulation algorithm, equally cycling the logical sectors. For more details see the Reference Manual. Data Sheet 62 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3 AC Parameters 3.3.1 Testing Waveforms VD D P VSS 90% 90% 10% 10% tR tF AC_Rise-Fall-Times.vsd Figure 18 Rise/Fall Time Parameters VD D P VD D P / 2 Test Points VD D P / 2 VSS AC_TestPoints.vsd Figure 19 Testing Waveform, Output Delay VL OAD + 0.1V VL OAD - 0.1V Timing Reference Points VOH - 0.1V VOL + 0.1V AC_HighImp.vsd Figure 20 Data Sheet Testing Waveform, Output High Impedance 63 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.2 Power-Up and Supply Monitoring PORST is always asserted when VDDP and/or VDDC violate the respective thresholds. Note: These parameters are not subject to production test, but verified by design and/or characterization. VDDP VDDP XMC4000 RPORST (optional) PORST PORESET External reset trigger IPPD GND GND Figure 21 PORST Circuit Table 36 Supply Monitoring Parameters Parameter Supply Monitoring Symbol Values Min. Digital supply voltage reset VPOR CC threshold Unit Note / Test Condition 3) Typ. Max. 2.791) − 3.052) V Core supply voltage reset threshold VPV CC − − 1.17 V VDDP voltage to ensure defined pad states VDDPPA − 1.0 − V − − 2 μs 4) − 2.5 3.5 ms Time to the first user code instruction − 550 − μs Ramp up after power-on or after a reset triggered by a violation of VPOR or VPV CC tPR SR Startup time from power-on tSSW CC PORST rise time reset with code execution from Flash VDDC ramp up time tVCR CC 1) Minimum threshold for reset assertion. Data Sheet 64 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 2) Maximum threshold for reset deassertion. 3) The VDDP monitoring has a typical hysteresis of VPORHYS = 180 mV. 4) If tPR is not met, low spikes on PORST may be seen during start up (e.g. reset pulses generated by the supply monitoring due to a slow ramping VDDP). 3.3 V VPOR VD D P VD D PPA 1.3 V VDDC VPV tVCR PORST tPR t SSW Pads as programmed High-impedance or pull -device active Undefined Figure 22 3.3.3 Power-Up Behavior Power Sequencing While starting up and shutting down as well as when switching power modes of the system it is important to limit the current load steps. A typical cause for such load steps is changing the CPU frequency fCPU. Load steps exceeding the below defined values may cause a power on reset triggered by the supply monitor. Note: These parameters are not subject to production test, but verified by design and/or characterization. Data Sheet 65 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 37 Power Sequencing Parameters Parameter Symbol Values Unit Note / Test Condition 50 mA Load increase on VDDP Δt ≤ 10 ns − 150 mA Load decrease on VDDP Δt ≤ 10 ns − ±100 mV For maximum positive or negative load step − - μs Min. Typ. Max. Positive Load Step Current ΔIPLS SR - − Negative Load Step Current ΔINLS SR - VDDC Voltage Over- ΔVLS CC - / Undershoot from Load Step Positive Load Step Settling tPLSS SR 50 Time Negative Load Step Settling Time tNLSS SR 100 − - μs External Buffer Capacitor on VDDC CEXT SR - 10 - μF In addition C = 100 nF capacitor on each VDDC pin Positive Load Step Examples System assumptions: fCPU = fSYS, target frequency fCPU = 144 MHz, main PLL fVCO = 288 MHz, stepping done by K2 divider, tPLSS between individual steps: 24 MHz - 48 MHz - 72 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 4 - 3 - 2) 24 MHz - 48 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 3 - 2) 24 MHz - 72 MHz - 144 MHz (K2 steps 12 - 4 - 2) Data Sheet 66 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.4 Phase Locked Loop (PLL) Characteristics Note: These parameters are not subject to production test, but verified by design and/or characterization. Main and USB PLL Table 38 PLL Parameters Parameter Symbol Accumulated Jitter DP CC Duty Cycle1) PLL base frequency Values Unit Note / Test Condition Min. Typ. Max. − − ±5 ns accumulated over 300 cycles fSYS = 144 MHz DDC CC 46 50 54 % Low pulse to total period, assuming an ideal input clock source fPLLBASE 30 − 140 MHz − 16 MHz − 520 MHz − 400 μs CC VCO input frequency VCO frequency range PLL lock-in time fREF CC 4 fVCO CC 260 tL CC − 1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values. Data Sheet 67 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.5 Internal Clock Source Characteristics Note: These parameters are not subject to production test, but verified by design and/or characterization. Fast Internal Clock Source Table 39 Fast Internal Clock Parameters Parameter Nominal frequency Accuracy Symbol Values Unit Min. Typ. Max. fOFINC − 36.5 − MHz not calibrated CC − 24 − MHz calibrated ΔfOFI -0.5 − 0.5 % automatic calibration1)2) -15 − 15 % factory calibration, VDDP = 3.3 V -25 − 25 % no calibration, VDDP = 3.3 V -7 − 7 % Variation over voltage range3) 3.13 V ≤ VDDP ≤ 3.63 V 50 − μs CC Start-up time Note / Test Condition tOFIS CC − 1) Error in addition to the accuracy of the reference clock. 2) Automatic calibration compensates variations of the temperature and in the VDDP supply voltage. 3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory calibrated oscillator frequency. Data Sheet 68 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Slow Internal Clock Source Table 40 Slow Internal Clock Parameters Parameter Symbol Nominal frequency fOSI CC ΔfOSI Accuracy Values Unit Min. Typ. − 32.768 − Max. kHz -4 − % 4 CC Note / Test Condition VBAT = const. 0 °C ≤ TA ≤ 85 °C Start-up time Data Sheet -5 − 5 % -5 − 5 % -10 − 10 % 50 − μs tOSIS CC − 69 VBAT = const. TA < 0 °C or TA > 85 °C 2.4 V ≤ VBAT, TA = 25 °C 1.95 V ≤ VBAT < 2.4 V, TA = 25 °C V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.6 JTAG Interface Timing The following parameters are applicable for communication through the JTAG debug interface. The JTAG module is fully compliant with IEEE1149.1-2000. Note: These parameters are not subject to production test, but verified by design and/or characterization. Note: Operating conditions apply. Table 41 JTAG Interface Timing Parameters Parameter Symbol Min. Values Typ. Max. Unit Note / Test Condition t1 t2 t3 t4 t5 t6 SR 25 – – ns SR 10 – – ns SR 10 – – ns SR – – 4 ns SR – – 4 ns SR 6 – – ns t7 SR 6 – – ns TDO valid after TCK falling t8 edge1) (propagation delay) CC – – 13 ns CL = 50 pF 3 – – ns CL = 20 pF 2 – – ns TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TDI/TMS setup to TCK rising edge TDI/TMS hold after TCK rising edge TDO hold after TCK falling t18 CC edge1) TDO high imped. to valid from TCK falling edge1)2) t9 – – 14 ns CL = 50 pF TDO valid to high imped. from TCK falling edge1) t10 CC – – 13.5 ns CL = 50 pF CC 1) The falling edge on TCK is used to generate the TDO timing. 2) The setup time for TDO is given implicitly by the TCK cycle time. Data Sheet 70 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters t1 TCK 0.9 VD D P 0.1 VD D P 0.5 VD D P t2 t3 t4 t5 JTAG_TCK .vsd Figure 23 Test Clock Timing (TCK) TCK t6 t7 t6 t7 TMS TDI t9 t8 t10 TDO t18 JTAG_IO.vsd Figure 24 Data Sheet JTAG Timing 71 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.7 Serial Wire Debug Port (SW-DP) Timing The following parameters are applicable for communication through the SW-DP interface. Note: These parameters are not subject to production test, but verified by design and/or characterization. Note: Operating conditions apply. Table 42 SWD Interface Timing Parameters (Operating Conditions apply) Parameter Symbol Values Typ. Max. Unit Note / Test Condition tSC SR 25 – – ns CL = 30 pF 40 – – ns CL = 50 pF SR 10 – 500000 ns SR 10 – 500000 ns SR 6 – – ns SWDIO input hold t4 after SWDCLK rising edge SR 6 – – ns SWDIO output valid time t5 after SWDCLK rising edge CC – – 17 ns CL = 50 pF – – 13 ns CL = 30 pF t6 SWDIO output hold time from SWDCLK rising edge CC 3 – – ns Min. SWDCLK clock period t1 t2 t3 SWDCLK high time SWDCLK low time SWDIO input setup to SWDCLK rising edge tSC t1 t2 SWDCLK t6 SWDIO (Output) t5 t3 t4 SWDIO (Input) Figure 25 Data Sheet SWD Timing 72 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.8 Peripheral Timing 3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing The following parameters are applicable for a USIC channel operated in SSC mode. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 43 USIC SSC Master Mode Timing Parameter Symbol Values Min. SCLKOUT master clock period Unit Typ. Max. tCLK CC 33.3 − − ns Slave select output SELO t1 active to first SCLKOUT transmit edge CC tPB 6.51) − − ns Slave select output SELO t2 inactive after last SCLKOUT receive edge CC tPB 8.51) − − ns t3 CC -6 − 8 ns Receive data input t4 DX0/DX[5:3] setup time to SCLKOUT receive edge SR 23 − − ns Data input DX0/DX[5:3] t5 hold time from SCLKOUT receive edge SR 1 − − ns Data output DOUT[3:0] valid time Note / Test Condition 1) tPB = 1 / fPB Table 44 USIC SSC Slave Mode Timing Parameter Symbol Values Min. DX1 slave clock period Select input DX2 setup to first clock input DX1 transmit edge1) Data Sheet tCLK SR 66.6 t10 SR 3 73 Unit Typ. Max. − − ns − − ns Note / Test Condition V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 44 USIC SSC Slave Mode Timing Parameter Symbol Values Min. Unit Typ. Max. Select input DX2 hold after last clock input DX1 receive edge1) t11 SR 4 − − ns Receive data input DX0/DX[5:3] setup time to shift clock receive edge1) t12 SR 6 − − ns Data input DX0/DX[5:3] hold t13 time from clock input DX1 receive edge1) SR 4 − − ns Data output DOUT[3:0] valid t14 time CC 0 − 24 ns Note / Test Condition 1) This input timing is valid for asynchronous input signal handling of slave select input, shift clock input, and receive data input (bits DXnCR.DSEN = 0). Data Sheet 74 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Master Mode Timing t1 Select Output SELOx t2 Inactive Inactive Active Clock Output SCLKOUT Receive Edge First Transmit Edge t3 Last Receive Edge Transmit Edge t3 Data Output DOUT[3:0] t4 Data Input DX0/DX[5:3] t4 t5 Data valid t5 Data valid Slave Mode Timing t1 0 Select Input DX2 Clock Input DX1 t1 1 Active Inactive Receive Edge First Transmit Edge t1 2 Data Input DX0/DX[5:3] Inactive Last Receive Edge Transmit Edge t1 2 t1 3 Data valid t13 Data valid t14 t1 4 Data Output DOUT[3:0] Transmit Edge: with this clock edge, transmit data is shifted to transmit data output. Receive Edge: with this clock edge, receive data at receive data input is latched . Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal. USIC_SSC_TMGX.VSD Figure 26 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration, for which the slave select signal is low-active, and the serial clock signal is not shifted and not inverted. Data Sheet 75 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.8.2 Inter-IC (IIC) Interface Timing The following parameters are applicable for a USIC channel operated in IIC mode. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 45 USIC IIC Standard Mode Timing1) Parameter Symbol Values Unit Min. Typ. Max. Fall time of both SDA and t1 SCL CC/SR - - 300 ns Rise time of both SDA and t2 SCL CC/SR - - 1000 ns 0 - - µs 250 - - ns 4.7 - - µs 4.0 - - µs 4.0 - - µs 4.7 - - µs 4.0 - - µs 4.7 - - µs - - 400 pF Data hold time t3 Note / Test Condition CC/SR Data set-up time t4 CC/SR LOW period of SCL clock t5 CC/SR HIGH period of SCL clock t6 CC/SR t7 Hold time for (repeated) START condition CC/SR Set-up time for repeated START condition CC/SR Set-up time for STOP condition CC/SR t8 t9 Bus free time between a STOP and START condition t10 Capacitive load for each bus line Cb SR CC/SR 1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s. Data Sheet 76 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 46 USIC IIC Fast Mode Timing1) Parameter Symbol Values Min. Fall time of both SDA and t1 SCL CC/SR Typ. Unit Max. 20 + 0.1*Cb 300 ns 20 + 0.1*Cb 300 ns 0 - - µs 100 - - ns 1.3 - - µs 0.6 - - µs 0.6 - - µs 0.6 - - µs 0.6 - - µs 1.3 - - µs - - 400 pF Note / Test Condition 2) Rise time of both SDA and t2 SCL CC/SR 2) Data hold time t3 CC/SR Data set-up time t4 CC/SR LOW period of SCL clock t5 CC/SR HIGH period of SCL clock t6 CC/SR t7 Hold time for (repeated) START condition CC/SR Set-up time for repeated START condition CC/SR Set-up time for STOP condition CC/SR t8 t9 Bus free time between a STOP and START condition t10 Capacitive load for each bus line Cb SR CC/SR 1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device, approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s. 2) Cb refers to the total capacitance of one bus line in pF. Data Sheet 77 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters t1 SDA t2 t4 70% 30% t1 t3 t2 t6 SCL th t7 9 clock t5 t10 S SDA t8 t7 t9 SCL th 9 clock Sr Figure 27 3.3.8.3 P S USIC IIC Stand and Fast Mode Timing Inter-IC Sound (IIS) Interface Timing The following parameters are applicable for a USIC channel operated in IIS mode. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 47 USIC IIS Master Transmitter Timing Parameter Symbol Clock period t1 CC t2 CC Clock high time Values Unit Min. Typ. Max. 33.3 − − ns 0.35 x − − ns − − ns Note / Test Condition t1min Clock low time t3 CC 0.35 x t1min Hold time Clock rise time t4 CC t5 CC 0 − − ns − − 0.15 x ns t1min Data Sheet 78 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters t1 t2 t5 t3 SCK t4 WA/ DOUT Figure 28 USIC IIS Master Transmitter Timing Table 48 USIC IIS Slave Receiver Timing Parameter Symbol Clock period Clock high time t6 SR t7 SR Values Unit Min. Typ. Max. 66.6 − − ns 0.35 x − − ns − − ns − − ns − − ns Note / Test Condition t6min Clock low time t8 SR 0.35 x t6min t9 SR Set-up time 0.2 x t6min t10 SR Hold time 0 t6 t7 t8 SCK t9 t10 WA/ DIN Figure 29 Data Sheet USIC IIS Slave Receiver Timing 79 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.8.4 SDMMC Interface Timing Note: These parameters are not subject to production test, but verified by design and/or characterization. Note: Operating Conditions apply, total external capacitive load CL = 40 pF. AC Timing Specifications (Full-Speed Mode) Table 49 SDMMC Timing for Full-Speed Mode Parameter Symbol Values Clock frequency in full speed transfer mode (1/tpp) fpp CC 0 24 MHz Clock cycle in full speed transfer mode tpp CC 40 − ns Clock low time tWL CC 10 tWH CC 10 tTLH CC − tTHL CC − tISU_F SR 2 − ns Min. Unit Max. − ns 10 ns 10 ns − ns − ns Outputs valid time in full speed tODLY_F CC − mode 10 ns Outputs hold time in full speed tOH_F mode − ns Clock high time Clock rise time Clock fall time Inputs setup to clock rising edge Inputs hold after clock rising edge Table 50 tIH_F SR 2 CC 0 SD Card Bus Timing for Full-Speed Mode1) Parameter Symbol SD card input setup time tISU tIH Values Min. SD card input hold time Data Sheet Note/ Test Condition 80 Unit Max. 5 − ns 5 − ns Note/ Test Condition V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters SD Card Bus Timing for Full-Speed Mode1) (cont’d) Table 50 Parameter Symbol Values Min. tODLY tOH SD card output valid time SD card output hold time Unit Max. − 14 ns 0 − ns Note/ Test Condition 1) Reference card timing values for calculation examples. Not subject to production test and not characterized. Full-Speed Output Path (Write) t pp (Clock Cycle) SD Clock at Host Pin Driving Edge tCLK_DELAY SD Clock at Card Pin Sampling Edge Output Valid Time: t ODLY_H Output Hold Time: tOH_H tWL Output at Host Pins Output at Card Pins tDATA _DELAY + tTAP_DELAY t IH t ISU Figure 30 Full-Speed Output Path Full-Speed Write Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. No clock delay: (1) t ODLY_F + t DATA_DELAY + t TAP_DELAY + t ISU < t WL Data Sheet 81 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters With clock delay: (2) t ODLY_F + t DATA_DELAY + t TAP_DELAY + t ISU < t WL + t CLK_DELAY (3) t DATA_DELAY + t TAP_DELAY + t WL < t PP + t CLK_DELAY – t ISU – t ODLY_F t DATA_DELAY + t TAP_DELAY + 20 < 40 + t CLK_DELAY – 5 – 10 t DATA_DELAY < 5 + t CLK_DELAY – t TAP_DELAY The data can be delayed versus clock up to 5 ns in ideal case of tWL= 20 ns. Full-Speed Write Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. (4) t CLK_DELAY < t WL + t OH_F + t DATA_DELAY + t TAP_DELAY – t IH t CLK_DELAY < 20 + t DATA_DELAY + t TAP_DELAY – 5 t DATA_DELAY < 15 + t CLK_DELAY + t TAP_DELAY The clock can be delayed versus data up to 18.2 ns (external delay line) in ideal case of tWL= 20 ns, with maximum tTAP_DELAY = 3.2 ns programmed. Data Sheet 82 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Full-Speed Input Path (Read) tpp (Clock Cycle) SD Clock at Host Pin Sampling Edge tCLK_DELAY SD Clock at Card Pin Driving Edge tODLY tOH tDATA_DELAY + t TAP_DELAY Output at Host Pins Output at Card Pins tISU_H Figure 31 tIH_H Full-Speed Input Path Full-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. (5) t CLK_DELAY + t DATA_DELAY + t TAP_DELAY + t ODLY + t ISU_F < 0,5 × t pp t CLK_DELAY + t DATA_DELAY < 0,5 × t pp – t ODLY – t ISU_F – t TAP_DELAY t CLK_DELAY + t DATA_DELAY < 20 – 14 – 2 – t TAP_DELAY t CLK_DELAY + t DATA_DELAY < 4 – t TAP_DELAY The data + clock delay can be up to 4 ns for a 40 ns clock cycle. Data Sheet 83 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Full-Speed Read Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. (6) t CLK_DELAY + t OH + t DATA_DELAY + t TAP_DELAY > t IH_F t CLK_DELAY + t DATA_DELAY > t IH_F – t OH – t TAP_DELAY t CLK_DELAY + t DATA_DELAY > 2 – t TAP_DELAY The data + clock delay must be greater than 2 ns if tTAP_DELAY is not used. If the tTAP_DELAY is programmed to at least 2 ns, the data + clock delay must be greater than 0 ns (or less). This is always fulfilled. AC Timing Specifications (High-Speed Mode) Table 51 SDMMC Timing for High-Speed Mode Parameter Symbol Values Min. Clock frequency in high speed fpp transfer mode (1/tpp) Unit Max. CC 0 48 MHz − ns Clock cycle in high speed transfer mode tpp CC 20 Clock low time tWL tWH tTLH tTHL tISU_H CC 7 − ns CC 7 − ns CC − 3 ns CC − 3 ns SR 2 − ns Inputs hold after clock rising edge tIH_H SR 2 − ns Outputs valid time in high speed mode tODLY_H CC − 14 ns Outputs hold time in high speed mode tOH_H − ns Clock high time Clock rise time Clock fall time Inputs setup to clock rising edge Data Sheet CC 2 84 Note/ Test Condition V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters SD Card Bus Timing for High-Speed Mode1) Table 52 Parameter Symbol Values Unit Min. SD card input setup time SD card input hold time SD card output valid time SD card output hold time tISU tIH tODLY tOH Max. 6 − ns 2 − ns − 14 ns 2.5 − ns Note/ Test Condition 1) Reference card timing values for calculation examples. Not subject to production test and not characterized. High-Speed Output Path (Write) tpp (Clock Cycle) SD Clock at Host Pin Driving Edge t CLK_DELAY SD Clock at Card Pin Sampling Edge Output Valid Time: t ODLY_H Output Hold Time: tOH_H tWL Output at Host Pins Output at Card Pins tDATA _DELAY + tTAP_DELAY tIH tISU Figure 32 High-Speed Output Path High-Speed Write Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. Data Sheet 85 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters No clock delay: (7) t ODLY_H + t DATA_DELAY + t TAP_DELAY + t ISU < t WL With clock delay: (8) t ODLY_H + t DATA_DELAY + t TAP_DELAY + t ISU < t WL + t CLK_DELAY (9) t DATA_DELAY + t TAP_DELAY – t CLK_DELAY < t WL – t ISU – t ODLY_H t DATA_DELAY – t CLK_DELAY < t WL – t ISU – t ODLY_H – t TAP_DELAY t DATA_DELAY – t CLK_DELAY < 10 – 6 – 14 – t TAP_DELAY t DATA_DELAY – t CLK_DELAY < – 10 – t TAP_DELAY The data delay is less than the clock delay by at least 10 ns in the ideal case where tWL= 10 ns. High-Speed Write Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed skew range between the SD_CLK and SD_DAT/CMD signals on the PCB. (10) t CLK_DELAY < t WL + t OH_H + t DATA_DELAY + t TAP_DELAY – t IH t CLK_DELAY – t DATA_DELAY < t WL + t OH_H + t TAP_DELAY – t IH t CLK_DELAY – t DATA_DELAY < 10 + 2 + t TAP_DELAY – 2 t CLK_DELAY – t DATA_DELAY < 10 + t TAP_DELAY The clock can be delayed versus data up to 13.2 ns (external delay line) in ideal case of tWL= 10 ns, with maximum tTAP_DELAY = 3.2 ns programmed. Data Sheet 86 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters High-Speed Input Path (Read) tpp (Clock Cycle) SD Clock at Host Pin Sampling Edge t CLK_DELAY SD Clock at Card Pin Driving Edge tODLY t OH t DATA_DELAY + tTAP_DELAY Output at Host Pins Output at Card Pins t ISU_H Figure 33 tIH_H High-Speed Input Path High-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. (11) t CLK_DELAY + t DATA_DELAY + t TAP_DELAY + t ODLY + t ISU_H < t pp t CLK_DELAY + t DATA_DELAY < t pp – t ODLY – t ISU_H – t TAP_DELAY t CLK_DELAY + t DATA_DELAY < 20 – 14 – 2 – t TAP_DELAY t CLK_DELAY + t DATA_DELAY < 4 – t TAP_DELAY The data + clock delay can be up to 4 ns for a 20 ns clock cycle. Data Sheet 87 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters High-Speed Read Meeting Hold (Minimum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. (12) t CLK_DELAY + t OH + t DATA_DELAY + t TAP_DELAY > t IH_H t CLK_DELAY + t DATA_DELAY > t IH_H – t OH – t TAP_DELAY t CLK_DELAY + t DATA_DELAY > 2 – 2,5 – t TAP_DELAY t CLK_DELAY + t DATA_DELAY > – 0,5 – t TAP_DELAY The data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. This is always fulfilled. Data Sheet 88 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.9 USB Interface Characteristics The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification and the OTG Specification Rev. 1.3. High-Speed Mode is not supported. Note: These parameters are not subject to production test, but verified by design and/or characterization. Table 53 USB Timing Parameters (operating conditions apply) Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition – 20 ns CL = 50 pF – 20 ns CL = 50 pF Rise/Fall time matching tR CC 4 tF CC 4 tR/tF CC 90 – 111.11 % CL = 50 pF Crossover voltage VCRS – 2.0 CL = 50 pF Rise time Fall time CC 1.3 D+ 90% V 90% VC R S DVSS 10% 10% tF tR USB_Rise-Fall-Times.vsd Figure 34 Data Sheet USB Signal Timing 89 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.10 Ethernet Interface (ETH) Characteristics For proper operation of the Ethernet Interface it is required that fSYS ≥ 100 MHz. Note: These parameters are not subject to production test, but verified by design and/or characterization. 3.3.10.1 ETH Measurement Reference Points ETH Clock ETH I/O 1.4 V 1.4 V 2.0 V 0.8 V 2.0 V 0.8 V tR tF ETH_Testpoints.vsd Figure 35 Data Sheet ETH Measurement Reference Points 90 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.10.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) Table 54 ETH Management Signal Timing Parameters Parameter Symbol Values Typ. Max. Unit Note / Test Conditi on CC 400 – – ns CC 160 – – ns CC 160 – – ns CC 10 – – ns CC 10 – – ns SR 0 – 300 ns Min. t1 ETH_MDC high time t2 t3 ETH_MDC low time ETH_MDIO setup time (output) t4 ETH_MDIO hold time (output) t5 t6 ETH_MDIO data valid (input) ETH_MDC period CL = 25 pF t1 t3 t2 ETH_MDC ETH_MDIO sourced by STA: ETH_MDC t4 ETH_MDIO (output) t5 Valid Data ETH_MDIO sourced by PHY: ETH_MDC t6 ETH_MDIO (input) Valid Data ETH_Timing-Mgmt.vsd Figure 36 Data Sheet ETH Management Signal Timing 91 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.10.3 ETH RMII Parameters In the following, the parameters of the RMII (Reduced Media Independent Interface) are described. Table 55 ETH RMII Signal Timing Parameters Parameter Symbol ETH_RMII_REF_CL clock period t13 Values Unit Note / Test Condit Min. Typ. Max. ion SR 20 – – ns CL = 25 pF; 50 ppm ETH_RMII_REF_CL clock high time t14 SR 7 – 13 ns CL = 25 pF ETH_RMII_REF_CL clock low time t15 SR 7 – 13 ns ETH_RMII_RXD[1:0], ETH_RMII_CRS setup time t16 SR 4 – – ns ETH_RMII_RXD[1:0], ETH_RMII_CRS hold time t17 SR 2 – – ns ETH_RMII_TXD[1:0], ETH_RMII_TXEN data valid t18 CC 4 – 15 ns t1 3 t1 5 t14 ETH_RMII_REF_CL ETH_RMII_REF_CL t1 6 ETH_RMII _RXD[1:0] ETH_RMII _CRS (sourced by PHY ) t17 Valid Data ETH_RMII_REF_CL t18 ETH_RMII _TXD[1:0] ETH_RMII _TXEN (sourced by STA ) Figure 37 Data Sheet Valid Data Valid Data ETH_Timing-RMII .vsd ETH RMII Signal Timing 92 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.11 EtherCAT (ECAT) Characteristics 3.3.11.1 ECAT Measurement Reference Points ECAT Clock 1.4 V 1.4 V ECAT I/O 2.0 V 0.8 V 2.0 V 0.8 V tR tF ECAT_Testpoints.vsd Figure 38 Measurement Reference Points 3.3.11.2 ETH Management Signal Parameters (MCLK, MDIO) Table 56 ECAT Management Signal Timing Parameters Parameter Min. Typ. Max. Unit Note / Test Conditi on – 400 – ns 160 – – ns 160 – – ns 10 – – ns ECAT_MDIO hold time (output) tD_hold 10 CC – – ns ECAT_MDIO data valid (input) tD_valid 0 SR – 300 ns ECAT_MCLK period Symbol tMCLK Values CC ECAT_MCLK high time tMCLK_h CC ECAT_MCLK low time tMCLK_l IEEE802.3 requirement (2.5 MHz) CL = 25 pF CC ECAT_MDIO setup time (output) Data Sheet tD_setup CC 93 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters tMCLK tMCLK_l tMCLK_h ECAT_MCLK ECAT_MDIO sourced by STA: ECAT_MCLK tD_setup tD_hold ECAT_MDIO (output) Valid Data ECAT_MDIO sourced by PHY: ECAT_MCLK tD_valid ECAT_MDIO (input) Valid Data ECAT_Timing-Mgmt.vsd Figure 39 ECAT Management Signal Timing 3.3.11.3 MII Timing TX Characteristics Table 57 ETH MII TX Signal Timing Parameters Parameter Symbol PHY_CLK25, TX_CLK period tTX_CLK Delay between PHY clock source PHY_CLK25 and TX_CLK output of the PHY tPHY_delay Data Sheet Values Min. Typ. Max. Unit Note / Test Condition – 40 – ns – – – ns SR PHY dependent SR 94 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters Table 57 ETH MII TX Signal Timing Parameters (cont’d) Parameter Symbol PHY setup requirement: TXEN/TXD[3:0] with respect to TX_CLK tTX_setup PHY hold requirement: TXEN/TXD[3:0] with respect to TX_CLK tTX_hold Min. Values Typ. Max. Unit Note / Test Condition 15 – 0 ns PHY dependent IEEE802.3 limit is 15 ns 0 – 25 ns PHY dependent IEEE802.3 limit is 0 ns SR CC Note: ECAT0_CONPx.TX_SHIFT can be adjusted by displaying TX_CLK of a PHY and TXEN/TXD[3:0] on an oscilloscope. TXEN/TXD[3:0] is allowed to change between 0 ns and 25 ns after a rising edge of TX_CLK (according to IEEE802.3 – check your PHY’s documentation). Configure TX_SHIFT so that TXEN/TXD[3:0] change near the middle of this range. It is sufficient to check just one of the TXEN/TXD[3:0] signals, because they are nearly generated at the same time. PHY_CLK25 tTX_CLK ECAT_MII_TX_CLK tPHY_delady tPHY_TX_Setup ECAT_MII_TXD[3:0] ECAT_MII_TXEN tPHY_TX_Hold Valid Data TX_Shift[1:0]=00 10ns ECAT_MII_TXD[3:0] ECAT_MII_TXEN Valid Data TX_Shift[1:0]=01 20ns ECAT_MII_TXD[3:0] ECAT_MII_TXEN Valid Data TX_Shift[1:0]=10 30ns ECAT_MII_TXD[3:0] ECAT_MII_TXEN Valid Data TX_Shift[1:0]=11 FAIL: Setup/Hold Timing violated Figure 40 Data Sheet MII TX Characteristics 95 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.11.4 MII Timing RX Characteristics Table 58 ETH MII RX Signal Timing Parameters Parameter Symbol RX_CLK period tRX_CLK Values Min. Typ. Max. Unit Note / Test Condition – 40 – ns 10 – – ns 10 – – ns SR RX_DV/RX_DV/RXD[3:0] valid before rising edge of RX_CLK tRX_setup RX_DV/RX_DV/RXD[3:0] valid after rising edge of RX_CLK tRX_hold CL = 25 pF, IEEE802.3 requirement SR SR tRX_CLK ECAT_MII_RX_CLK tRX_setup ECAT_MII_RXD[3:0] ECAT_MII_RX_DV ECAT_MII_RX_ER Figure 41 Data Sheet tRX_hold Valid Data MII RX characteristics 96 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Electrical Parameters 3.3.11.5 Sync/Latch Timings Table 59 Sync/Latch Timings Parameter Symbol Values Min. tDC_SYNC_ – SYNC0/1 Jitter – 11 + m1) ns – – ns SR tDC_LATCH 12 + LATCH0/1 Typ. Max. Unit Note / Test Condition SR n2) 1) additional delay form logic and pad, number is added after characterization 2) additional shaping delay, number is added after characterization Note: SYNC0/1 pulse length are initially loaded by EEPROM content ADR 0x0002. The actual used value can be read back from Register DC_PULSE_LEN. tDC_LATCH tDC_LATCH LATCH0/1 tDC_SYNC_Jiiter SYNC0/1 Figure 42 Data Sheet Sync/Latch Timings 97 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Package and Reliability 4 Package and Reliability The XMC4300 is a member of the XMC4000 Family of microcontrollers. It is also compatible to a certain extent with members of similar families or subfamilies. Each package is optimized for the device it houses. Therefore, there may be slight differences between packages of the same pin-count but for different device types. In particular, the size of the Exposed Die Pad may vary. If different device types are considered or planned for an application, it must be ensured that the board layout fits all packages under consideration. 4.1 Package Parameters Table 60 provides the thermal characteristics of the packages used in XMC4300. Table 60 Thermal Characteristics of the Packages Parameter Symbol Limit Values Unit Package Types Exposed Die Pad dimensions including UGroove Ex × Ey CC 7.0 × 7.0 mm PG-LQFP-100-25 Exposed Die Pad dimensions excluding UGroove Ax × Ay CC 6.2 × 6.2 mm PG-LQFP-100-25 Thermal resistance Junction-Ambient TJ ≤ 150 °C RΘJA 22.5 K/W PG-LQFP-100-251) Min. - Max. CC 1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered. Note: For electrical reasons, it is required to connect the exposed pad to the board ground VSS, independent of EMC and thermal requirements. 4.1.1 Thermal Considerations When operating the XMC4300 in a system, the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage. The maximum heat that can be dissipated depends on the package and its integration into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The power dissipation must be limited so that the average junction temperature does not exceed 150 °C. Data Sheet 98 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Package and Reliability The difference between junction temperature and ambient temperature is determined by ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA The internal power consumption is defined as PINT = VDDP × IDDP (switching current and leakage current). The static external power consumption caused by the output drivers is defined as PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL) The dynamic external power consumption caused by the output drivers (PIODYN) depends on the capacitive load connected to the respective pins and their switching frequencies. If the total power dissipation for a given system configuration exceeds the defined limit, countermeasures must be taken to ensure proper system operation: • • • • Reduce VDDP, if possible in the system Reduce the system frequency Reduce the number of output pins Reduce the load on active output drivers Data Sheet 99 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Package and Reliability 4.2 Package Outlines 0.6 ±0.15 0°...7° -0.037 H 0.5 0.2 +0.07 -0.03 0.127 +0.073 1.4 ±0.05 24 x 0.5 = 12 1.6 MAX. 0.1±0.05 STAND OFF The exposed die pad dimensions are listed in Table 60. 0.08 C 100x C SEATING COPLANARITY PLANE 0.08 M C A-B D 100x 2) Bottom View 16 14 1) 0.2 C A-B D 100x Ex 3) 0.2 H A-B D 4x Ax 3) 100 Ay 3) 16 1) B 14 A Ey 3) D 100 1 1 Index Marking Exposed Diepad 1) Does not include plastic or metal protrusion of 0.25 max. per side 2) Does not include dambar protrusion of 0.08 max. per side 3) Refer table for exposed pad dimension details Figure 43 PG-LQFP-100-24, -25-PO V04 PG-LQFP-100-25 (Plastic Green Low Profile Quad Flat Package) All dimensions in mm. You can find complete information about Infineon packages, packing and marking in our Infineon Internet Page “Packages”: http://www.infineon.com/packages Data Sheet 100 V1.0, 2016-02 Subject to Agreement on the Use of Product Information XMC4300 XMC4000 Family Quality Declarations 5 Quality Declarations The qualification of the XMC4300 is executed according to the JEDEC standard JESD47I. Note: For automotive applications refer to the Infineon automotive microcontrollers. Table 61 Quality Parameters Parameter Symbol Values Min. Operation lifetime tOP CC 20 Typ. Max. − − Unit Note / Test Condition a TJ ≤ 109°C, device permanent on VHBM ESD susceptibility according to Human Body SR Model (HBM) − − 3 000 V EIA/JESD22A114-B ESD susceptibility according to Charged Device Model (CDM) VCDM − − 1 000 V Conforming to JESD22-C101-C Moisture sensitivity level MSL − − 3 − JEDEC J-STD-020D − − 260 °C Profile according to JEDEC J-STD-020D SR CC Soldering temperature TSDR SR Data Sheet 101 V1.0, 2016-02 Subject to Agreement on the Use of Product Information w w w . i n f i n e o n . c o m Published by Infineon Technologies AG