SST25VF064C to SST26VF064B/064BA Migration 1.0 INTRODUCTION The Serial Quad I/O™ (SQI™) family of flash-memory devices features a six-wire, 4-bit I/O interface that allows for low-power, high-performance operation in a low pin-count package. SST26VF064B/064BA also supports full command-set compatibility to traditional Serial Peripheral Interface (SPI) protocol. TABLE 1-1: This document lists all the firmware and hardware changes required to migrate from SST25VF064C to SST26VF064B/064BA. Refer to the SST26VF064B/ 064BA data sheet (DS20005119) for more information. SUMMARY OF CHANGES REQUIRED FOR ALL PART NUMBERS AND PACKAGES Board Layout/ Footprint Change Firmware Change SST26VF064B-104I/SO (16-lead SOIC) No Yes SST25VF064C-80-4I-S3AE (8-lead SOIC) SST26VF064B-104I/SM (8-lead SOIC) No Yes SST25VF064C-80-4I-Q2AE (WSON) SST26VF064B-104I/MN (WDFN)1 No Yes Any SST25VF064C SST26VF064B-104I/TD (TBGA)2 Yes Yes Current Part Recommended Upgrade SST25VF064C-80-4I-SCE (16-lead SOIC) 1. WSON and WDFN are different designators for the same package 2. TBGA is a new package available for SST26VF064B/064BA TABLE 1-2: Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN LAYOUT COMPARISON, 16-LEAD SOIC SST25VF064C RST#/HOLD#1 VDD NC NC NC NC CE# SO/SIO1 WP# VSS NC NC NC NC SI/SIO0 SCK SST26VF064B/ 064BA HOLD#/SOI3 VDD NC NC NC NC CE# SO/SIO1 WP#/SIO2 VSS NC NC NC NC SI/SIO0 SCK TABLE 1-3: Pin No. PIN LAYOUT COMPARISON, 8-LEAD SOIC SST25VF064C SST26VF064B/ 064BA 1 CE# CE# 2 SO/SIO1 SO/SIO1 3 WP# WP#/SIO2 4 VSS VSS 5 SI/SIO0 SI/SIO0 6 SCK SCK 7 RST#/HOLD#1 HOLD#/SOI3 8 VDD VDD 1. For SST25VF064C, Pin 7 is RST# pin at power-up. For SST26VF064B/064BA, Pin 7 is HOLD# pin at power-up. 1. For SST25VF064C, Pin 1 is RST# pin at power-up. For SST26VF064B/064BA, Pin 1 is HOLD# pin at power-up. 2014 Microchip Technology Inc. DS20005343A-page 1 SST25VF064C TO SST26VF064B/064BA 2.0 MIGRATION CONSIDERATIONS The following topics should be considered when migrating from SST26VF064C to SST26VF064B/ 064BA. 2.1 Reset Pin Function at Power-Up SST25VF064C powers up with the Reset-pin function enabled. Reset-pin function is not supported by SST26VF064B/064BA. SST26VF064B/064BA executes a Reset by software reset using Reset Enable (66H) or Reset memory (99H) software instruction commands. TABLE 2-1: Bit 0 WEL 2 3 4 5 6 BP0 BP1 BP2 BP3 SEC1 7 BPL Status and Configuration Register The status register of the SST25VF064C differs from the Status register of SST26VF064B/064BA. Table 2-1 shows the Status register of SST25VF064C and Table 2-2 shows the Status register of SST26VF064B/ 064BA. SST26VF064B/064BA also has an additional Configuration register used to configure device operations and setup defaults on I/O configuration and Block Protection state, see Table 2-3. STATUS REGISTER SST25VF064C Name BUSY 1 2.2 Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection Indicate current level of block write protection Indicate current level of block write protection Indicate current level of block write protection Security ID status 1 = Security ID space locked 0 = Security ID space not locked 1 = BP3, BP2, BP1, BP0 are read-only bits 0 = BP3, BP2, BP1, BP0 are readable/writable Default at Power-up 0 Read/Write R 0 R 1 1 1 1 01 R/W R/W R/W R/W R 0 R/W T0.0 25036 1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout SID instruction; otherwise, the default at power up is ‘0’. TABLE 2-2: Bit 0 Name BUSY 1 WEL 2 WSE 3 WSP 4 WPLD 5 SEC1 STATUS REGISTERSST26VF064B/064BA DS20005343A-page 2 Function Write operation status 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress Write-Enable Latch status 1 = Device is write-enabled 0 = Device is not write-enabled Write Suspend-Erase status 1 = Erase suspended 0 = Erase is not suspended Write Suspend-Program status 1 = Program suspended 0 = Program is not suspended Write Protection Lock-Down status 1 = Write Protection Lock-Down enabled 0 = Write Protection Lock-Down disabled Security ID status 1 = Security ID space locked 0 = Security ID space not locked Default at Power-up 0 Read/Write (R/W) R 0 R 0 R 0 R 0 R 01 R 2014 Microchip Technology Inc. SST25VF064C TO SST26VF064B/064BA TABLE 2-2: Bit 6 7 Name RES BUSY STATUS REGISTERSST26VF064B/064BA (CONTINUED) Default at Power-up 0 0 Function Reserved for future use Write operation status 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress Read/Write (R/W) R R 1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout Security ID instruction, otherwise default at power-up is ‘0’. TABLE 2-3: Bit 0 Name CONFIGURATION REGISTERSST26VF064B/064BA Function Default at Power-up Read/Write (R/W) RES Reserved 0 R IOC I/O Configuration for SPI Mode 1 = WP# and HOLD# pins disabled 0 = WP# and HOLD# pins enabled 01 R/W RES Reserved 0 R BPNV Block-Protection Volatility State 1 = No memory block has been permanently locked 0 = Any block has been permanently locked 1 R 4 RES Reserved 0 R 5 RES Reserved 0 R 6 RES Reserved 0 R WPEN Write-Protection Pin (WP#) Enable 1 = WP# enabled 0 = WP# disabled 02 R/W 1 2 3 7 1. SST26VF064B default at Power-up is ‘0’ SST26VF064BA default at Power-up is ‘1’ 2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down. The Read-Status-Register (RDSR) instructions allows the device to read the Status register for SST25VF064C or SST26VF064B/064BA. The Read-ConfigurationRegister (RDCR) enables the device to read the Configuration register for SST26VF064B/064BA. to write to the Status register of SST25VF064C is shown in Figure 2-1. The WRSR sequence that allows the device to write to the Status and Configuration registers of SST26VF064B/064BA is shown in Figure 2-2. The default I/O state factory settings are the same between SST25VF064C and SST26VF064B. The SST26VF064BA factory default setting for I/O WP# and HOLD# are disabled and different from the SST25VF064C. The Write-Status-Register (WRSR) instruction writes to the Status and Configuration registers. Write-Enable (WREN) instruction must be issued prior to WRSR instruction.The WRSR sequence that allows the device FIGURE 2-1: WRITE-STATUS-REGISTER SEQUENCE SST25VF064C CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MODE 0 01 SI MSB SO STATUS REGISTER IN 7 6 5 4 3 2 1 0 MSB HIGH IMPEDANCE 1392 F20.1a 2014 Microchip Technology Inc. DS20005343A-page 3 SST25VF064C TO SST26VF064B/064BA FIGURE 2-2: WRITE-STATUS-REGISTER SEQUENCE SST26VF064B/064BA CE# MODE 3 SCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MODE 0 01 SI MSB SO STATUS CONFIGURATION REGISTER REGISTER XX XX XX XX XX XX XX XX 7 6 5 4 3 2 1 0 MSB MSB HIGH IMPEDANCE 25119 F64.1 2.3 Device Protection 2.4 SST26VF064B/064BA employs a new protection scheme that allows for more flexibility and a higher level of protection in comparison to the SST25VF064C. SST25VF064C offers traditional memory protection via block protection bits in the Status Register, whereas SST26VF064B/064BA supports individual block protection via Block Protection Register instructions. Both SST25VF064C and SST26VF064B/064BA power up with memory protected. To execute Program or Erase commands, remove the protection. Device ID SST26VF064C and SST26VF064B/064BA use different device IDs. The device ID of SST25VF064C is BF254BH. BFH is manufacturer ID, 25H is memory type and 4BH is device ID. The device ID of SST26VF064B/064BA is BF2643H. BFH is manufacturer ID, 26H is memory type and 43H is device ID. The device IDs for both devices are accessed with the same operation command and protocol, but the return data will be different for each device. See Table 2-5. for more information about the operation commands. To remove the memory protection of SST25VF064C, clear the protection bits in the status register. The status register contains protection bits BP0, BP1, BP2, and BP3, all of which are set to 0 to clear all protection. SST26VF064B/064BA supports JEDEC’s Serial Flash Discoverable Parameters (SFDP) v1.1 as an additional method of device identification. SST26VF064B/064BA supports the Global Block-protection Unlock command (98H) to unlock the entire memory. Table 2-4 lists all block protection commands for SST26VF064B/064BA. 2.5 TABLE 2-4: BLOCK PROTECTION COMMANDS SST26VF064B/ 064BA Instruction Read Block Protection Register Write Block Protection Register Lock Down Block Protection Register non-Volatile Write Lock-Down Register Global Block Protection Unlock DS20005343A-page 4 OpCode 72H 42H 8DH E8H 98H Communication Protocol SST25VF064C only utilizes SPI protocol, but SST26VF064B/064BA can use either SPI and SQI protocol. SST26VF064B/064BA will work with a host controller that only supports SPI. If the host controller supports both SPI and SQI, then all the features of SST26VF064B/064BA are available. SST25VF064C supports a clock frequency up to 80MHz and SST26VF064B/064BA supports a clock frequency up to 104MHz. 2014 Microchip Technology Inc. SST25VF064C TO SST26VF064B/064BA 2.6 Host Controller Supports SPI Most operation commands of SST25VF064C are compatible with SST26VF064B with minimal changes required. See Table 2-5. TABLE 2-5: OPERATION COMMAND COMPATIBILITY SST25VF064C Device Operation Instructions Compatible with OpCode SST26VF064B/ 064BA Comments Read 03H Yes Fast-Read Dual I/O BBH Yes Fast-Read Dual Output 3BH Yes High-Speed Read 0BH Yes Sector-Erase 20H Yes 32KByte Block Erase 52H Change Required This command is not supported in the SST26VF064B/ 064BA. For 32 KByte Block Erase, use D8H. 64KByte Block Erase D8H Change Required The memory maps of SST25VF064C and SST26VF064B/ 064BA are different. Refer to data sheet. 60H or C7H Change Required SST26VF064B/064BA supports C7H but not 60H instruction Chip-Erase Page-Program 02H Yes Dual-Input Page Program A2H No Not supported by SST26VF064B/064BA RDSR 05H Yes With the exception of bit 0 (BUSY) and bit 1 (WEL), all other bits in the Status register are different between the two devices. Status register on SST26VF064B/064BA is readonly. EWSR 50H No Not supported by SST26VF064B WRSR 01H The two parts use different block protection schemes and the block protection bits in the Status Register are removed from SST26VF064B/064BA. WRSR instructions for Change Required SST26VF064B/064BA ignore Write to the 1st data byte to the Status Register, and only accept Write to the 2nd data byte for the Configuration Register. WREN 06H Yes WRDI 04H Yes RDID 90H or ABH No Not supported by SST26VF064B/064BA JEDEC-ID 9FH Yes Device Id is different between two parts. EHLD AAH No Not supported by SST26VF064B/064BA Read SID 88H Yes Program SID A5H Yes The security memory space increases from 256 Bytes on SST25VF064C to 2048 Bytes on SST26VF064B/064BA. Lockout SID 85H Yes 2014 Microchip Technology Inc. DS20005343A-page 5 SST25VF064C TO SST26VF064B/064BA 2.7 Host Controller Supports Both SPI and SQI If the host controller can support both SPI and SQI protocol than the above changes described are still relevant and in addition all features of SST26VF064B/ 064BA are now available for use. A review of the current methods/code to perform read and program must be done and the firmware should be upgraded to take advantage of all the features available as described in the data sheet. SST26VF064B/064BA supports higher functionality and performance such as: • up to 104 MHz operating frequency • multi-I/O read/program capability • enhanced security and OTP security memory area outside of the main memory array • JEDEC Serial Flash Discoverable Parameters (SFDP) • Suspend Program/Erase capability. Refer to the SST26VF064B/064BA data sheet for detailed instructions. 2.8 Conclusion This document describes the aspects to consider when migrating from SST25VF064C to SST26VF064B/ 064BA. SST26VF064B/064BA is a great choice because it supports higher clock frequency, uses both SPI and SQI protocol, and continues to provide the superior reliability represented by SuperFlash® technology. DS20005343A-page 6 2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-783-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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