P3MS650100H 1.8V/2.5V/3.3V, LVCMOS Peak EMI Reduction Clock Generator Product Description P3MS650100H device is a spread spectrum frequency modulator clock generator with 1.8 V/2.5 V/3.3 V LVCMOS output designed specifically for clock frequencies between 15 MHz and 60 MHz. P3MS650100H reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of all clock dependent signals. The device allows significant system cost savings by reducing the number of circuit board layers, ferrite beads, and shielding that are traditionally required to pass EMI regulations. P3MS650100H accepts an LVCMOS input from an external reference clock and locks to a 1x modulated clock output. P3MS650100H goes to power down mode for power save when no clock is present on CLKIN pin. ModOUT goes ‘low’ in power down mode. P3MS650100H operates over −20°C to +85°C and is available in a 4 Pin WDFN, (1.2mmX1.0mm) Package. http://onsemi.com MARKING DIAGRAM WDFN4 CASE 511BS 1 X = Specific Device Code M = Date Code PIN CONFIGURATION Features • Peak EMI Reduction Clock Generator with LVCMOS Output • Supply Voltage and Input / Output Clock Frequency Range • • • • • • 1.6 V − 2.0 V: 15 MHz − 30 MHz 2.3 V − 3.6 V: 15 MHz − 60 MHz Frequency Deviation: ±1.4% @ 24 MHz Power Down current less than 1 mA 4−pin WDFN (1.2mmX1.0mm) Package Output Drive Current: 1.8 V: 8 mA 2.5 V/3.3 V: 16 mA Operating temperature range: −20°C to +85°C These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant XM 1 VSS 1 4 VDD CLKIN 2 3 ModOUT (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Applications • P3MS650100H is targeted towards consumer electronic applications like mobile Phones, tablets, net books and MIDs VDD 4 CLKIN PLL + Frequency Modulator 2 1 ModOUT 3 VSS Figure 1. Simplified Block Diagram © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 0 1 Publication Order Number: P3MS650100H/D P3MS650100H Table 1. PIN DESCRIPTION Pin # Pin Name Type 1 VSS Power Description 2 CLKIN Input 3 ModOUT Output Spread Spectrum Clock Output. 4 VDD Power Power supply for the entire chip Ground connection. LVCMOS External reference clock input. Table 2. OPERATING CONDITIONS Symbol VDD (1.8 V) Description Supply Voltage with respect to VSS VDD (2.5 V/3.3 V) Min Max Unit 1.6 2.0 V 2.3 3.6 −20 +85 °C TA Operating temperature CL Load Capacitance 15 pF CIN Input Capacitance 5 pF Table 3. ABSOLUTE MAXIMUM RATING Symbol VDD, VIN TSTG Description Rating Unit Voltage on any input pin with respect to VSS −0.5 to +4.6 V Storage temperature −65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 P3MS650100H Table 4. DC Electrical Characteristics VDD = 1.6 V − 2.0 V, TA= −20°C to +85°C Symbol Parameter Min Typ Max Unit 1.6 1.8 2.0 V 15MHz 1.3 1.8 30MHz 2 2.8 VDD Supply Voltage with respect to VSS IDD Dynamic supply current (Unloaded Output) ICC Static supply current (No Clock @ CLKIN) VIH Input high voltage VIL Input low voltage 0.3*VDD V IIH Input high current (CLKIN pin) 10 mA IIL Input low current (CLKIN pin) 10 mA VOH Output high voltage, IOH = − 8mA VOL Output low voltage , IOL = 8mA ZOUT Output impedance mA 1 mA 0.65*VDD V 0.75*VDD V 0.2*VDD 28 V W Table 5. AC ELECTRICAL CHARACTERISTICS VDD = 1.6 V − 2.0 V, TA = −20°C to +85°C Symbol CLKIN ModOUT Parameter Min Typ Max Unit Input Clock frequency 15 30 MHz Output Clock frequency 15 30 MHz tLH (Notes 1 and 2) Output rise time (Measured between 20% to 80%) 1.7 2.7 nS tHL (Notes 1 and 2) Output fall time (Measured between 80% to 20%) 1.4 2.4 nS tJC (Notes 2) Cycle−to−cycle Jitter, Peak (1000 cycles) 15 MHz 400 24 MHz 250 pS 30 MHz tD (Notes 1 and 2) Output duty cycle (Measured @ 50%) tON (Notes 1 and 2) PLL lock Time (Stable power supply, valid clock presented on CLKIN) fd 45 Frequency Deviation @ 24 MHz 50 ±1.4 1. All parameters are specified with 15 pF loaded output. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production http://onsemi.com 3 55 % 3 mS ±1.55 % P3MS650100H Table 6. DC ELECTRICAL CHARACTERISTICS VDD = 2.3 V – 3.6 V, TA = −20°C to +85°C Symbol Parameter VDD Supply Voltage with respect to VSS IDD Dynamic supply current (Unloaded Output) ICC Static supply current (No Clock @ CLKIN) VIH Input high voltage VIL Input low voltage IIH IIL Min Typ Max Unit 2.3 2.8 3.6 V 15MHz 1.7 3 30MHz 2.8 5 60MHz 5 9 mA 2 mA 0.65 * VDD V 0.3 * VDD V Input high current (CLKIN pin) 10 mA Input low current (CLKIN pin) 10 mA VOH Output high voltage, IOH = −16 mA VOL Output low voltage, IOL = 16 mA ZOUT Output impedance 0.75 * VDD V 0.2 * VDD 20 V W Table 7. AC ELECTRICAL CHARACTERISTICS VDD = 2.3 V – 3.6 V, TA = −20°C to +85°C Symbol CLKIN ModOUT Parameter Min Typ Max Unit Input Clock frequency 15 60 MHz Output Clock frequency 15 60 MHz tLH (Notes 3 and 4) Output rise time (Measured between 20% to 80%) 0.8 1.6 nS tHL (Notes 3 and 4) Output fall time (Measured between 80% to 20%) 0.8 1.6 nS tJC (Notes 4) Cycle−to−cycle Jitter, Peak (1000 cycles) tD (Notes 3 and 4) Output duty cycle tON (Notes 3 and 4) PLL lock Time (Stable power supply, valid clock presented on CLKIN) fd 15 MHz 350 24 MHz 250 60 MHz 100 45 Frequency Deviation @ 24 MHz 50 ±1.4 3. All parameters are specified with 15 pF loaded output. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production http://onsemi.com 4 pS 55 % 3 mS ±1.55 % P3MS650100H 1.80 1.80 1.70 1.70 DEVIATION (±%) DEVIATION (±%) 1.60 1.60 1.50 1.40 1.30 1.50 1.40 1.30 1.20 1.10 1.20 15 20 25 FREQUENCY (MHz) 1.00 15 30 20 Figure 2. Deviation vs. Frequency (VDD = 1.6 V − 2.0 V) VDDIN 40 45 30 35 FREQUENCY (MHz) 50 55 60 Figure 3. Deviation vs. Frequency (VDD = 2.3 V − 3.6 V) Noise Reduction Filter C1 C2 R VDD 0.1mF 2.2mF 4 CLKIN CLKIN 25 ModOUT 2 Rs 3 ModOUT P3MS650100H VSS 1 Rs = Trace Impedance of PCB – Output Impedance of Device (Z0) Note: Refer Pin Description table for Functionality details Figure 4. Typical Application Schematic PCB Layout Recommendation For optimum device performance, following guidelines are recommended. ♦ Dedicated VDD and GND planes. ♦ The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should have decoupling capacitors. ♦ In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. http://onsemi.com 5 P3MS650100H A typical layout is shown in the figure below. Figure 5. Recommended PCB Layout ORDERING INFORMATION Ordering Code P3MS650100H−4CR Marking Temperature Package Type Shipping† A −20°C to +85°C 4−pin (1.2 mm x 1.0 mm) WDFN (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 6 P3MS650100H PACKAGE DIMENSIONS WDFN4, 1.0x1.2, 0.5P CASE 511BS−01 ISSUE O PIN ONE REFERENCE 2X ÉÉ ÉÉ E 0.05 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 mm FROM THE TERMINAL TIPS. 4. PACKAGE DIMENSIONS EXCLUSIVE OF BURRS AND MOLD FLASH. A B D DIM A A1 A3 b D E e L 0.05 C TOP VIEW (A3) 0.05 C A MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 1.00 BSC 1.20 BSC 0.50 BSC 0.35 0.45 0.05 C SIDE VIEW e A1 e/2 2 1 4 3 4X C SEATING PLANE RECOMMENDED MOUNTING FOOTPRINT* 0.50 PITCH L 3X 0.63 PACKAGE OUTLINE 1.50 4X b 0.05 BOTTOM VIEW M C A B NOTE 3 4X 0.30 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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