P3PS850BH Timing-Safe] Peak EMI Reduction IC Functional Description P3PS850BH is a versatile, Timing−Safe peak EMI reduction IC. P3PS850BH accepts one input from an external reference, and locks on to it delivering a 1x Timing−Safe output clock. P3PS850BH has a Frequency Selection (FS) control that facilitates selecting one of the two operating frequency ranges. Refer to the frequency Selection table. The device has an SSEXTR pin to select different deviations depending upon the value of an external resistor connected at this pin to GND. P3PS850BH has an MR pin for selecting one of the two Modulation Rates. PD#/OE provides the Power Down option. Outputs will be tri−stated when power down is active. P3PS850BH operates over a supply voltage range of 2.3 V to 3.6 V, and is available in an 8 Pin WDFN (2 mm x 2 mm) Package. General Features • 1x , LVCMOS Timing−Safe Peak EMI Reduction • Input Clock Frequency: • • • • • • • • 18 MHz − 72 MHz Output Clock Frequency( Timing−Safe): ♦ 18 MHz − 72 MHz Analog Frequency Deviation Selection Two different Modulation Rate Selection Power Down Option for Power Save Output Buffer Strength: 16 mA Supply Voltage: 2.3 V − 3.6 V 8 pin WDFN 2 mm x 2 mm, (TDFN) Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ♦ Application • P3PS850BH is targeted for use in consumer electronic applications http://onsemi.com MARKING DIAGRAMS 1 1 WDFN8 CASE 511AQ DGMG G DG = Specific Device Code M = Date Code G = Pb−Free Device PIN CONFIGURATION CLKIN 1 8 V DD 7 SSEXTR FS 3 6 MR GND 4 5 ModOUT PD#/OE 2 P3PS850BH ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. like mobile phones, Camera modules, MFP and DPF. © Semiconductor Components Industries, LLC, 2012 January, 2012 − Rev. 1 1 Publication Order Number: P3PS850BH/D P3PS850BH VDD MR CLKIN SSEXTR PLL ModOUT (Timing−Safe) PD#/OE GND FS Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN I External reference Clock input. 2 PD# / OE I Power Down. Pull LOW to enable Power Down. Outputs will be tri−stated when power down is enabled. Pull HIGH to disable power down and enable output. NO default state. 3 FS I Frequency Select .NO default state. Refer to the Frequency Selection table 4 GND P Ground 5 ModOUT O Buffered modulated Timing−Safe clock output 6 MR I Modulation Rate Select. When LOW, selects Low Modulation Rate. Selects High Modulation Rate when pulled HIGH. Has an internal pull−up resistor. 7 SSEXTR I Analog Deviation Selection through external resistor to GND. 8 VDD P Supply Voltage Table 2. FREQUENCY SELECTION TABLE FS Frequency (MHz) 0 18−36 1 36−72 Table 3. OPERATING CONDITIONS Symbol VDD Parameter Min Max Unit Supply Voltage 2.3 3.6 V −20 TA Operating Temperature +85 °C CL Load Capacitance 15 pF CIN Input Capacitance 7 pF http://onsemi.com 2 P3PS850BH Table 4. ABSOLUTE MAXIMUM RATING Symbol Parameter Rating Unit VDD, VIN Voltage on any input pin with respect to Ground −0.5 to +4.6 V Storage temperature −65 to +125 °C TSTG Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV TDV Static Discharge Voltage (As per JEDEC STD22−A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. DC ELECTRICAL CHARACTERISTICS Symbol Parameter VDD Supply Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Test Conditions Min Typ Max Unit 2.3 2.7 3.6 V 0.65 * VDD V 0.35 * VDD V VIN = VDD 10 mA Input LOW Current VIN = 0 V for MR pin 10 mA VOH Output HIGH Voltage IOH = −16 mA VOL Output LOW Voltage IOL = 16 mA ICC Static Supply Current PD#/OE pin pulled to GND IDD Dynamic Supply Current Unloaded Output Zo 0.75 * VDD V 0.25 * VDD mA mA FS = 0, @ 18 MHz 6 10 FS = 0, @ 24 MHz 7 12 FS = 0, @ 36 MHz 10 17 FS = 1, @ 36 MHz 9 14 FS = 1, @ 48 MHz 11 19 FS = 1, @ 72 MHz 16 28 Output Impedance V 10 13 W Table 6. AC ELECTRICAL CHARACTERISTICS Parameter Min Typ Max Unit FS = 0 18 24 36 MHz FS = 1 36 48 72 FS = 0 18 24 36 FS = 1 36 48 72 Duty Cycle (Note 1 and 2) Measured at VDD / 2 45 50 55 % Rise Time (Note 1 and 2) Measured between 20% to 80% 0.8 1.2 ns 2) Measured between 80% to 20% 0.8 1.2 ns Input Frequency ModOUT Fall Time (Note 1 and Test Conditions 1. All parameters are specified with 15 pF loaded output. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. http://onsemi.com 3 P3PS850BH Table 6. AC ELECTRICAL CHARACTERISTICS Parameter Cycle−to−Cycle Jitter (Note 2) PLL Lock Time (Note 2) Test Conditions Unloaded output with SSEXTR pin OPEN Typ Max Unit FS = 0, 18 MHz $250 $350 ps FS = 0, 24 MHz $150 $225 FS = 0, 36 MHz $75 $125 FS = 1, 36 MHz $150 $200 FS = 1, 48 MHz $100 $150 FS = 1, 72 MHz $75 $125 Stable power supply, valid clock presented on CLKIN pin, PD# toggled from Low to High 1. All parameters are specified with 15 pF loaded output. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. http://onsemi.com 4 Min 1 ms P3PS850BH 3.0 2.5 2.5 2.0 1.5 MR = 0 1.0 0.5 0.0 0 2.0 1.5 MR = 0 1.0 MR = 1 0.5 100 200 300 400 500 600 700 800 900 1000 0.0 0 MR = 1 100 200 300 400 500 600 700 800 900 1000 RESISTOR (kW) RESISTOR (kW) Figure 2. Deviation vs. SSEXTR @ 18 MHz (FS = 0) Figure 3. Deviation vs. SSEXTR @ 24 MHz (FS = 0) 3.0 3.0 2.5 2.5 DEVIATION ($%) DEVIATION ($%) DEVIATION ($%) 3.0 2.0 1.5 1.0 2.0 1.5 1.0 MR = 0 MR = 0 0.5 0.5 0.0 0 MR = 1 MR = 1 0.0 0 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 RESISTOR (kW) RESISTOR (kW) Figure 4. Deviation vs. SSEXTR @ 27 MHz (FS = 0) Figure 5. Deviation vs. SSEXTR @ 30 MHz (FS = 0) 3.0 2.5 DEVIATION ($%) DEVIATION ($%) DEVIATION VERSUS SSEXTR RESISTANCE CHARTS 2.0 1.5 1.0 MR = 0 0.5 0.0 MR = 1 0 100 200 300 400 500 600 700 800 900 1000 RESISTOR (kW) Figure 6. Deviation vs. SSEXTR @ 36 MHz (FS = 0) http://onsemi.com 5 P3PS850BH 3.0 2.5 2.5 2.0 1.5 1.0 MR = 0 0.5 0.0 0 100 2.0 1.5 1.0 MR = 0 MR = 1 0.5 MR = 1 200 300 400 500 0.0 600 0 300 400 500 Figure 7. Deviation vs. SSEXTR @ 36 MHz (FS = 1) Figure 8. Deviation vs. SSEXTR @ 48 MHz (FS = 1) 3.0 2.5 2.5 2.0 1.5 1.0 MR = 1 0.5 100 200 1.5 1.0 MR = 0 0.5 300 400 500 0.0 600 MR = 1 0 100 200 300 400 500 RESISTOR (kW) RESISTOR (kW) Figure 9. Deviation vs. SSEXTR @ 54 MHz (FS = 1) Figure 10. Deviation vs. SSEXTR @ 60 MHz (FS = 1) 3.0 2.5 2.0 1.5 1.0 MR = 0 0.5 0.0 MR = 1 0 100 200 300 400 RESISTOR (kW) 500 Figure 11. Deviation vs. SSEXTR @ 72 MHz (FS = 1) http://onsemi.com 6 600 2.0 MR = 0 0 200 RESISTOR (kW) 3.0 0.0 100 RESISTOR (kW) DEVIATION ($%) DEVIATION ($%) DEVIATION ($%) 3.0 DEVIATION ($%) DEVIATION ($%) DEVIATION VERSUS SSEXTR RESISTANCE CHARTS 600 600 P3PS850BH TSKEW VERSUS SSEXTR RESISTANCE CHARTS 25 18 16 14 12 15 10 Tskew (ns) Tskew (ns) 20 MR = 0 8 6 MR = 0 4 5 2 MR = 1 0 0 10 0 100 200 300 400 500 600 700 800 900 1000 1100 MR = 1 0 100 200 300 400 500 600 700 800 900 1000 1100 RESISTOR (kW) RESISTOR (kW) Figure 12. Tskew vs. SSEXTR @ 18 MHz (FS = 0) Figure 13. Tskew vs. SSEXTR @ 24 MHz (FS = 0) 16 12 14 10 8 10 Tskew (ns) Tskew (ns) 12 8 6 4 4 MR = 0 MR = 0 2 2 0 0 MR = 1 0 100 200 300 400 500 600 700 800 900 1000 1100 0 100 200 300 400 500 600 700 800 900 1000 1100 RESISTOR (kW) Figure 14. Tskew vs. SSEXTR @ 27 MHz (FS = 0) Figure 15. Tskew vs. SSEXTR @ 36 MHz (FS = 0) 10 9 10 8 7 6 Tskew (ns) 8 Tskew (ns) MR = 1 RESISTOR (kW) 12 MR = 0 4 6 5 4 MR = 0 3 2 0 6 2 MR = 1 0 MR = 1 1 0 100 200 300 400 500 600 700 800 900 1000 1100 RESISTOR (kW) 0 Figure 16. Tskew vs. SSEXTR @ 36 MHz (FS = 1) 100 200 300 400 500 600 700 800 900 1000 1100 RESISTOR (kW) Figure 17. Tskew vs. SSEXTR @ 48 MHz (FS = 1) http://onsemi.com 7 P3PS850BH TSKEW VERSUS SSEXTR RESISTANCE CHARTS 8 6 7 5 4 5 Tskew (ns) Tskew (ns) 6 4 3 MR = 0 3 2 MR = 0 2 1 0 1 MR = 1 0 0 100 200 300 400 500 600 700 800 900 1000 1100 MR = 1 0 100 200 300 400 500 600 700 800 900 1000 1100 RESISTOR (kW) RESISTOR (kW) Figure 18. Tskew vs. SSEXTR @ 54 MHz (FS = 1) Figure 19. Tskew vs. SSEXTR @ 72 MHz (FS = 1) 50 120 45 110 40 100 35 RESISTANCE (kW) RESISTANCE (kW) MINIMUM SSEXTR RESISTANCE VERSUS FREQUENCY(FOR TIMING−SAFE OPERATION) CHARTS MR = 0 30 25 20 15 10 MR = 1 5 0 18 NOTE: 90 80 70 MR = 0 60 50 40 30 20 MR = 1 10 20 22 24 26 28 30 32 34 0 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 36 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Frequency vs. Resistance (FS = 0) Figure 21. Frequency vs. Resistance (FS = 1) Device−to−Device variation of Deviation and Tskew is $10% http://onsemi.com 8 P3PS850BH SWITCHING WAVEFORMS t1 t2 VDD/2 VDD/2 VDD/2 OUTPUT Figure 22. Duty Cycle Timing 80% 80% 20% 20% OUTPUT t3 t4 Figure 23. Output Rise/Fall Time Input Timing−Safe Output TSKEW ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ TSKEW/2 TSKEW/2 One clock cycle (T) TSKEW represents input−output skew when spread spectrum is ON For example, TSKEW / 2 = 0.20 * T for an Input clock of 24 MHz, translates in to (1/24 MHz) * 0.20 = 8.33 ns Figure 24. Input−Output Skew Input Input Timing-Safe ModOUT ModOUT with SSOFF Figure 25. Typical Example of Timing−Safe Waveform http://onsemi.com 9 P3PS850BH Recommended Noise reduction Filter VDDIN R 0.1 mF C1 2.2 mF C2 8 CLKIN Power down Control VDD 1 CLKIN VDD Rs ModOUT Clock ModOUT 5 Rx 2 PD#/OE VDD Frequency Selection Control Analog Deviation Control SSEXTR 7 P3PS850BH VDD 3 FS MR 6 GND Modulation Rate Control 4 NOTE: Refer Pin Description table for Functionality details. Figure 26. Typical Application Schematic http://onsemi.com 10 P3PS850BH PCB Layout Recommendation For optimum device performance, following guidelines are recommended. • Dedicated VDD and GND planes. • The device must be isolated from system power supply noise. A 0.1 mF and a 2.2 mF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should have decoupling capacitors. • In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. A typical layout is shown in Figure 27. As short as possible R As short as possible CLKIN VDD SSEXTR PD#/OE FS MR GND GND Modout Rs Figure 27. ORDERING INFORMATION Part Number P3PS850BHG−08CR Top Marking Temperature Package Type Shipping† DG −20°C to +85°C 8−Pin (2 mm x 2 mm) WDFN(TDFN) (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 11 P3PS850BH PACKAGE DIMENSIONS WDFN8 2x2, 0.5P CASE 511AQ ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. L L L1 PIN ONE REFERENCE 2X ÍÍÍ ÍÍÍ DETAIL A E OPTIONAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÉÉ ÉÉ TOP VIEW EXPOSED Cu A3 DETAIL B 0.05 C 0.05 C MOLD CMPD DETAIL B A 8X DIM A A1 A3 b D E e L L1 OPTIONAL CONSTRUCTION A1 C SIDE VIEW RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X 0.78 DETAIL A 1 MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60 --0.15 8X 4 L PACKAGE OUTLINE 2.30 0.88 8 5 e/2 e 8X b 0.10 C A 0.05 C 8X B 0.35 NOTE 3 1 0.50 PITCH DIMENSIONS: MILLIMETERS BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Timing−Safe is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative P3PS850BH/D