P3P2043B LCD Panel EMI Reduction IC Product Description The P3P2043B is a versatile spread spectrum frequency modulator designed specifically for digital flat panel applications. The P3P2043B reduces electromagnetic interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The P3P2043B allows significant system cost savings by reducing the number of circuit board layers ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. The P3P2043B uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The P3P2043B modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. http://onsemi.com MARKING DIAGRAMS 8 1 SOIC−8 CASE 751 A L Y W G 8 1 CML ALYW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Features • FCC Approved Method of EMI Attenuation • Provides Up to 15 dB of EMI Suppression • Generates a Low EMI Spread Spectrum Clock of the Input • • • • • • • • • • • Frequency Input Frequency Range: 30 MHz to 110 MHz Optimized for 32.5 MHz, 54 MHz, 65 MHz, 74 MHz and 108 MHz Pixel Clock Frequencies Internal Loop Filter Minimizes External Components and Board Space Eight Selectable High Spread Ranges Up to $2% SSON# Control Pin for Spread Spectrum Enable and Disable Options Low Cycle−to−Cycle Jitter 3.3 V $ 0.3 V Operating Range Low power CMOS Design Supports Most Mobile Graphic Accelerator and LCD Timing Controller Specifications Available in 8−pin SOIC Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant PIN CONFIGURATION CLKIN 1 8 VDD CP0 2 7 SR0 MR 3 VSS 4 6 ModOUT 5 SSON# ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Applications • The P3P2043B is targeted towards digital flat panel applications for notebook PCs, palm−size PCs, office automation equipments and LCD monitors. © Semiconductor Components Industries, LLC, 2012 July, 2012 − Rev. 0 1 Publication Order Number: P3P2043B/D P3P2043B VDD SR0 MR0 CP0 SSON# PLL Modulation CLKIN Frequency Divider Feedback Phase Loop Detector Filter VCO Output Divider Divider ModOUT Figure 1. Block Diagram VSS Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN Input External reference frequency input. Connect to externally generated reference signal. 2 CP0 Input Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor. Refer Modulation Selection Table. 3 MR Input Digital logic input used to select two different Modulation Rate. This pin has an internal pull−up resistor. Refer Modulation Selection Table. 4 VSS Power 5 SSON# Input 6 ModOUT Output 7 SR0 Input 8 VDD Power Ground to entire chip. Connect to system ground. Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull−low resistor. Spread spectrum clock output. Digital logic input used to select Spreading Range. This pin has an internal pullup resistor. Refer Modulation Selection Table. Power supply for the entire chip Table 2. MODULATION SELECTION Spreading Range ($ %) MR CP0 SR0 32.5 MHz 54 MHz 65 MHz 81 MHz 108 MHz 0 0 0 1.47 1.19 1.08 0.96 0.88 0 0 1 2.26 1.82 1.66 1.48 1.31 0 1 0 0.75 0.59 0.55 0.50 0.46 0 1 1 3.03 2.43 2.20 1.98 1.74 1 0 0 1.39 1.21 1.11 0.98 0.86 1 0 1 2.06 1.85 1.67 1.47 1.27 1 1 0 0.74 0.61 0.56 0.50 0.43 1 1 1 2.88 2.49 2.26 2.00 1.71 http://onsemi.com 2 Modulation Rate (kHz) (FIN / 40) * 94.33 (FIN / 40) * 62.89 P3P2043B Spread Spectrum Selection The Modulation Selection Table defines the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1). For example, P3P2043B is designed for high−resolution, flat panel applications and is able to support an XGA (1024 x 768) flat panel operating at 65 MHz (FIN) clock speed. A spreading selection of CP0 = 0, CP1 = 1 and SR0 = 0 provides a percentage deviation of $1.00% from FIN. This results in the frequency on ModOUT being swept from 65.65 to 64.35 MHz at a modulation rate of 102.19 kHz. Refer Modulation Selection Table. The example in the following illustration is a common EMI reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers. +3.3 V 65 MHz from graphics accelerator 1 CLKIN VDD 8 2 CP0 SR0 7 3 MR 0.1 mF ModOUT 6 SSON# 5 4 VSS P3P2043B Modulated 65 MHz signal with $1.00% deviation and modulation rate of 102.19 kHz. This signal is connected back to the spread spectrum input pin (SSIN) of the graphics accelerator. Digital control for the SS enable or disable Figure 2. Application Schematic for Mobile LCD Graphics Controllers Table 3. ABSOLUTE MAXIMUM RATING Symbol Rating Unit Voltage on any input pin with respect to Ground −0.5 to +4.6 V Storage temperature −65 to +125 °C TA Operating temperature −40 to +85 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 kV VDD, VIN TSTG TDV Parameter Static Discharge Voltage (As per JEDEC STD22−A114−B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage with respect to Ground TA Operating temperature TJ Junction temperature (0°C to +70°C) qJC SOIC Min Typ Max Unit 3.0 3.3 3.6 V +70 °C 82.39 °C 0 SOIC 156.5 http://onsemi.com 3 °C/W P3P2043B Table 5. DC ELECTRICAL CHARACTERISTICS Symbol Max Unit VIL Input low voltage VSS − 0.3 0.8 V VIH Input high voltage 2.0 VDD + 0.3 V IIL Input low current (pullup resistor on inputs CP0, CP1 and SR0) −50 mA IIH Input high current (pulldown resistor on input SSON#) 50 mA VOL Output low voltage (IOL = 8 mA) 0.4 V VOH Output high voltage (IOH = −8 mA) IDD Static supply current (CLKIN pulled LOW) 300 mA ICC Dynamic supply current (3.3 V and 10 pF loading) VDD Operating voltage tON Power−up time (first locked cycle after power up) ZOUT Parameter Min Typ 2.5 V 6 15 22 mA 3.0 3.3 3.6 V 3 ms Clock output impedance 35 W Table 6. AC ELECTRICAL CHARACTERISTICS Symbol Min Typ Max Unit Input Clock frequency 30 74 110 MHz fOUT Output Clock frequency 30 74 110 MHz tLH* Output rise time (measured between 20% to 80%) 1.1 1.5 2 ns tHL* Output fall time (measured between 80% to 20%) 0.8 1.2 1.8 ns tJC Jitter (cycle−to−cycle) < 50 MHz $250 ps w 50 MHz $200 fIN tD Parameter Output duty cycle 45 50 55 % *tLH and tHL are measured into a capacitive load of 10 pF. ORDERING INFORMATION Part Number P3P2043BG−08SR Top Marking Temperature Package Type Shipping† CML 0°C to +70°C SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb−Free. http://onsemi.com 4 P3P2043B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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