Ordering number : ENA1453A LC87F1JJ2A CMOS IC FROM 192K byte, RAM 16384 byte on-chip http://onsemi.com 8-bit 1-chip Microcontroller with USB-host controller Overview The LC87F1JJ2A is an 8-bit microcomputer that, integrates on a single chip a number of hardware features such as 192K-byte flash ROM, 16384-byte RAM, an on-chip debugger, a 16-bit timer/counter, a 16-bit timer, four 8-bit timers, a base timer serving as a realtime clock, 3 channels of synchronous SIO interface with automatic data transfer capabilities, an asynchronous/synchronous SIO interface, a UART interface, a full-speed USB interface (host control function), a 12-channel AD converter, 2 channels of 12-bit PWM, a system clock frequency divider, an infrared remote control receiver circuit, and an interrupt feature. Features Package Dimensions Flash ROM • 196608 × 8 bits • Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V • Block-erasable in 128 byte units • Writes data in 2-byte units unit : mm (typ) 3163B 36 0.5 9.0 7.0 25 37 24 48 13 7.0 9.0 RAM • 16384 × 9 bits Package Form • SQFP48(7×7): Lead-/Halogen-free type 1 12 0.5 0.18 0.15 (1.5) 0.1 1.7max (0.75) SANYO : SQFP48(7X7) * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.1.02 D2612HK/52009HKIM 20090407-S00002 No.A1453-1/27 LC87F1JJ2A Bus Cycle Time • 83.3ns (When CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time (tCYC) • 250ns (When CF=12MHz) Ports • I/O ports Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07) • USB ports 2 (UHD+, UHD-) • Dedicated oscillator ports 2 (CF1, CF2) • Input-only port (also used for oscillation) 1 (XT1) • Reset pin 1 (RES) • Power supply pins 6 (VSS1 to VSS3, VDD1 to VDD3) Timers • Timer 0: 16-bit timer/counter with 2 capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as PWM outputs) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes SIO • SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (Suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 8192 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or in word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in No.A1453-2/27 LC87F1JJ2A • SIO9: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 8192 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 8 bits × 12 channels PWM: Multifrequency 12-bit PWM × 2 channels Infrared Remote Control Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the base clock) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding. 3) X'tal HOLD mode release function USB Interface (host control function) 1) Compliant with full-speed (12M bps) specifications 2) Supports 4 transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer). Audio Interface 1) Sampling frequency (fs): 8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz 2) Master clock frequency: 256fs/384fs 3) Bit clock selectable: 48fs/64fs 4) Data bit length: 16/18/20/24 bits 5) LSB first/MSB first mode selectable 6) Left-justification/right-justification/I2S format selectable Watchdog Timer • Watchdog timer using external RC circuitry • Interrupt and reset signals selectable Clock Output Function 1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) Can output the source oscillation clock for the subclock. No.A1453-3/27 LC87F1JJ2A Interrupts • 41 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/UHC bus active/remote control signal receive 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/INT6/UHC device attach/UHC device detach/UHC resume 6 0002BH H or L T1L/T1H/INT7/SIO9/AIF start 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/SIO4/UART1 transmit/AIF end 9 00043H H or L ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC-STALL 10 0004BH H or L Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY/AIF error • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 8192 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation and PLL Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • PLL circuit (internal): For system clock For system clock For system clock, and realtime clock For USB interface (see Fig.5) and audio interface (see Fig. 6) No.A1453-4/27 LC87F1JJ2A Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of releasing the HALT mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer (3) Generating an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are five ways of releasing the HOLD mode. (1) Setting the reset pin to the lower level (2) System resetting by watchdog timer (3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins * The INT0 and INT1 pins must be configured only for level detection. (4) Having an interrupt source established at port 0 (5) Having an bus active interrupt source established in the USB host control circuit • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are seven ways of releasing the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer (3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4, and INT5 pins * The INT0 and INT1 pins must be configured only for level detection. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit (6) Having an bus active interrupt source established in the USB host control circuit (7) Having an interrupt source established in the infrared remote controller receiver circuit Development Tools • On-chip debugger: TCB87- type B + LC87F1JJ2A Flash ROM Programming Boards Package Programming board SQFP48(7×7) W87F55256SQ Flash ROM Programmer Maker Flash Support Group, Inc. (FSG) Model Single Device AF9709/AF9709B/AF9709C Rev. 03.12 or later LC87F1JJ2A (Note 2) LC87F1JJ2A (including Ando Electric Co., Ltd. models) AF9101/AF9103(main unit) Flash Support Group, Inc. (FSG) Onboard (FSG) + single/ganged SIB87(interface driver) Our company(Note 1) (Our company model) Single/ganged Our company Supported Version AF9708/ SKK/SKK Type B Application version: (SANYO FWS) 1.04 or later Onboard SKK-DBG Type B Chip data version: single/ganged (SANYO FWS) 2.17 or later LC87F1JJ2 Note 1: PC-less standalone onboard programming is possible using the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87) provided by Our company in pair. Note 2: Dedicated programming device and program are required depending on the programming conditions. Contact Our company or FSG if you have any questions or difficulties regarding this matter. No.A1453-5/27 LC87F1JJ2A 36 35 34 33 32 31 30 29 28 27 26 25 P27/INT5/SCK9 P26/INT5/SI9/WR9 P25/INT5/SO9/RD9 P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4 P20/INT4/INT6 P07/AN7/T7O/LRCK P06/AN6/T6O/BCLK P05/AN5/CKO/SDAT P04/AN4/DBGP2 Pin Assignment 37 38 39 40 41 42 43 44 45 46 47 48 LC87F1JJ2A 24 23 22 21 20 19 18 17 16 15 14 13 P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0/MCLKO PWM1/MCLKI P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P73/INT3/T0IN/RMIN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 1 2 3 4 5 6 7 8 9 10 11 12 UHDUHD+ VDD3 VSS3 P34/UFILT P33/AFILT P32 P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN Top view SQFP48(7×7) “Lead-/Halogen-free type” SQFP48 NAME SQFP48 NAME 1 P73/INT3/T0IN/RMIN 25 P04/AN4/DBGP2 2 RES 26 P05/AN5/CKO/SDAT 3 XT1/AN10 27 P06/AN6/T6O/BCLK 4 XT2/AN11 28 P07/AN7/T7O/LRCK 5 VSS1 29 P20/INT4/INT6 6 CF1 30 P21/INT4 P22/INT4/SO4/RD 7 CF2 31 8 VDD1 32 P23/INT4/SI4/WR 9 P10/SO0 33 P24/INT5/INT7/SCK4 10 P11/SI0/SB0 34 P25/INT5/SO9/RD9 11 P12/SCK0 35 P26/INT5/SI9/WR9 12 P13/SO1 36 P27/INT5/SCK9 13 P14/SI1/SB1 37 UHD- 14 P15/SCK1 38 UHD+ 15 P16/T1PWML 39 VDD3 16 P17/T1PWMH/BUZ 40 VSS3 17 PWM1/MCLKI 41 P34/UFILT 18 PWM0/MCLKO 42 P33/AFILT 19 VDD2 43 P32 P31/URX1 20 VSS2 44 21 P00/AN0 45 P30/UTX1 22 P01/AN1 46 P70/INT0/T0LCP/AN8 23 P02/AN2/DBGP0 47 P71/INT1/T0HCP/AN9 24 P03/AN3/DBGP1 48 P72/INT2/T0IN No.A1453-6/27 LC87F1JJ2A System Block Diagram Interrupt control Standby control CF USB PLL RC Clock generator X’tal PLA IR FROM PC SIO0 Bus interface ACC SIO1 Port 0 B register SIO4 Port 1 C register SIO9 Port 2 Timer 0 Port 3 Timer 1 Port 7 Timer 4 INT0 to INT7 noise filter RAR Timer 5 UART1 RAM Timer 6 Audio interface Stack pointer Timer 7 ADC Watchdog timer Base timer Infrared remote control receiver circuit ALU PSW On-chip debugger PWM0 PWM1 USB host No.A1453-7/27 LC87F1JJ2A Pin Description Pin Name I/O Description Option VSS1,VSS2, VSS3 - - power supply No VDD1, VDD2 - + power supply No VDD3 - USB reference voltage Yes Port 0 I/O • 8-bit I/O ports Yes • I/O specifiable in 4-bit units P00 to P07 • Pull-up resistors can be turned on and off in 4-bit units. • HOLD release input • Port 0 interrupt input • Pin functions AD converter input ports: AN0 to AN7(P00 to P07) On-chip debugger pins: DBGP0 to DBGP2(P02 to P04) P05: System clock output/audio interface SDAT input/output P06: Timer 6 toggle output/audio interface BCLK input/output P07: Timer 7 toggle output/audio interface LRCK input/output Port 1 I/O • 8-bit I/O ports Yes • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions Port 2 I/O P10: SIO0 data output P14: SIO1 data input/bus input/output P11: SIO0 data input/bus input/output P15: SIO1 clock input/output P12: SIO0 clock input/output P16: Timer 1 PWML output P13: SIO1 data output P17: Timer 1 PWMH output/beeper output • 8-bit I/O ports Yes • I/O specifiable in 1-bit units P20 to P27 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20 to P23: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input P22: SIO4 data input/output/parallel interface RD output P23: SIO4 data input/output/parallel interface WR output P24: SIO4 clock input/output/INT7 input/timer 0H capture 1 input P25: SIO9 data input/output/parallel interface RD9 output P26: SIO9 data input/output/parallel interface WR9 output P27: SIO9 clock input/output Interrupt acknowledge types Port 3 P30 to P34 I/O Rising Falling INT4 enable enable INT5 enable enable INT6 enable INT7 enable Rising & H level L level enable disable disable enable disable disable enable enable disable disable enable enable disable disable Falling • 5-bit I/O ports Yes • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P30: UART1 transmit P31: UART1 receive P33: Audio interface PLL filter circuit connection pin (See Fig. 6.) P34: USB interface PLL filter circuit connection pin (See Fig. 5.) Continued on next page. No.A1453-8/27 LC87F1JJ2A Continued from preceding page. Pin Name Port 7 I/O Description Option • 4-bit I/O ports I/O No • I/O specifiable in 1-bit units P70 to P73 • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input/ infrared remote control receiver input AD converter input ports: AN8(P70), AN9(P71) Interrupt acknowledge types PWM0 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling No PWM0, PWM1 output ports PWM1 General-purpose input port • Pin functions PWM0: Audio interface master clock output PWM1: Audio interface master clock input UHD- I/O USB data I/O pin UHD-/general-purpose I/O port No UHD+ I/O USB data I/O pin UHD+/general-purpose I/O port No RES I Reset pin No XT1 I • 32.768kHz crystal oscillator input No • Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 when not to be used. XT2 • 32.768kHz crystal oscillator output I/O No • Pin functions General-purpose input port AD converter input port: AN11 Must be configured for oscillation and kept open if not to be used. CF1 I Ceramic/crystal resonator input No CF2 O Ceramic/crystal resonator output No Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 P10 to P17 Option Selected in Units of 1 bit 1 bit P20 to P27 Option Type Output Type Pull-up Resistor 1 CMOS Programmable (Note 1) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable Programmable P30 to P34 P70 - No Nch-open drain P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No UHD+, UHD- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal resonator output (Nch-open drain No when in general-purpose output mode) Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). No.A1453-9/27 LC87F1JJ2A User Options Option Name Type Flash ROM Version Port output type Option Selected in Units of P00 to P07 1 bit 1 bit 1 bit P30 to P34 1 bit - - USB Regulator - - - address USB Regulator USB Regulator (at HOLD mode) USB Regulator (at HALT mode) Nch-open drain CMOS P20 to P27 Program start Nch-open drain CMOS P10 to P17 Setting CMOS Nch-open drain CMOS Nch-open drain 00000h 1FE00h Use Nonuse Use Nonuse Use Nonuse Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin and extend the backup period. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. LSI For backup Power supply VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. LSI For backup Power supply VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 No.A1453-10/27 LC87F1JJ2A USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by optional settings. The procedure for marking the optional settings is described below. (1) Option settings Reference voltage circuit state (2) (3) (4) USB regulator Use Use Use Nonuse USB regulator in HOLD mode Use Nonuse Nonuse Nonuse USB regulator in HALT mode Use Nonuse Use Nonuse Normal mode Active Active Active Inactive HOLD mode Active Inactive Inactive Inactive HALT mode Active Inactive Active Inactive • When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1. • Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode. • When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with when the reference voltage circuit is inactive. Circuit example 1: When VDD1=VDD2=3.3V • Inactivating the reference voltage circuit (selection (4)). • Connecting VDD3 to VDD1 and VDD2. LSI Power supply 3.3V VDD1 UHD+ 33Ω To USB connector UHDVDD2 15kΩ 5pF 2.2μF VDD3 *1 UFILT 0Ω VSS1 VSS2 VSS3 2.2μF *1: Needs adjustment on target board. Circuit example 2: When VDD1=VDD2=5.0V • Activating the reference voltage circuit (selection (1)). • Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. LSI Power supply 5V VDD1 UHD+ 33Ω To USB connector UHDVDD2 15kΩ 5pF VDD3 2.2μF UFILT 0Ω 0.1μF VSS1 VSS2 VSS3 2.2μF No.A1453-11/27 LC87F1JJ2A Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply voltage VDD max VDD1, VDD2, VDD3 Input voltage VI(1) XT1, CF1 Input/output VIO(1) Ports 0, 1, 2, 3, 7 voltage VDD1= VDD2= VDD3 min typ max -0.3 +6.5 -0.3 VDD+0.3 unit V PWM0, PWM1 -0.3 VDD+0.3 XT2 Peak output IOPH(1) Ports 0, 1, 2 current • When CMOS output type is selected -10 • Per 1 applicable pin IOPH(2) PWM0, PWM1 Per 1 applicable pin IOPH(3) Port 3 • When CMOS output P71 to P73 type is selected -20 -5 • Per 1 applicable pin High level output current Average IOMH(1) Ports 0, 1, 2 output current • When CMOS output type is selected -7.5 • Per 1 applicable pin (Note 1-1) IOMH(2) PWM0, PWM1 Per 1 applicable pin IOMH(3) Port 3 • When CMOS output P71 to P73 type is selected -15 -3 • Per 1 applicable pin Total output ΣIOAH(1) Ports 0, 2 current Total current of all applicable pins ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) Port 1 Total current of all PWM0, PWM1 applicable pins Ports 0, 1, 2 Total current of all PWM0, PWM1 applicable pins Port 3 Total current of all P71 to P73 applicable pins UHD+, UHD- Total current of all applicable pins Peak output IOPL(1) current P02 to P07 -25 -25 -45 -10 -25 mA Per 1 applicable pin Ports 1, 2 20 PWM0, PWM1 IOPL(2) P00, P01 Per 1 applicable pin IOPL(3) Ports 3, 7 Per 1 applicable pin 30 10 XT2 Low level output current Average IOML(1) P02 to P07 output current Ports 1, 2 (Note 1-1) PWM0, PWM1 Per 1 applicable pin 15 IOML(2) P00, P01 Per 1 applicable pin IOML(3) Ports 3, 7 Per 1 applicable pin 20 7.5 XT2 Total output ΣIOAL(1) Ports 0, 2 current Total current of all 45 applicable pins ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) Port 1 Total current of all PWM0, PWM1 applicable pins Ports 0, 1, 2 Total current of all PWM0, PWM1 applicable pins Ports 3, 7 Total current of all XT2 applicable pins UHD+, UHD- 45 80 15 Total current of all 25 applicable pins Allowable power Pd max SQFP48(7×7) Ta=-40 to +85°C 140 dissipation Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 mW °C Note 1-1: The average output current is an average of current values measured over 100ms intervals. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A1453-12/27 LC87F1JJ2A Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Operating Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions 0.245μs ≤ tCYC ≤ 200μs supply voltage 0.490μs ≤ tCYC ≤ 200μs Except (Note 2-1) in onboard programming mode Memory VHD VDD1=VDD2=VDD3 sustaining VDD[V] min typ unit max 3.0 5.5 2.7 5.5 2.0 5.5 RAM and register contents sustained in HOLD mode. supply voltage High level VIH(1) input voltage Ports 0, 1, 2, 3 P71 to P73 2.7 to 5.5 P70 port input/ 0.3VDD +0.7 VDD 2.7 to 5.5 0.9VDD VDD 2.7 to 5.5 0.75VDD 4.0 to 5.5 VSS VDD 0.1VDD 2.7 to 4.0 VSS 4.0 to 5.5 VSS 2.7 to 4.0 VSS 2.7 to 5.5 VSS 2.7 to 5.5 VSS 0.25VDD 3.0 to 5.5 0.245 200 2.7 to 5.5 0.490 200 3.0 to 5.5 0.1 12 interrupt side PWM0, PWM1 VIH(2) Port 70 watchdog timer side VIH(3) Low level VIL(1) input voltage XT1, XT2, CF1, RES Ports 1, 2, 3 P71 to P73 VIL(2) P70 port input/ interrupt side VIL(3) Port 0 PWM0, PWM1 VIL(4) VIL(5) Port 70 watchdog timer side VIL(6) Instruction XT1, XT2, CF1, RES tCYC cycle time Except in onboard programming (Note 2-2) mode External FEXCF(1) CF1 V +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 μs • CF2 pin open • System clock frequency system clock division ratio=1/1 frequency • External system clock duty =50±5% MHz • CF2 pin open • System clock frequency division ratio=1/1 2.7 to 5.5 0.1 6 • External system clock duty =50±5% Oscillation FmCF(1) CF1, CF2 See Fig. 1. frequency range When 12MHz ceramic oscillation FmCF(2) CF1, CF2 (Note 2-3) When 6MHz ceramic oscillation See Fig. 1. FmRC FsX’tal Internal RC oscillation XT1, XT2 32.768kHz crystal oscillation See Fig. 2. 3.0 to 5.5 12 2.7 to 5.5 6 2.7 to 5.5 2.7 to 5.5 0.3 1.0 MHz 2.0 32.768 kHz Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See oscillation characteristics examples. No.A1453-13/27 LC87F1JJ2A Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current IIH(2) Low level input Ports 0, 1, 2, 3 Output disabled Port 7 Pull-up resistor off RES PWM0, PWM1 VIN=VDD (Including output Tr's off leakage UHD+, UHD- current) XT1, XT2 Input port configuration IIH(3) CF1 VIN=VDD VIN=VDD IIL(1) Ports 0, 1, 2, 3 Output disabled Port 7 Pull-up resistor off RES PWM0, PWM1 VIN=VSS (Including output Tr's off leakage UHD+, UHD- current) current IIL(2) min typ unit 2.7 to 5.5 1 2.7 to 5.5 1 2.7 to 5.5 15 2.7 to 5.5 -1 2.7 to 5.5 -1 XT1, XT2 Input port configuration IIL(3) CF1 VIN=VSS VIN=VSS 2.7 to 5.5 -15 High level output VOH(1) Ports 0, 1, 2, 3 IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) P71 to P73 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 IOH=-0.2mA 2.7 to 5.5 VDD-0.4 VOH(3) max VOH(4) PWM0, PWM1 IOH=-10mA 4.5 to 5.5 VDD-1.5 VOH(5) P05 to P07 IOH=-1.6mA 3.0 to 5.5 VDD-0.4 IOH=-1mA 2.7 to 5.5 VDD-0.4 IOL=30mA 4.5 to 5.5 1.5 VOH(6) (Note 3-1) Low level output VOL(1) P00, P01 voltage VOL(2) IOL=5mA 3.0 to 5.5 0.4 VOL(3) IOL=2.5mA 2.7 to 5.5 0.4 VOL(4) Ports 0, 1, 2 IOL=10mA 4.5 to 5.5 1.5 VOL(5) PWM0, PWM1 IOL=1.6mA 3.0 to 5.5 0.4 IOL=1mA 2.7 to 5.5 0.4 IOL=1.6mA 3.0 to 5.5 0.4 IOL=1mA 2.7 to 5.5 0.4 VOL(6) VOL(7) XT2 Ports 3, 7 VOL(8) Pull-up resistance Hysteresis voltage Rpu(1) Ports 0, 1, 2, 3 Rpu(2) Port 7 VHYS VOH=0.9VDD RES Port 1, 2, 3, 7 Pin capacitance CP All pins 4.5 to 5.5 15 35 80 2.7 to 4.5 18 50 150 μA V kΩ 2.7 to 5.5 0.1VDD V 2.7 to 5.5 10 pF For pins other than that under test: VIN=VSS f=1MHz Ta=25°C Note 3-1: When the CKO system clock output function (P05) or audio interface output function (P05 to P07) is used. No.A1453-14/27 LC87F1JJ2A Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Frequency tSCK(1) Low level tSCKL(1) Specification Pin/ Conditions Remarks SCK0(P12) VDD[V] See Fig. 9. typ max unit 2 1 pulse width High level min tSCKH(1) 1 pulse width • Continuous data transfer mode tSCKHA(1a) • USB, AIF, SIO4, SIO9, and DMCOPY not used at the same 4 time. Input clock • See Fig. 9. • (Note 4-1-2) • Continuous data transfer mode tSCKHA(1b) 2.7 to 5.5 tCYC • USB used at the same time. • AIF, SIO4, SIO9, and DMCOPY 7 not used at the same time. • See Fig. 9. • (Note 4-1-2) • Continuous data transfer mode tSCKHA(1c) • USB, AIF, SIO4, SIO9, and DMCOPY used at the same 9 time. • See Fig. 9. Serial clock • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • When CMOS output type is 4/3 selected Low level tSCKL(2) • See Fig. 9. 1/2 pulse width High level tSCK tSCKH(2) 1/2 pulse width tSCKHA(2a) • Continuous data transfer mode • USB, AIF, SIO4, SIO9, and DMCOPY not used at the same tSCKH(2) time. +2tCYC Output clock • When CMOS output type is tSCKH(2) + (10/3)tCYC selected • See Fig. 9. tSCKHA(2b) • Continuous data transfer mode 2.7 to 5.5 • USB used at the same time. • AIF, SIO4, SIO9, and DMCOPY not used at the same time. • When CMOS output type is tSCKH(2) +2tCYC tSCKH(2) + tCYC (19/3)tCYC selected. • See Fig.9. tSCKHA(2c) • Continuous data transfer mode • USB, AIF, SIO4, SIO9, and DMCOPY used at the same time • When CMOS output type is selected tSCKH(2) +2tCYC tSCKH(2) + (25/3)tCYC • See Fig.9. Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page. No.A1453-15/27 LC87F1JJ2A Continued from preceding page. Parameter Serial input Data setup time tsDI(1) Specification Pin/ Conditions Remarks SB0(P11), SI0(P11) VDD[V] Data hold time min typ max unit • Must be specified with respect to rising edge of SIOCLK. • See Fig. 9. thDI(1) 0.03 2.7 to 5.5 0.03 Input clock Output delay tdDO(1) time SO0(P10), • Continuous data transfer mode SB0(P11) • (Note 4-1-3) (1/3)tCY C +0.05 • Synchronous 8-bit mode tdDO(2) +0.05 2.7 to 5.5 tdDO(3) μs 1tCYC • (Note 4-1-3) (Note 4-1-3) Output clock Serial output Symbol (1/3)tCY C +0.05 Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 9. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Input clock Symbol Frequency tSCK(3) Low level tSCKL(3) Specification Pin/ Conditions Remarks SCK1(P15) VDD[V] See Fig. 9. 2.7 to 5.5 pulse width High level Frequency SCK1(P15) • When CMOS output type is • See Fig. 9. tSCKL(4) pulse width High level 2 1/2 2.7 to 5.5 tSCK tSCKH(4) 1/2 Serial input SB1(P14), SI1(P14) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 9. Data hold time thDI(2) 0.03 2.7 to 5.5 0.03 Output delay time Serial output tsDI(2) unit 1 pulse width Data setup time max 1 selected Low level typ tCYC tSCKH(3) tSCK(4) min 2 pulse width Output clock Serial clock Parameter tdDO(4) SO1(P13), SB1(P14) μs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output 2.7 to 5.5 (1/3)tCYC +0.05 mode. • See Fig. 9. Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. No.A1453-16/27 LC87F1JJ2A 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Parameter Symbol Frequency tSCK(5) Low level tSCKL(5) Specification Pin/ Conditions Remarks SCK4(P24) VDD[V] See Fig. 9. typ max unit 2 1 pulse width High level min tSCKH(5) 1 pulse width • USB, SIO0 continuous transfer tSCKHA(5a) mode, AIF, SIO9, and DMCOPY 4 not used at the same time. Input clock • See Fig. 9. • (Note 4-3-2) • USB used at the same time tSCKHA(5b) 2.7 to 5.5 • SIO0 continuous transfer mode, tCYC AIF, SIO9, and DMCOPY not 7 used at the same time. • See Fig. 9. • (Note 4-3-2) • USB, SIO0 continuous transfer tSCKHA(5c) mode, SIO9, and DMCOPY used at the same time. 12 • AIF not used at the same time. • See Fig. 9. Serial clock • (Note 4-3-2) Frequency tSCK(6) SCK4(P24) • When CMOS output type is 4/3 selected. Low level tSCKL(6) • See Fig. 9. 1/2 pulse width High level tSCK tSCKH(6) 1/2 pulse width (Note 4-3-3) tSCKHA(6a) • USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY tSCKH(6) not used at the same time. • When CMOS output type is Output clock selected. tSCKH(6) + + (5/3)tCYC (10/3)tCYC tSCKH(6) tSCKH(6) • See Fig. 9. tSCKHA(6b) • USB used at the same time. • SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time. • When CMOS output type is 2.7 to 5.5 + + (5/3)tCYC (19/3)tCYC tSCKH(6) tSCKH(6) tCYC selected. • See Fig. 9. tSCKHA(6c) • USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time. • AIF not used at the same time. • When CMOS output type is + + (5/3)tCYC (34/3)tCYC selected. • See Fig. 9. Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following conditions: Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V Continued on next page. No.A1453-17/27 LC87F1JJ2A Continued from preceding page. Parameter Serial input Data setup time Symbol tsDI(3) Specification Pin/ Conditions Remarks SO4(P22), SI4(P23) VDD[V] to rising edge of SIOCLK. • See Fig. 9 Data hold time min typ max unit • Must be specified with respect 0.03 2.7 to 5.5 thDI(3) 0.03 Output delay time tdDO(5) SO4(P22), Serial output SI4(P23) μs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state (1/3)tCYC 2.7 to 5.5 +0.05 change in open drain output mode. • See Fig. 9. 4. SIO9 Serial I/O Characteristics (Note 4-4-1) Parameter Symbol Frequency tSCK(7) Low level tSCKL(7) Specification Pin/ Conditions Remarks SCK9(P27) VDD[V] See Fig. 9. tSCKH(7) • USB, SIO0 continuous transfer 4 not used at the same time. Input clock unit 1 mode, AIF, SIO4, and DMCOPY Serial clock max 1 pulse width tSCKHA(7a) typ 2 pulse width High level min • See Fig. 9. • (Note 4-4-2) tSCKHA(7b) • USB used at the same time. 2.7 to 5.5 tCYC • SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time. 7 • See Fig. 9. • (Note 4-4-2) tSCKHA(7c) • USB, SIO0 continuous transfer mode, SIO4, and DMCOPY used at the same time. • AIF not used at the same time. 15 • See Fig. 9. • (Note 4-4-2) Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-4-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI9RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page. No.A1453-18/27 LC87F1JJ2A Continued from preceding page. Parameter Frequency Symbol tSCK(8) Specification Pin/ Conditions Remarks SCK9(P27) VDD[V] • When CMOS output type is typ 1/2 pulse width High level tSCK tSCKH(8) 1/2 pulse width (Note 4-4-3) • USB, SIO0 continuous transfer tSCKHA(8a) mode, AIF, SIO4, and DMCOPY tSCKH(8) not used at the same time. • When CMOS output type is Output clock selected. Serial clock unit tCYC • See Fig. 9. tSCKL(8) max 4/3 selected. Low level min tSCKH(8) + + (5/3)tCYC (10/3)tCYC tSCKH(8) tSCKH(8) • See Fig. 9. • USB used at the same time. tSCKHA(8b) • SIO0 continuous transfer mode, 2.7 to 5.5 AIF, SIO4, and DMCOPY not used at the same time. • When CMOS output type is + + (5/3)tCYC (19/3)tCYC tSCKH(8) tSCKH(8) tCYC selected • See Fig. 9. • USB, SIO0 continuous transfer tSCKHA(8c) mode , SIO4, and DMCOPY used at the same time. • AIF not used at the same time. • When CMOS output type is + + (5/3)tCYC (43/3)tCYC selected. • See Fig. 9. Serial input Data setup time SO9(P25), SI9(P26) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 9. Data hold time 0.03 2.7 to 5.5 thDI(4) 0.03 Output delay time Serial output tsDI(4) tdDO(6) SO9(P25), SI9(P26) μs • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output 2.7 to 5.5 (1/3)tCYC +0.05 mode • See Fig. 9. Note 4-4-3: When using the serial clock output, make sure that the load at the SCK9 (P27) pin meets the following conditions: Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V No.A1453-19/27 LC87F1JJ2A Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), INT1(P71), • Interrupt source flag can be set. pulse width tPIL(1) INT2(P72), • Event inputs for timer 0 or 1 are INT4(P20 to P23), enabled. INT5(P24 to P27), min typ 2.7 to 5.5 1 2.7 to 5.5 2 2.7 to 5.5 64 2.7 to 5.5 256 2.7 to 5.5 4 2.7 to 5.5 200 max unit INT6(P20), INT7(P24) tPIH(2) INT3(P73) when noise • Interrupt source flag can be set. tPIL(2) filter time constant is • Event inputs for timer 0 are 1/1 tPIH(3) INT3(P73) when noise • Interrupt source flag can be set. tPIL(3) filter time constant is • Event inputs for timer 0 are 1/32 enabled. tPIH(4) INT3(P73) when noise • Interrupt source flag can be set. tPIL(4) filter time constant is • Event inputs for timer 0 are 1/128 tPIL(5) RMIN(P73) enabled. Recognized by the infrared remote control receiver circuit as a signal tPIL(6) tCYC enabled. RES Resetting is enabled. RMCK (Note 5-1) μs Note 5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock) for the infrared remote control receiver circuit. AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Resolution N AN0(P00) to Absolute ET AN7(P07), Conversion time TCAD AN9(P71), AD conversion time=32×tCYC AN10(XT1), (when ADCR2=0) (Note 6-2) 4.5 to 5.5 3.0 to 5.5 AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 3.0 to 5.5 VAIN 3.0 to 5.5 voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 max unit 8 bit ±1.5 3.0 to 5.5 AN11(XT2) Analog input typ 3.0 to 5.5 (Note 6-1) AN8(P70), accuracy min 15.68 97.92 (tCYC= (tCYC= 0.490µs) 3.06µs) 23.52 97.92 (tCYC= (tCYC= 0.735µs) 3.06µs) 18.82 97.92 (tCYC= (tCYC= 0.294µs) 1.53µs) 47.04 97.92 (tCYC= (tCYC= 0.735µs) 1.53µs) VSS VDD 1 -1 LSB μs V μA Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the period from the time when an instruction for starting a conversion process is issued to the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. No.A1453-20/27 LC87F1JJ2A Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Parameter Symbol Specification Pin/ Conditions Remarks VDD[V] • FmCF=12MHz ceramic oscillation mode consumption VDD1 =VDD2 current =VDD3 • System clock set to 12MHz side Normal mode (Note 7-1) IDDOP(1) IDDOP(2) • FsX'tal=32.768kHz crystal oscillation mode min typ max 4.5 to 5.5 11 27 3.0 to 3.6 6.2 16 4.5 to 5.5 16 37 3.0 to 3.6 8.0 21 4.5 to 5.5 7.2 17 3.0 to 3.6 4.4 11 unit • Internal PLL oscillation stopped • Internal RC oscillation stopped • USB circuit stopped • 1/1 frequency division ratio IDDOP(3) • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side IDDOP(4) • Internal PLL oscillation mode active • Internal RC oscillation stopped • USB circuit active mA • 1/1 frequency division ratio IDDOP(5) • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode IDDOP(6) • System clock set to 6MHz side IDDOP(7) • Internal RC oscillation stopped • 1/2 frequency division ratio 2.7 to 3.0 3.6 8.2 IDDOP(8) • FmCF=0Hz (oscillation stopped) 4.5 to 5.5 0.77 3.7 • System clock set to internal RC oscillation 3.0 to 3.6 0.43 2.0 IDDOP(10) • 1/2 frequency division ratio 2.7 to 3.0 0.36 1.6 IDDOP(11) • FmCF=0Hz (oscillation stopped) 4.5 to 5.5 47 184 3.0 to 3.6 19 65 2.7 to 3.0 15 51 4.5 to 5.5 4.9 12 3.0 to 3.6 2.7 6.4 4.5 to 5.5 9.5 23 3.0 to 3.6 4.7 12 4.5 to 5.5 3.0 7.3 3.0 to 3.6 1.6 3.8 2.7 to 3.0 1.3 2.9 4.5 to 5.5 0.41 2.0 3.0 to 3.6 0.20 0.95 2.7 to 3.0 0.17 0.70 IDDOP(9) • FsX'tal=32.768kHz crystal oscillation mode • FsX'tal=32.768kHz crystal oscillation mode IDDOP(12) • System clock set to crystal oscillation side (32.768kHz) IDDOP(13) • Internal RC oscillation stopped • 1/2 frequency division ratio HALT mode IDDHALT(1) μA • HALT mode consumption • FmCF=12MHz ceramic oscillation mode current • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side (Note7-1) IDDHALT(2) • Internal PLL oscillation stopped • Internal RC oscillation stopped • USB circuit stopped • 1/1 frequency division ratio IDDHALT(3) • HALT mode • FmCF=12MHz ceramic oscillation mode • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side IDDHALT(4) • Internal PLL oscillation mode active • Internal RC oscillation stopped • USB circuit active mA • 1/1 frequency division ratio IDDHALT(5) • HALT mode • FmCF=12MHz ceramic oscillation mode IDDHALT(6) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to 6MHz side IDDHALT(7) • Internal RC oscillation stopped • 1/2 frequency division ratio IDDHALT(8) IDDHALT(9) IDDHALT(10) • HALT mode • FmCF=0Hz (oscillation stopped) • FsX'tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • 1/2 frequency division ratio Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.A1453-21/27 LC87F1JJ2A Continued from preceding page. Parameter Symbol HALT mode IDDHALT(11) consumption current IDDHALT(12) Specification Pin/ Conditions Remarks VDD[V] VDD1 =VDD2 • HALT mode =VDD3 • FsX'tal=32.768kHz crystal oscillation mode typ max unit 4.5 to 5.5 31 132 3.0 to 3.6 9.1 53 2.7 to 3.0 6.3 42 • HOLD mode 4.5 to 5.5 0.24 72 • CF1=VDD or open (External clock mode) 3.0 to 3.6 0.12 38 2.7 to 3.0 0.11 33 • FmCF=0Hz (oscillation stopped) • System clock set to crystal oscillation side (Note 7-1) min (32.768kHz) IDDHALT(13) • Internal RC oscillation stopped • 1/2 frequency division ratio HOLD mode IDDHOLD(1) consumption IDDHOLD(2) current VDD1 IDDHOLD(3) Timer HOLD IDDHOLD(4) • Timer HOLD mode 4.5 to 5.5 26 115 mode IDDHOLD(5) • CF1=VDD or open (External clock mode) 3.0 to 3.6 6.1 50 2.7 to 3.0 3.8 40 consumption • FsX’tal=32.768kHz crystal oscillation mode IDDHOLD(6) current μA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Conditions min typ max unit High level output VOH(USB) • 15kΩ±5% to GND 2.8 3.6 V Low level output VOL(USB) • 1.5kΩ±5% to 3.6V 0.0 0.3 V Output signal crossover voltage VCRS 1.3 2.0 Differential input sensitivity VDI Differential input common mode range VCM 0.8 High level input VIH(USB) 2.0 Low level input VIL(USB) USB data rise time tR • RS=33Ω, CL=50pF USB data fall time tF • RS=33Ω, CL=50pF • ⏐(UHD+)-(UHD-)⏐ 0.2 V V 2.5 V V 0.8 V 4 20 ns 4 20 ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Parameter Onboard programming Symbol IDDFW(1) Pin/ Remarks VDD1 current Programming time Specification Conditions VDD[V] • Excluding power dissipation in the microcontroller block tFW(1) • Erase operation tFW(2) • Write operation 3.0 to 5.5 min typ max unit 10 mA 20 30 ms 40 60 μs 5 3.0 to 5.5 Main System Clock Oscillation The constant values of the oscillator and oscillation circuit for the main and system clocks must be determined after exercising extensive oscillation evaluation tests. For an application in which the USB host function is to be used, use an oscillator having the accuracy and precision that satisfy the USB specifications. The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4): • Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit. • Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed. • Till the oscillation gets stabilized after the HOLD mode is released. • Till the oscillation gets stabilized after the X'tal HOLD mode is released with CFSTOP (OCR register, bit 0) set to 0. No.A1453-22/27 LC87F1JJ2A Subsystem Clock Oscillation Table 1 shows the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Vendor Name Frequency Circuit Constant Oscillator Name Operating C3 C4 Rf Rd2 [pF] [pF] [Ω] [Ω] 18 18 OPEN 560k Voltage Range [V] Oscillation Stabilization Time typ max [s] [s] 1.1 3.0 Remarks Applicable CL 32.768kHz EPSON TOYOCOM MC-306 2.7 to 5.0 value=12.5pF SMD type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4): • Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed. • Till the oscillation gets stabilized after the HOLD mode is released with EXTOSC (OCR register, bit 6) set to 1. Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 XT2 Rf Rd1 C1 CF C2 Figure 1 CF Oscillator Circuit Rd2 C3 X’tal C4 Figure 2 Crystal Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1453-23/27 LC87F1JJ2A VDD Operating VDD lower limit Power supply GND Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Execute oscillation enable instruction. Operating mode Unpredictable Instruction execution Reset Reset Time and Oscillation Stabilization Time HOLD release signal valid HOLD release signal Internal RC oscillation tmsCF CF1, CF2 tmsX’tal * When oscillation is enabled before entry into HOLD mode XT1, XT2 Operating mode HOLD HALT HOLD Release Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time No.A1453-24/27 LC87F1JJ2A P34/UFILT When using the internal PLL circuit to generate the 48MHz clock for USB, it is necessary to connect a filter circuit to the P34/UFILT pin such as that shown in the left figure. Rd 0kΩ + Cd - 2.2μF Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit P33/AFILT + Cp 1μF - Rd 150Ω + - Cd 4.7μF To generate the master clock for the audio interface using the internal PLL circuit, it is necessary to connect a filter circuit to the P33/AFILT pin that is shown in the left figure. Figure 6 External Filter Circuit for Audio Interface (Used with Internal PLL Circuit) 33Ω UHD+ 5pF 15kΩ It is necessary to adjust the Circuit Constant of the USB Port Peripheral Circuit for each mounting board. 33Ω UHD5pF 15kΩ Figure 7 USB Port Peripheral Circuit No.A1453-25/27 LC87F1JJ2A VDD Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC's operating voltage. RRES RES CRES Figure 8 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transfer period (SIO0, 4, 9 only) tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0, 4, 9 only) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 9 Serial I/O Waveform No.A1453-26/27 LC87F1JJ2A tPIL tPIH Figure 10 Pulse Input Timing Signal Waveform Voh tr D+ tr 90% 90% Vcrs 10% Vol 10% D- Figure 11 USB Data Signal Timing and Voltage Level VIH(1) min=0.3VDD+0.7V tSCKR tSCKR: Defined as the time period from the time the state of the output starts changing till the time it reaches the value of VIH(1). Figure 12 Serial Clock Output Timing Signal Waveform ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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