ENA1951 D

Ordering number : ENA1951
LC88F58B0A
CMOS IC
FROM 128K byte, RAM 6K byte on-chip
http://onsemi.com
16-bit 1-chip Microcontroller
Overview
The LC88F58B0A is a 16-bit microcomputer that, centered around an Xstromy16 CPU, integrates on a single chip a
number of hardware features such as 128K-byte flash ROM (onboard programmable), 6K-byte RAM, six 16-bit
timers, a base timer serving as a time-of-day clock, two synchronous SIO interfaces with automatic transmission
capability, a single master I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a 11-channel
12-bit resolution AD converter, a motor drive signal generator circuit, two multifrequency 12-bit PWM modules, a
watchdog timer, a system clock frequency divider, a 40-source (24 modules) 16-vector interrupt feature, and on-chip
debugger feature.
Features
Xstromy16 CPU
• 4G-byte address space
• General-purpose registers: 16 bits × 16 registers
Flash ROM
• Capable of onboard programming with a wide range of voltage levels (3.0 to 5.5V).
• Block-erasable in 128 or 1K byte units.
• Data written in 2-byte units.
• 131072 × 8 bits
RAM
• 6144 × 8 bits
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.03
41311HKIM 20080924-S00002 No.A1951-1/31
LC88F58B0A
Minimum Instruction Cycle Time (tCYC)
• 83.3 ns (12MHz)
VDD = 4.5 to 5.5V
• 100 ns (10MHz)
VDD = 3.0 to 5.5V
• 500 ns (2MHz)
VDD = 2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units : 52 (P0n, P1n, P2n, P30 to P33, P4n, P6n, P70 to P72,
PA0 to PA3, PC2)
• Oscillation/normal withstand voltage I/O ports
: 2 (PC0, PC1)
• Oscillation dedicated ports
: 2 (CF1, CF2)
• Reset pins
: 1 (RESB)
• TEST pins
: 1 (TEST)
• Power pins
: 6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16-bit timer that supports PWM/toggle outputs
1) 5-bit prescaler
2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 1: 16-bit timer with capture registers
1) 5-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator
• Timer 2: 16-bit timer with capture registers
1) 4-bit prescaler
2) May be divided into 2 channels of 8-bit timer
3) Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 3: 16-bit timer that supports PWM/toggle outputs
1) 8-bit prescaler
2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable
3) Clock source selectable from system clock, OSC0, OSC1, and external events
• Timer 4: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Timer 5: 16-bit timer that supports toggle outputs
1) Clock source selectable from system clock and prescaler 0
• Base timer
1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock.
2) Interrupts can be generated in 7 timing schemes.
No.A1951-2/31
LC88F58B0A
Serial Interfaces
• SIO0: 8-bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
4) Continuous/automatic data transmission (9- to 32768-bit units specifiable)
5) Interval function (intervals specifiable in 0 to 64 tSCK units)
6) Wakeup function
• SIO1: 8-bit synchronous SIO
1) LSB first/MSB first mode selectable
2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable)
3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks)
4) Continuous/automatic data transmission (9- to 32768-bit units specifiable)
5) Interval function (intervals specifiable in 0 to 64 tSCK units)
6) Wakeup function
• SMIIC0: Single master I2C/8-bit synchronous SIO
Mode 0: Single-master mode communication
Mode 1: Synchronous 8-bit serial I/O (MSB first)
• UART0
1) Data length
: 8 bits (LSB first)
2) Start bits
: 1 bit
3) Stop bits
: 1 bit
4) Parity bits
: None/even parity/odd parity
5) Transfer rate
: 4/8 cycle
6) Baudrate source clock : P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source)
7) Full duplex communication
Note: The “cycle” refers to one period of the baudrate clock source.
• UART2
1) Data length
: 8 bits (LSB first)
2) Start bits
: 1 bit
3) Stop bits
: 1/2 bit
4) Parity bits
: None/even parity/odd parity
5) Transfer rate
: 8 to 4096 cycle
6) Baudrate source clock : System clock/OSC0/OSC1
7) Wakeup function
8) Full duplex communication
Note: The “cycle” refers to one period of the baudrate clock source.
AD Converter
1) 12/8 bits resolution selectable
2) Analog input: 11 channels
3) Comparator mode
4) Automatic reference voltage generation
PWM
• PWM0: Multifrequency 12-bit PWM × 2 channels (PWM0A and PWM0B)
1) 2-channel pairs controlled independently of one another
2) Clock source selectable from system clock or OSC1
3) 8-bit prescaler: TPWMR0=(prescaler value + 1) × clock period
4) 8-bit fundamental wave PWM generator circuit + 4-bit additional pulse generator circuit
5) Fundamental wave PWM mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
6) Fundamental wave + additional pulse mode
Fundamental wave period : 16 TPWMR0 to 256 TPWMR0
Overall period
: Fundamental wave period × 16
High pulse width
: 0 to (Fundamental wave period - TPWMR0)
No.A1951-3/31
LC88F58B0A
Watchdog Timer
1) Driven by the base timer + internal watchdog timer dedicated counter
2) Interrupt or reset mode selectable
Motor Drive Signal Generator Circuit
Interrupts (peripheral function)
• 40 sources (24 modules), 16 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Interrupt Module
1
08000H
Watchdog timer (1)
2
08004H
Base timer (2)
3
08008H
Timer 0 (2)
4
0800CH
INT0 (1)
5
08010H
6
08014H
INT1 (1)
7
08018H
INT2 (1)/timer 1 (2)/UART2 (4)
8
0801CH
INT3 (1)/timer 2 (4)/SMIIC0 (1)
9
08020H
INT4 (1)/timer 3 (2)
10
08024H
INT5 (1)/timer 4 (1)/SIO1 (2)
11
08028H
USM0 (3)
12
0802CH
PWM0 (1)
13
08030H
ADC (1)/timer 5 (1)
14
08034H
INT6 (1)
15
08038H
INT7 (1)/SIO0 (2)
16
0803CH
Port 0 (3)
• 3 priority levels selectable.
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• A number enclosed in parentheses denotes the number of sources.
Subroutine Stack: 6K-byte RAM area
• Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes
• Subroutine calls that do not automatically save PSW: 4 bytes
Multiplication/Division Instructions
• 16 bits × 16 bits (18 tCYC execution time)
• 16 bits ÷ 16 bits (18 to 19 tCYC execution time)
• 32 bits ÷ 16 bits (18 to 19 tCYC execution time)
Oscillator Circuits
• RC oscillator circuit (internal): For system clock
• OSC1 (CF oscillator circuit): For system clock, built-in Rf circuit
• OSC0 (crystal oscillator circut): For low-speed system clock
• SLRC oscillator circuit (internal): For system clock (exception processing time)
System Clock Divider Function
• Can run on low current.
• 1/1 to 1/128 of the system clock frequency can be set.
No.A1951-4/31
LC88F58B0A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not stopped automatically.
2) Released by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) OSC1, RC and OSC0 oscillators automatically stop.
2) There are three ways of releasing the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt established at SIO0 or SIO1
(5) Having an interrupt established at UART2
• HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run
on OSC0.
1) OSC1 and RC oscillations automatically stop.
2) OSC0 maintains the state that is established when the HOLDX mode is entered.
3) There are four ways of releasing the HOLDX mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, INT5, INT6, and INT7 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established at the base timer circuit
(5) Having an interrupt established at SIO0 or SIO1
(6) Having an interrupt established at UART2
On-chip Debugger Function
• Supports software debugging with the IC mounted on the target board.
• Supports source line debugging and tracing functions, and breakpoint setting.
• Single-wire communication
Package Form
• SQFP64 (10×10): Lead-free and halogen-free type
Development Tools
• On-chip debugger: EOCUIF1 + LC88F58B0A
Programming Board
Package
Programming Board
SQFP64 (10 × 10)
W88F58SQ
Flash Programming
Manufacturer
Model Name
Supported Version
Device
Flash Support Group (Single)
AF9708/09/09B/09C
Revison : After Rev.03.04
LC88F58B0A
AF9723/23B
Revison : After Rev.02.29
LC88F58B0A
AF9833
Revison : After Rev.01.90
SKK/SKK Type-B
Revison : After Rev.01.13
Flash Support Group (Gang)
Our company
LC88F58B0A
No.A1951-5/31
LC88F58B0A
Package Dimensions
unit : mm (typ)
3190A
12.0
0.5
10.0
48
33
64
12.0
32
10.0
49
17
1
16
0.5
0.15
0.18
0.1
1.7max
(1.5)
(1.25)
SANYO : SQFP64(10X10)
P47/PWM0B
P46/PWM0A
VSS3
VDD3
P45/SCK1
P44/SI1/SB1
P43/SO1
P42
P41/INT7
P40/INT6
PA0/USM0O0
PA1/USM0O1
PA2/USM0O2
PA3/USM0O3
PC2/FILT
P33/INT3
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P32/INT2
49
32
P72/AN10
P31/INT1
50
31
P71/AN9
P30/INT0
51
30
P70/AN8
TEST
52
29
P17/U2TX
RESB
53
28
P16/U2RX
PC0/XT1
54
27
P15/T3OH
PC1/XT2
55
26
P14/T3OL/U0RX
VSS1
56
25
P13/U0TX
CF1
57
24
P12/SCK0
LC88F58B0A
P06/T0PWML
P62/AN2
62
19
P05/P05INT
P63/AN3
63
18
P04/P04INT
P64/AN4
64
17
P03/P0INT
8
9 10 11 12 13 14 15 16
P02/P0INT
7
P01/P0INT
6
P27
5
P00/P0INT
4
P26/T5O
3
P25/T4O
2
VSS2
1
VDD2
P07/T0PWMH/U0BRG
20
P24/SM0DO
21
61
P23/SM0DA
60
P61/AN1
P22/SM0CK
P60/AN0
P21/INT5
P10/SO0
P20/INT4
P11/SI0/SB0
22
P67/AN7
23
59
P66/AN6
58
P65/AN5
CF2
VDD1
Top view
SQFP64 (10×10) (Lead-free and halogen-free type)
No.A1951-6/31
LC88F58B0A
CF
RC
Base timer
X’tal
Low
speed
RC
Clock generator
System Block Diagram
Watchdog timer
FLASH ROM
Xstromy16
CPU
Timer 0
RAM
Timer 1
On-chip debugger
Timer 2
Port 0
Timer 3
Port 1
Timer 4
Port 2
Timer 5
Port 3
SIO0
Port 4
SIO1
Port 6
SMIIC0
Port 7
UART0
UART2
PWM0
AD
Port A
Port C
INT0 to INT7
Motor control signal
generator
No.A1951-7/31
LC88F58B0A
Pin Description
Pin Name
I/O
Description
VSS1, VSS2,
VSS3
-
- Power sources
VDD1, VDD2,
VDD3
-
+ Power sources
Port 0
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1 bit units
• HOLD release input (P00 to P03, P04, P05)
• Port 0 interrupt input (P00 to P03, P04, P05)
• Pin functions
P06: Timer 0L output
P07: Timer 0L output/UART0 clock input
Port 1
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/pulse input/output
P12: SIO0 clock input/output
P13: UART0 transmit
P14: Timer 3L output/UART0 receive
P15: Timer 3H output
P16: UART2 receive
P17: UART2 transmit
Port 2
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input
P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input
P22: SMIIC0 clock input/output
P23: SMIIC0 bus input/output/data input
P24: SMIIC0 data output (used in 3-wire SIO mode)
P25: Timer 4 output
P26: Timer 5 output
Interrupt acknowledge type
INT4, INT5: H level, L level, H edge, L edge, both edges
Port 3
P30 to P33
I/O
• 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P30: INT0 input/HOLD release/timer 2L capture input
P31: INT1 input/HOLD release/timer 2H capture input
P32: INT2 input/HOLD release/timer 2 event input/timer 2L capture input
P33: INT3 input/HOLD release/timer 2 event input/timer 2H capture input
Interrupt acknowledge type
INT0 to INT3: H level, L level, H edge, L edge, both edges
Continued on next page.
No.A1951-8/31
LC88F58B0A
Continued from preceding page.
Pin Name
Port 4
I/O
I/O
Description
• 8-bit I/O port
• I/O specifiable in 1-bit units
P40 to P47
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
P40: INT6 input/HOLD release input
P41: INT7 input/HOLD release input
P43: SIO1 data output
P44: SIO1 data input/bus input/output
P45: SIO1 clock input/output
P46: PWM00 output
P47: PWM01 output
Interrupt acknowledge type
INT6, INT7: H level, L level, H edge, L edge, both edges
Port 6
I/O
• 8-bit I/O port
• I/O specifiable in 1-bit units
P60 to P67
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
AN0 (P60) to AN7 (P67): AD converter input port
Port 7
I/O
• 3-bit I/O port
• I/O specifiable in 1-bit units
P70 to P72
• Pull-up resistors can be turned on and off in 1 bit units
• Pin functions
AN8 (P70) to AN10 (P72): AD converter input port
Port A
I/O
• 4-bit I/O port
• I/O specifiable in 1-bit units
PA0 to PA3
• Pull-up resistors can be turned on and off in 1 bit units
• Multiplexed pin functions
PA0: USM0 output 0
PA1: USM0 output 1
PA2: USM0 output 2
PA3: USM0 output 3
Port C
I/O
• 3-bit I/O port (on output: Nch-open drain (PC0 to PC1), CMOS (PC2))
• I/O specifiable in 1-bit units
PC0 to PC2
• Pin functions
PC0: 32.768kHz crystal oscillator input
PC1: 32.768kHz crystal oscillator output
PC2: FILT
TEST
I/O
• TEST pin
• Used to communicate with on-chip debugger.
• Connects an external 100kΩ pull-down resistor.
RESB
I
Reset pin
CF1
I
Ceramic oscillator input pin
CF2
O
Ceramic oscillator output pin
No.A1951-9/31
LC88F58B0A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
Option Selected in
Units of
1 bit
Option Type No.
Output Type
1
CMOS
2
N-channel open drain
CMOS
Pull-up Resistor
Programmable
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P60 to P67
P70 to P72
PA0 to PA3
PC2
-
-
PC0
-
-
N-channel open drain
None
(32.768kHz crystal oscillator input)
PC1
-
-
N-channel open drain
None
(32.768kHz crystal oscillator output)
* Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2 and VSS3 pins.
Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the
backup capacitors.
LSI
VDD1
Power
supply
PC2/FILT
For buckup
1kΩ
VDD2
+
-
2.2μF
VDD3
VSS1 VSS2 VSS3
Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is
unpredictable.
LSI
VDD1
Power
supply
PC2/FILT
For buckup
1kΩ
VDD2
+
-
2.2μF
VDD3
VSS1 VSS2 VSS3
No.A1951-10/31
LC88F58B0A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Maximum supply
Symbol
Applicable Pin
/Remarks
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
CF1, RESB
Input/output
VIO(1)
Ports 0, 1, 2
Specification
Conditions
VDD[V]
VDD1=VDD2=VDD3
voltage
voltage
Ports 3, 4
min
typ
-0.3
+6.5
-0.3
VDD
+0.3
unit
V
VDD
+0.3
-0.3
Ports 6, 7
max
Ports A, C
Peak output
IOPH(1)
current
Ports 0, 1, 2
CMOS output selected
P70 to P72
Per applicable pin
P40 to P45
-10
PA0 to PA3
IOPH(2)
P46, P47
Per applicable pin
IOPH(3)
Port 6
Per applicable pin
-20
-5
P30 to P33
PC2
Average
Ports 0, 1, 2
CMOS output selected
output
IOMH(1)
P70 to P72
Per applicable pin
current
P36 to P37
(Note 1-1)
P40 to P45
-7.5
High level output current
PA0 to PA3
IOMH(2)
P46, P47
Per applicable pin
IOMH(3)
Port 6
Per applicable pin
P30 to P33
-10
-3
PC2
Total output
ΣIOAH(1)
P30 to P33, PC2
current
Total of currents at
applicable pins
ΣIOAH(2)
Port 6
Total of currents at
applicable pins
ΣIOAH(3)
Port 6
Total of currents at
P30 to P33
applicable pins
-15
mA
-15
-20
PC2
ΣIOAH(4)
ΣIOAH(5)
Ports 0, 1
Total of currents at
P25 to P27
applicable pins
P20 to P24
Total of currents at
applicable pins
ΣIOAH(6)
Ports 0, 1, 2
Total of currents at
applicable pins
ΣIOAH(7)
ΣIOAH(8)
ΣIOAH(9)
P40 to P45
Total of currents at
PA0 to PA3
applicable pins
P46 to P47
Total of currents at
P70 to P72
applicable pins
Port 4
Total of currents at
P70 to P72
applicable pins
-25
-25
-45
-25
-25
-45
PA0 to PA3
Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms.
Continued on next page.
No.A1951-11/31
LC88F58B0A
Continued from preceding page.
Parameter
Peak output
Symbol
IOPL(1)
current
Applicable Pin
/Remarks
Ports 0, 1, 4
Specification
Conditions
VDD[V]
min
typ
max
unit
Per applicable pin
P70 to P72
20
PA0 to PA3
P20, P21, P24 to P27
IOPL(2)
P22, P23
Per applicable pin
IOPL(3)
P30 to P33
Per applicable pin
25
Port 6
10
PC0 to PC2
Average
IOML(1)
Ports 0, 1, 4
output current
P70 to P72
(Note 1-1)
PA0 to PA3
Per applicable pin
15
Low level output current
P20, P21, P24 to P27
IOML(2)
P22, P23
Per applicable pin
IOML(3)
P30 to P33
Per applicable pin
20
Port 6
7.5
PC0 to PC2
Total output
ΣIOAL(1)
P30 to P34
Total of currents at
PC0 to PC2
applicable pins
ΣIOAL(2)
Port 6
Total of currents at
ΣIOAL(3)
Port 6
Total of currents at
P30 to P33
applicable pins
current
15
mA
15
applicable pins
20
PC0 to PC2
ΣIOAL(4)
ΣIOAL(5)
Ports 0, 1
Total of currents at
P25 to P27
applicable pins
P20 to P24
45
Total of currents at
45
applicable pins
ΣIOAL(6)
Ports 0, 1, 2
Total of currents at
80
applicable pins
ΣIOAL(7)
ΣIOAL(8)
ΣIOAL(9)
P40 to P45
Total of currents at
PA0 to PA3
applicable pins
P46 to P47
Total of currents at
P70 to P72
applicable pins
Port 4
Total of currents at
P70 to P72
applicable pins
45
45
80
PA0 to PA3
Allowable power
Pd max
SQFP64 (10×10)
Ta=-40 to +85°C
200
dissipation
Operating ambient
Topr
temperature
Storage ambient
temperature
Tstg
-40
+85
-55
+125
mW
°C
Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1951-12/31
LC88F58B0A
Allowable Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
VDD(1)
VDD1=VDD2=VDD3
(Note 2-1)
VHD
Conditions
/Remarks
supply voltage
Memory
Specification
Applicable Pin
Symbol
VDD1=VDD2=VDD3
sustaining
VDD[V]
min
typ
max
unit
0.081μs≤tCYC≤66μs
4.5
5.5
0.098μs≤tCYC≤66μs
3.0
5.5
0.490μs≤tCYC≤66μs
2.2
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode
supply voltage
High level input
VIH(1)
voltage
Ports 0, 1, 2, 3, 4
2.2 to 5.5
Port A
VIH(2)
Ports 6, 7, PC2
VIH(3)
CF1, RESB
PC0, PC1
VIH(4)
Low level input
VIL(1)
voltage
P22, P23 I C side
When ports 1, 2, 3, 4
PnFSAn=0
Ports 0, 6, 7, PC2
VIL(3)
When ports 1, 2, 3, 4
and port A,
VIL(4)
PnFSAn=1
VIL(5)
CF1, RESB
PC0, PC1
VIL(6)
Instruction
2
P22, P23 I C side
tCYC
cycle time
(Note 2-2)
External
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
system clock
frequency
+0.7
VDD
2.2 to 5.5
0.3VDD
+0.7
VDD
2.2 to 5.5
0.75VDD
VDD
2.2 to 5.5
0.7VDD
4.0 to 5.5
VSS
VDD
0.1VDD
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
0.2VDD
2.2 to 5.5
VSS
0.25VDD
0.3VDD
V
2
and port A,
VIL(2)
0.3VDD
division ratio=1/1
+0.4
0.2VDD
0.15VDD
+0.4
2.2 to 5.5
VSS
4.5 to 5.5
0.081
66
3.0 to 5.5
0.098
66
2.2 to 5.5
0.490
66
4.5 to 5.5
0.1
12
3.0 to 5.5
0.1
10
μs
• External system clock
DUTY50±5%
2.2 to 5.5
0.1
2
• CF2 pin open
4.5 to 5.5
0.2
24
• System clock frequency
3.0 to 5.5
0.2
20
2.2 to 5.5
0.2
4
division ratio=1/2
Oscillation
FmCF(1)
CF1, CF2
12MHz ceramic oscillator
frequency
mode
range
See Fig. 1.
(Note 2-3)
FmCF(2)
CF1, CF2
4.5 to 5.5
12
3.0 to 5.5
10
10MHz ceramic oscillator
mode
MHz
See Fig. 1.
FmCF(3)
CF1, CF2
MHz
4MHz ceramic oscillator
mode
2.2 to 5.5
4
See Fig. 1.
FmRC
Internal RC oscillation
FmSLRC
Internal low-speed RC
oscillation
FsX'tal
XT1, XT2
2.2 to 5.5
0.5
1.0
2.0
2.2 to 5.5
18
30
45
kHz
32.768kHz crystal oscillator
mode
2.2 to 5.5
32.768
See Fig. 2.
Note 2-1: VDD≥3.0V must be maintained when making onboard programming into flash ROM.
Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and
2/FmCF when the ratio is 1/2.
Note 2-3: See Tables 1 and 2 for oscillator constant values.
No.A1951-13/31
LC88F58B0A
Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
High level input
Symbol
IIH(1)
current
Low level input
Specification
Applicable Pin
Conditions
/Remarks
VDD[V]
Ports 0, 1, 2
Output disabled
Ports 3, 4
Pull-up resistor off
Ports 6, 7
Ports A, C
VIN=VDD
(Including output Tr. off leakage
RESB
current)
IIH(2)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
Ports 3, 4
Pull-up resistor off
Ports 6, 7
VIN=VSS
(Including output Tr. off leakage
current
Ports A, C
min
typ
2.2 to 5.5
1
2.2 to 5.5
15
2.2 to 5.5
RESB
current)
CF1
VIN=VSS
2.2 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2
IOH=-1.0mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
PA0 to PA3
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
VOH(3)
VOH(4)
VOH(5)
VOH(6)
Low level output
P30 to P33
PC2
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(8)
IOH=-1.0mA
2.2 to 5.5
VDD-0.4
IOL=10mA
4.5 to 5.5
1.5
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1.0mA
2.2 to 5.5
0.4
IOL=11mA
4.5 to 5.5
1.5
VOL(5)
IOL=3.0mA
3.0 to 5.5
0.4
VOL(6)
IOL=1.3mA
2.2 to 5.5
0.4
VOL(1)
voltage
P46, P47
Ports 0, 1
VOL(3)
VOL(4)
V
P20 to P21,
P24 to P27
PA0 to PA3
P22, P23
VOL(7)
Ports 6, C
IOL=1.6mA
3.0 to 5.5
0.4
VOL(8)
P30 to P33
IOL=1.0mA
2.2 to 5.5
0.4
Rpu(1)
Ports 0, 1, 2, 3
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.2 to 4.5
18
55
150
Ports 4, 6, 7
Rpu(2)
Hysteresis
μA
Ports 4, 7
VOL(2)
Pull-up resistor
Port 6
unit
-1
IIL(2)
P40 to P45
max
VHYS
voltage
kΩ
Ports A, PC2
RESB
When ports 1, 2, 3,
4, A
2.2 to 5.5
0.1VDD
V
2.2 to 5.5
10
pF
PnFSAn=1
Pin capacitance
CP
All pins
Pins other than that under test
VIN=VSS
f=1MHz
Ta=25°C
No.A1951-14/31
LC88F58B0A
Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1)
Parameter
Symbol
Period
tSCK(1)
Low level
tSCKL(1)
Specification
Applicable
Conditions
Pin/Remarks
SCK0 (P12)
VDD[V]
• See Fig. 6.
tSCKHA(1)
Input clock
tSCKH(1)
pulse width
typ
max
unit
4
2
pulse width
High level
min
2
• Automatic communication
mode
• See Fig. 6.
6
2.2 to 5.5
tCYC
• Automatic communication
tSCKHBSY(1a)
mode
23
• See Fig. 6.
• Mode other than automatic
tSCKHBSY(1b)
communication mode
4
Serial clock
• See Fig. 6.
Period
tSCK(2)
SCK0 (P12)
• CMOS output selected
4
• See Fig. 6.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
• Automatic communication
Output clock
tSCKHA(2)
mode
• CMOS output selected
2.2 to 5.5
6
• See Fig. 6.
• Automatic communication
tSCKHBSY(2a)
mode
4
• CMOS output selected
23
tCYC
• See Fig. 6.
• Mode other than automatic
tSCKHBSY(2b)
communication mode
4
• See Fig. 6.
Serial input
Data setup time
SI0 (P11),
SB0 (P11)
• Specified with respect to rising
edge of SIOCLK
• See Fig. 6.
Data hold time
thDI(1)
0.03
2.2 to 5.5
0.03
Output clock
Input clock
Output
Serial output
tsDI(1)
tdD0(1)
delay time
SO0 (P10),
• (Note 4-1-2)
SB0 (P11)
1tCYC
μs
+0.05
tdDO(2)
• (Note 4-1-2)
2.2 to 5.5
1tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig. 6.
No.A1951-15/31
LC88F58B0A
SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1)
Input clock
Serial clock
Parameter
Period
tSCK(3)
Low level
tSCKL(3)
Applicable
Pin/Remarks
SCK0 (P12)
Specification
Conditions
VDD[V]
• See Fig. 6.
typ
max
tSCKH(3)
pulse width
tSCKHBSY(3)
tsDI(2)
unit
2
2.2 to 5.5
High level
tCYC
1
2
SI0 (P11),
SB0 (P11)
• Specified with respect to
rising edge of SIOCLK
• See Fig. 6.
Data hold time
min
1
pulse width
Data setup time
Serial input
Symbol
thDI(2)
0.03
2.2 to 5.5
0.03
Input clock
Serial output
μs
Output
delay time
tdD0(3)
SO0 (P10),
• (Note 4-2-2)
SB0 (P11)
2.2 to 5.5
1tCYC
+0.05
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig.6.
No.A1951-16/31
LC88F58B0A
SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1)
Parameter
Symbol
Period
tSCK(4)
Low level
tSCKL(4)
Specification
Applicable
Conditions
Pin/Remarks
SCK1(P45)
VDD[V]
• See Fig. 6.
tSCKHA(4)
Input clock
tSCKH(4)
pulse width
typ
max
unit
4
2
pulse width
High level
min
2
• Automatic communication
mode
• See Fig. 6.
6
2.2 to 5.5
tCYC
• Automatic communication
tSCKHBSY(4a)
mode
23
• See Fig. 6.
• Mode other than automatic
tSCKHBSY(4b)
communication mode
4
Serial clock
• See Fig. 6.
Period
tSCK(5)
SCK1(P45)
• CMOS output selected
4
• See Fig. 6.
Low level
tSCKL(5)
1/2
pulse width
High level
tSCK
tSCKH(5)
1/2
pulse width
• Automatic communication
Output clock
tSCKHA(5)
mode
• CMOS output selected
2.2 to 5.5
6
• See Fig. 6.
• Automatic communication
tSCKHBSY(5a)
mode
4
• CMOS output selected
23
tCYC
• See Fig. 6.
• Mode other than automatic
tSCKHBSY(5b)
communication mode
4
• See Fig. 6.
Serial input
Data setup time
SI1(P44),
SB1(P44)
• Specified with respect to rising
edge of SIOCLK
• See Fig. 6.
Data hold time
thDI(3)
0.03
μs
2.2 to 5.5
0.03
Input clock
Output
tdD0(4)
delay time
SO1(P43),
• (Note 4-3-2)
SB1(P44)
1tCYC
+0.05
tdDO(5)
Output clock
Serial output
tsDI(3)
• (Note 4-3-2)
μs
2.2 to 5.5
1tCYC
+0.05
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig. 6.
No.A1951-17/31
LC88F58B0A
SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1)
Input clock
Serial clock
Parameter
Period
tSCK(6)
Low level
tSCKL(6)
Specification
Applicable
Conditions
Pin/Remarks
SCK1(P45)
VDD[V]
min
• See Fig. 6.
typ
1
High level
tSCKH(6)
1
pulse width
tSCKHBSY(6)
2
tsDI(4)
SI1(P44),
SB1(P44)
unit
tCYC
• Specified with respect to rising
edge of SIOCLK
• See Fig. 6.
Data hold time
max
2
2.2 to 5.5
pulse width
Data setup time
Serial input
Symbol
thDI(4)
0.03
2.2 to 5.5
0.03
Input clock
Serial output
μs
Output
tdD0(6)
delay time
SO1(P43),
• (Note 4-4-2)
SB1(P44)
1tCYC
2.2 to 5.5
+0.05
Note 4-4-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output
change begins in the open drain output mode. See Fig. 6.
SMIIC0 Simple SIO Mode Input/Output Characteristics
Input clock
Symbol
Period
tSCK(7)
Low level
tSCKL(7)
Specification
Applicable
Conditions
Pin/Remarks
SM0CK(P22)
VDD[V]
See Fig. 6.
2.2 to 5.5
pulse width
High level
Period
SM0CK(P22)
• CMOS output selected
tSCKL(8)
8
1/2
tSCK
tSCKH(8)
1/2
pulse width
Serial input
Data setup time
SM0DA(P23)
• Specified with respect to rising
edge of SIOCLK
• See Fig. 6.
Data hold time
thDI(5)
0.03
2.2 to 5.5
0.03
Output delay
Serial output
tsDI(5)
unit
4
2.2 to 5.5
pulse width
High level
max
4
• See Fig. 6.
Low level
typ
tCYC
tSCKH(7)
tSCK(8)
min
8
pulse width
Output clock
Serial clock
Parameter
time
tdD0(7)
SM0DO(P24),
SM0DA(P23)
μs
• Specified with respect to falling
edge of SIOCLK
• Specified as interval up to time
when output state starts
2.2 to 5.5
1tCYC
+0.05
changing.
• See Fig. 6.
Note 4-5-1: These specifications are theoretical values. Add margin depending on its use.
No.A1951-18/31
LC88F58B0A
SMIIC0 I2C Mode Input/Output Characteristics
Clock
Input clock
Parameter
Symbol
Period
tSCL
Low level
tSCLL
Specification
Applicable
Conditions
Pin/Remarks
SM0CK(P22)
VDD[V]
• See Fig. 8.
High level
Output clock
SM0CK(P22)
• Specified as interval up to time
tSCLLx
2.2 to 5.5
pulse width
High level
2.5
10
when output state starts changing.
Low level
1/2
tSCL
tSCLHx
1/2
pulse width
SM0CK and SM0DA
tsp
pins input spike
unit
2
pulse width
tSCLx
max
Tfilt
tSCLH
Period
typ
5
2.2 to 5.5
pulse width
min
SM0CK(P22)
• See Fig. 8.
SM0DA(P23)
1
Tfilt
suppression time
time between
start and stop
tBUF
SM0CK(P22)
• See Fig. 8.
SM0DA(P23)
Input
Bus release
2.5
SM0CK(P22)
• Standard clock mode
SM0DA(P23)
• Specified as interval up to time
Output
tBUFx
Tfilt
2.2 to 5.5
5.5
when output state starts changing.
μs
• High-speed clock mode
• Specified as interval up to time
1.6
when output state starts changing.
Start/restart
tHD;STA
condition hold
SM0DA(P23)
• When SMIIC register control bit,
I2CSHDS=0
2.0
• See Fig. 8.
Input
time
SM0CK(P22)
Tfilt
• When SMIIC register control bit,
2
I CSHDS=1
• See Fig. 8.
SM0CK(P22)
• Standard clock mode
SM0DA(P23)
• Specified as interval up to time
Output
tHD;STAx
2.5
2.2 to 5.5
4.1
when output state starts changing.
μs
• High-speed clock mode
• Specified as interval up to time
1.0
when output state starts changing.
time
tSU;STA
SM0CK(P22)
• See Fig. 8.
SM0DA(P23)
1.0
tSU;STAx
Output
condition setup
Input
Restart
SM0CK(P22)
• Standard clock mode
SM0DA(P23)
• Specified as interval up to time
2.2 to 5.5
5.5
when output state starts changing.
μs
• High-speed clock mode
• Specified as interval up to time
Tfilt
1.6
when output state starts changing.
Continued on next page.
No.A1951-19/31
LC88F58B0A
Continued from preceding page
Parameter
Symbol
setup time
tSU;STO
Input
Stop condition
Specification
Applicable
Conditions
Pin/Remarks
SM0CK(P22)
VDD[V]
SM0DA(P23)
typ
max
1.0
SM0CK(P22)
• Standard clock mode
SM0DA(P23)
• Specified as interval up to time
Output
tSU;STOx
min
unit
• See Fig. 8.
2.2 to 5.5
Tfilt
4.9
when output state starts changing.
μs
• High-speed clock mode
• Specified as interval up to time
1.1
when output state starts changing.
tHD;DAT
Input
Data hold time
Output
Input
Output
SM0CK(P22)
SM0DA(P23)
• Specified as interval up to time
2.2 to 5.5
when output state starts changing.
Tfilt
1
1.5
• See Fig. 8.
1
• Specified as interval up to time
2.2 to 5.5
when output state starts changing.
Tfilt
1tSCL
-1.5Tfilt
tF
Input
time
SM0CK(P22)
0
SM0DA(P23)
tSU;DATx
SM0DA pins fall
SM0CK(P22)
SM0DA(P23)
tSU;DAT
SM0CK and
• See Fig. 8.
SM0DA(P23)
tHD;DATx
Data setup time
SM0CK(P22)
SM0CK(P22)
• See Fig. 8.
SM0DA(P23)
tF
SM0CK (P22)
SM0DA (P23)
2.2 to 5.5
• When SMIIC register control bits,
5
PSLW=1, P5V=1
Output
• When SMIIC register control bits,
3
PSLW=1, P5V=0
300
20
+0.1Cb
20
+0.1Cb
250
ns
250
• SM0CK, SM0DA port output
FAST mode
3 to 5.5
100
• Cb≤400pF
Note 4-6-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and
the system clock frequency.
BRP1
BRP0
Tfilt
0
0
tCYC×1
0
1
tCYC×2
1
0
tCYC×3
1
1
tCYC×4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns ≥ Tfilt >140ns
Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 400pF
Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt >140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt >140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A1951-20/31
LC88F58B0A
UART2 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Transfer rate
Symbol
UBR2
Applicable
Pin/Remarks
Specification
Conditions
VDD[V]
U2RX(P16),
min
2.2 to 5.5
U2TX(P17)
typ
max
8
unit
4096
tBGCYC
Note 4-7: tBGCYC denotes one cycle of the baudrate clock source.
UART0 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Transfer rate
Symbol
UBR0
Applicable
Pin/Remarks
Specification
Conditions
VDD[V]
min
typ
max
unit
U0RX(P13),
U0TX(P14),
2.2 to 5.5
4
8
tBGCYC
U0BRG(P07)
Note 4-8: tBGCYC denotes one cycle of the baudrate clock source.
Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Applicable
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P30),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P31),
• Event inputs for timers 2 and 3
INT2(P32),
min
typ
max
unit
are enabled.
INT3(P33),
INT4(P20),
2.2 to 5.5
2
tCYC
2.2 to 5.5
10
μs
INT5(P21),
INT6(P40),
INT7(P41)
tPIL(2)
RESB
Resetting is enabled.
No.A1951-21/31
LC88F58B0A
AD Converter Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
12-bit AD Conversion Mode
Parameter
Applicable Pin
Symbol
/Remarks
Resolution
NAD
AN0(P60) to
Absolute accuracy
ETAD
AN7(P67),
Conversion time
TCAD12
AN8(P70) to
Specification
Conditions
VDD[V]
typ
2.9 to 5.5
max
unit
12
bit
(Note 6-1)
2.9 to 5.5
Conversion time calculated
4.7 to 5.5
17
209
4.0 to 5.5
27
209
2.9 to 5.5
67
209
2.9 to 5.5
VSS
VDD
AN11(P72)
Analog input
min
VAIN
voltage range
Analog port
IAINH
VAIN=VDD
2.9 to 5.5
input current
IAINL
VAIN=VSS
2.9 to 5.5
±16
1
-1
LSB
μs
V
μA
Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC
8-bit AD Conversion Mode
Parameter
Symbol
Applicable Pin
/Remarks
Resolution
NAD
AN0(P60) to
Absolute accuracy
ETAD
AN7(P67),
Conversion time
TCAD8
Analog input
AN8(P70) to
AN11(P72)
Specification
Conditions
VDD[V]
min
2.9 to 5.5
(Note 6-1)
Conversion time calculated
VAIN
voltage range
typ
max
unit
8
2.9 to 5.5
bit
±1.5
4.7 to 5.5
11
129
4.0 to 5.5
17
129
2.9 to 5.5
42
129
2.9 to 5.5
VSS
VDD
Analog port
IAINH
VAIN=VDD
2.9 to 5.5
input current
IAINL
VAIN=VSS
2.9 to 5.5
1
-1
LSB
μs
V
μA
Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy.
Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital value against the analog input value is loaded in the result register.
The conversion time is twice the normal value when one of the following conditions occurs:
• The first AD conversion is executed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion
mode.
No.A1951-22/31
LC88F58B0A
Consumption Current Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSS3=0V
typ: 5.0V (VDD=4.5V to 5.5V), 3.3V (VDD=3.0V to 4.5V, 2.2V to 4.5V)
Parameter
Symbol
Applicable
Pin/Remarks
Specification
Conditions
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz
Normal mode
IDDOP(1)
min
typ
max
unit
• FmX'tal=32.768kHz crystal oscillation mode
4.5 to 5.5
9.3
15.0
4.5 to 5.5
8.5
14.4
3.0 to 4.5
5.0
8.3
• Internal RC oscillation stopped
(Note 7-1)
• 1/1 frequency division mode
IDDOP(2)
• FmCF=10MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
IDDOP(3)
• System clock set to 10MHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
IDDOP(4)
• FmX'tal=32.768kHz crystal oscillator mode
IDDOP(5)
• Internal RC oscillation stopped
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
IDDOP(7)
• System clock set to internal RC oscillation
• 1/1 frequency division mode
IDDOP(8)
5.6
2.2 to 4.5
2.5
4.6
4.5 to 5.5
2.5
5.6
2.2 to 4.5
1.7
4.6
4.5 to 5.5
63
155
2.2 to 4.5
39
102
4.5 to 5.5
11.0
17.5
• System clock set to 32.768kHz
• Internal RC oscillation stopped
• 1/1 frequency division mode
IDDOP(10)
3.8
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
IDDOP(9)
4.5 to 5.5
• System clock set to 4MHz
• 1/2 frequency division mode
IDDOP(6)
mA
• FmCF=4MHz ceramic oscillator mode
μA
• FmCF=12MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz
• Internal RC oscillation stopped
• PLL oscillation mode
• 1/1 frequency division mode
IDDOP(11)
mA
• FmCF=10MHz ceramic oscillation mode
• FmX'tal=32.768kHz crystal oscillation mode
4.5 to 5.5
10.3
17.0
3.0 to 4.5
5.9
13.0
• System clock set to 10MHz
IDDOP(12)
• Internal RC oscillation stopped
• PLL oscillation mode
• 1/1 frequency division mode
Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal
pull-up resistors.
Continued on next page.
No.A1951-23/31
LC88F58B0A
Continued from preceding page.
Parameter
Symbol
HALT mode
IDDHALT(1)
Specification
Applicable
Conditions
Pin/Remarks
VDD[V]
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FmX'tal=32.768kHz crystal oscillation mode
typ
max
unit
• FmCF=12MHz ceramic mode
• System clock set to 12MHz
(Note 7-1)
min
4.5 to 5.5
2.9
4.4
4.5 to 5.5
2.5
4.2
3.0 to 4.5
1.3
3.0
• Internal RC oscillation stopped
• 1/1 frequency division mode
• HALT mode
IDDHALT(2)
• FmCF=10MHz ceramic oscillator mode
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 10MHz
IDDHALT(3)
• Internal RC oscillation stopped
• 1/1 frequency division mode
mA
• HALT mode
IDDHALT(4)
• FmCF=4MHz ceramic oscillator mode
4.5 to 5.5
0.90
1.6
2.2 to 4.5
0.40
1.1
4.5 to 5.5
0.42
1.25
2.2 to 4.5
0.20
0.85
4.5 to 5.5
23
90
• FmX'tal=32.768kHz crystal oscillator mode
• System clock set to 4MHz
IDDHALT(5)
• Internal RC oscillation stopped
• 1/2 frequency division mode
• HALT mode
IDDHALT(6)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
IDDHALT(7)
• System clock set to internal RC oscillation
• 1/1 frequency division mode
• HALT mode
IDDHALT(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz crystal oscillator mode
μA
• System clock set to 32.768kHz
IDDHALT(9)
• Internal RC oscillation stopped
2.2 to 4.5
10
40
4.5 to 5.5
0.05
20
2.2 to 4.5
0.03
15
4.5 to 5.5
15
58
2.2 to 4.5
4
35
• 1/1 frequency division mode
HOLD mode
consumption
current
HOLDX
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
current
HOLD mode
• CF1=VDD or open (external clock mode)
HOLDX mode
• CF1=VDD or open (external clock mode)
mode
consumption
VDD1
IDDHOLD(4)
• FmX'tal=32.768kHz crystal oscillator mode
μA
Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal
pull-up resistors.
No.A1951-24/31
LC88F58B0A
F-ROM Programming Characteristics at Ta = +10 to +55°C, VSS1=VSS2=VSS3=0V
Parameter
Onboard
Symbol
IDDFW(1)
Specification
Applicable
Conditions
Pin/Remarks
VDD1
programming
VDD[V]
min
typ
max
unit
• Microcontroller erase current current is
excluded.
3.0 to 5.5
5
10
mA
current
Onboard
tFW(1)
• 128-/1K-byte erase operation
3.0 to 5.5
20
30
ms
tFW(2)
• 2-byte programming operation
3.0 to 5.5
40
60
μs
programming
time
Power Pin Treatment Conditions 1 (VDD1, VSS1)
Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins:
• Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires,
of the same length (L1=L1', L2=L2') wherever possible.
• Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1μF or larger.
• The VDD1 and VSS1 traces must be thicker than the other traces.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
Power Pin Treatment Conditions 2 (VDD(2, 3), VSS(2, 3))
Connect capacitors that meet the following condition between the VDD (2, 3) and VSS (2, 3) pins:
• Connect among the VDD (2, 3) and VSS (2, 3) pins and the capacitor C3 with the shortest possible lead wires,
of the same length (L3=L3') wherever possible.
• The capacitance of C3 should be approximately 0.1μF or larger.
• The VDD (2, 3) and VSS (2, 3) traces must be thicker than the other traces.
L3
VSS (2, 3)
C3
VDD (2, 3)
L3’
No.A1951-25/31
LC88F58B0A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator
Nominal
Vendor
Frequency
Name
12MHz
Oscillation
Operating
Circuit Constant
Stabilization
Voltage
Resonator
C3
C4
Rf
Rd2
[pF]
[pF]
[Ω]
[Ω]
CSTCE12M0G52-R0
(10)
(10)
OPEN
220
CSTCE10M0G52-R0
(10)
(10)
OPEN
CSTLS10M0G53-B0
(15)
(15)
CSTCE8M00G52-R0
(10)
CSTLS8M00G53-B0
Time
Range
Remarks
typ
max
[ms]
[ms]
2.4 to 5.5
0.02
0.2
470
2.4 to 5.5
0.02
0.2
OPEN
680
2.6 to 5.5
0.02
0.2
(10)
OPEN
470
2.3 to 5.5
0.02
0.2
(15)
(15)
OPEN
1k
2.5 to 5.5
0.02
0.2
CSTCR4M00G53-R0
(15)
(15)
OPEN
1.5k
2.2 to 5.5
0.02
0.2
CSTLS4M00G53-B0
(15)
(15)
OPEN
1.5k
2.3 to 5.5
0.02
0.2
[V]
10MHz
MURATA
8MHz
4MHz
C1, C2
integrated type
C1, C2
integrated type
C1, C2
integrated type
C1, C2
integrated type
C1, C2
integrated type
C1, C2
integrated type
C1, C2
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the lower limit level of the operating voltage range (see Figure 4)
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator
Nominal
Vendor
Frequency
Name
32.768kHz
EPSON
TOYOCOM
Circuit Constant
Oscillator Name
MC-306
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
10
10
OPEN
0
2.2 to 5.5
0.4
2.0
Remarks
Applicable
CL value=7.0pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation
to get stabilized after the HOLD mode is released (see Figure 4).
Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the
oscillation characteristics are affected by their trace pattern.
No.A1951-26/31
LC88F58B0A
CF1
CF2
Rf1
C1
XT1
Rf2
Rd1
C2
XT2
Rd2
C3
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1951-27/31
LC88F58B0A
VDD
Operating VDD
lower limit
0V
Power
Reset time
RESB
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX'tal
XT1, XT2
Operating
mode
Reset
Unpredictable
Initialization instruction
execution
User instruction execution
Reset Time and Oscillation Stabilization Time
HOLD
release
No HOLD release signal
HOLD release signal valid
Interrupt operation
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX'tal
XT1, XT2
State
HOLD
HALT
Instruction execution
HOLD Release and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time Timing Charts
No.A1951-28/31
LC88F58B0A
VDD
Note:
Reset signal must be present when power
supply rises.
Determine the value of CRES and RRES so
that the reset signal is present for 10μs after the
supply voltage gets stabilized.
RRES
RES
CRES
Figure 5 Reset Circuit
tSCKHBSY
tSCKHBSY
RUN:
SIOCLK:
DATAIN:
DI0
DI1
DI6
DI7
DI8
DIx
DATAOUT:
DO0
DO1
DO6
DO7
DO8
DOx
Data transfer period
(SIO0 and SIO1 only)
tSCK
SIOCLK:
tSCKL
tSCKH
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data transfer period
(SIO0 and SIO1 only)
SIOCLK:
tSCKL
tSCKHA
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
* Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1951-29/31
LC88F58B0A
P
S
Sr
P
SDA
tBUF
tHD;STA tR
tF
tHD;STA
tsp
SCK
tLOW
tHD;DAT tHIGH
tSU;DAT
tSU;STA
tSU;STO
S: Start condition
P: Stop condition
Sr: Restart condition
Figure 8 I2C Timing
1kΩ
PC2/FILT
+
2.2μF
-
Cfs
VSS1
Cfs=OPEN
Figure 9 Recommended FILT Circuit
* Take at least 50ms to oscillation to stabilize after PLL is started.
No.A1951-30/31
LC88F58B0A
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PS No.A1951-31/31