Ordering number : ENA1860 LC88F5LA4ACS CMOS IC FROM 96K byte, RAM 6K byte on-chip http://onsemi.com 16-bit 1-chip Microcontroller Overview The LC88F5LA4ACS is a 16-bit microcomputer that, centered around an Xstromy16 CPU, integrates on a single chip a number of hardware features such as 96K-byte flash ROM (onboard programmable), 6K-byte RAM, six 16-bit timers, a base timer serving as a time-of-day clock, a real time clock, two synchronous SIO interfaces with automatic transmission capability, a single master I2C/synchronous SIO interface, a slave I2C/synchronous SIO interface, two asynchronous SIO (UART) interfaces, a 4-channel 12-bit resolution AD converter, a watchdog timer, a system clock frequency divider, a 38-source (24 modules) 13-vector interrupt feature, and on-chip debugger feature. Features Xstromy16 CPU • 4G-byte address space • General-purpose registers: 16 bits × 16registers Flash ROM • Capable of onboard programming with a wide range of voltage levels (2.6 to 3.6V). • Block-erasable in 128 or 1K byte units. • Data written in 2-byte units. • 98304 × 8 bits RAM • 6144 × 8 bits * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 May, 2013 Ver.1.00 30211HKIM 20100223-S00001 No.A1860-1/33 LC88F5LA4ACS Minimum instruction cycle time (tCYC) • 100ns (10MHz) VDD = 2.6 to 3.6V • 250ns (4MHz) VDD = 2.2 to 3.6V Ports ● Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units ● Oscillation/normal withstand voltage I/O ports ● Oscillation pins ● Reset pins ● TEST pins ● Power pins : 33 (P0n P1n, P20 to P25, P3n, P60 to P62) : 2 (PC0, PC1) : 2 (CF1, CF2) : 1 (RESB) : 1 (TEST) : 7 (VSS1 to 2, VSSA, VDD1 to 3, VDDA) Timers • Timer 0: 16-bit timer that supports PWM/toggle outputs 1) 5-bit prescaler 2) 8-bit PWM × 2, 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 1: 16-bit timer with capture registers 1) 5-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and internal RC oscillator • Timer 2: 16-bit timer with capture registers 1) 4-bit prescaler 2) May be divided into 2 channels of 8-bit timer 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 3: 16-bit timer that supports PWM/toggle outputs 1) 8-bit prescaler 2) 8-bit timer × 2ch or 8-bit timer + 8-bit PWM mode selectable 3) Clock source selectable from system clock, OSC0, OSC1, and external events • Timer 4: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 • Timer 5: 16-bit timer that supports toggle outputs 1) Clock source selectable from system clock and prescaler 0 * Prescaler 0 and 1 are consisted of 4 bits and can choose their clock source from OSC0 or OSC1. • Base timer 1) Clock may be selected from OSC0 (32.768kHz crystal oscillator) and frequency-divided output of system clock. 2) Interrupts can be generated in 7 timing schemes. Real time clock 1) Calender with Jan. 1, 2000 to Dec.31, 2799 including automatic leap year calculation function. 2) Consisted of Independent second- minute-hour-day-month-year-century counters. 3) Programmable count-clock calibration function. No.A1860-2/33 LC88F5LA4ACS Serial interfaces • SIO0: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SIO1: 8-bit synchronous SIO 1) LSB first/MSB first mode selectable 2) Supports data communication with a data length of 8 bits or less (1 to 8 bits specifiable) 3) Built-in 8-bit baudrate generator (4 tCYC to 512 tCYC transfer clocks) 4) Continuous/automatic data transmission (9- to 32768-bit units specifiable) 5) Interval function (intervals specifiable in 0 to 64 tSCK units) 6) Wakeup function • SMIIC0: Single master I2C/8-bit synchronous SIO Mode 0: Single-master mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) • SLIIC0: Slave I2C/8-bit synchronous SIO Mode 0: I2C slave mode communication Mode 1: Synchronous 8-bit serial I/O (MSB first) Note: usable only with the external clock source • UART0 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 4/8 cycle 6) Baudrate source clock : P07 input signal used as a 1 cycle signal (T0PWMH can be used as a clock source) or Timer 4 cycle. 7) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. • UART2 1) Data length : 8 bits (LSB first) 2) Start bits : 1 bit 3) Stop bits : 1/2 bit 4) Parity bits : None/even parity/odd parity 5) Transfer rate : 8 to 4096 cycle 6) Baudrate source clock : System clock/OSC0/OSC1/P25 input signal 7) Wakeup function 8) Full duplex communication Note: The “cycle” refers to one period of the baudrate clock source. No.A1860-3/33 LC88F5LA4ACS AD converter 1) 12/8 bits resolution selectable 2) Analog input: 14 channels 3) Comparator mode Watchdog timer 1) Driven by the base timer + internal watchdog timer dedicated counter 2) Interrupt or reset mode selectable Interrupts (peripheral function) • 38 sources (24 modules), 13 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Module 1 08000H Watchdog timer (1) 2 08004H Base timer (2) 3 08008H Timer 0 (2) 4 0800CH INT0 (1) 5 08014H INT1 (1) 6 08018H INT2 (1)/timer 1 (2)/UART2 (4) 7 0801CH INT3 (1)/timer 2 (4)/SMIIC0 (1)/SLIIC1 (1) 8 08020H INT4 (1)/timer 3 (2) 9 08024H INT5 (1)/timer 4 (1)/SIO1 (2) 10 08030H ADC (1)/timer 5 (1) 11 08034H INT6 (1) 12 08038H INT7 (1)/SIO0 (2)/SIO0(2) 13 0803CH Port 0 (3)/RTC (1) • 3 priority levels selectable. • Of interrupts of the same level, the one with the smallest vector address takes precedence. • A number enclosed in parentheses denotes the number of sources. Subroutine Stack: 6K-byte RAM area • Subroutine calls that automatically save PSW, interrupt vector calls: 6 bytes • Subroutine calls that do not automatically save PSW: 4 bytes Multiplication/division instructions • 16 bits × 16 bits (18 tCYC execution time) • 16 bits ÷ 16 bits (18 to 19 tCYC execution time) • 32 bits ÷ 16 bits (18 to 19 tCYC execution time) Oscillator circuits • RC oscillator circuit (internal): For system clock • CF oscillator circuit (built-in Rf circuit): For system clock (OSC1) • VMRC oscillator circuit: For system clock (OSC1) • Crystal oscillator circuit (built-in Rf circuit): For low-speed system clock (OSC0) • SLRC oscillator circuit (internal): For system clock (In the case of exception processing) System clock divider function • Can run on low current. • 1/1 to 1/128 of the system clock frequency can be set. No.A1860-4/33 LC88F5LA4ACS Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Released by a system reset or occurrence of an interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) OSC1, RC and OSC0 oscillators automatically stop. 2) There are the six ways of releasing the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt established at SIO0 or SIO1 (5) Having an interrupt established at UART2 • HOLDX mode: Suspends instruction execution and the operation of the peripheral circuits except those which run on OSC0. 1) OSC1 and RC oscillations automatically stop. 2) OSC0 maintains the state that is established when the HOLDX mode is entered. 3) There are seven ways of releasing the HOLDX mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5, INT6, and INT7 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established at the base timer circuit (5) Having an interrupt established at SIO0 or SIO1 (6) Having an interrupt established at UART2 . On-chip debugger function • Supports software debugging with the IC mounted on the target board. • Supports source line debugging and tracing functions, and breakpoint setting and real time display. • Single-wire communication Power supply voltage • VDD1, 2 : 2.2 to 3.6V. • VDD3 : (I/O) 1.6 to 3.6V. * Voltage of VDD3 must be lower than VDD1. Package Form • WLP46 (3.03 × 3.03): Lead-free and halogen-free type Development Tools • On-chip debugger: EOCUIF1 + LC88F5LA4A No.A1860-5/33 LC88F5LA4ACS Package Dimensions unit : mm (typ) 3404 BOTTOM VIEW SIDE VIEW 0.315 TOP VIEW 0.315 1 2 3 4 5 6 7 0.4 0.4 3.03 3.03 0.68 MAX G F E D C B A 0.2 SIDE VIEW 0.26 SANYO : WLP46(3.03X3.03) Pin Assignment Top view Bottom view 7 6 5 LC88F5LA4ACS 4 3 2 1 G F E D C B A WLP46 (3.03×3.03) (Lead-free and halogen-free type) No.A1860-6/33 LC88F5LA4ACS No. Name No. Name P04/P04INT No. F7 Name G1 TEST B4 P12/SCK0 E2 RESB D3 P05/P05INT F6 P13/U0TX F1 VSSA A5 P06/T0PWML G7 P14/T3OL/U0RX/INT2 E1 VSS1 B5 P07/T0PWMH/U0BRG E5 P15/T3OH/INT3 D2 PC0/XT1 A6 P37/T4O G6 P16/U2RX D1 PC1/XT2 C5 P36/SCK1 F5 P17/U2TX C1 VDD1 A7 P35/SI1/SB1 G5 P62 C2 VDDA B6 P34/SO1 F4 VDD3 B1 CF1 B7 P33/SM0DA G4 P20/INT4 A1 CF2 C6 P32/SM0CK E3 P21/INT5 B2 P00/P0INT/AN0 C7 P31/INT1/SM0DO G3 P22/SL0CK A2 P01/P0INT/AN1 D6 VDD2 F3 P23/SL0DA B3 P60/AN2 D7 VSS2 G2 P24/SL0DO/INT6 A3 P61/AN3 D5 P30/INT0 F2 P25/INT7/T5O C3 P02/P0INT E7 P10/SO0 A4 P03/P0INT E6 P11/SI0/SB0 No.A1860-7/33 LC88F5LA4ACS System Block Diagram CF RC X’tal Clock generator VMRC Low speed RC Base timer Watchdog timer FLASH ROM Xstromy16 CPU Timer 0 RAM Timer 1 On-chip debugger Timer 2 Port 0 Timer 3 Port 1 Timer 4 Port 2 Timer 5 Port 3 UART0 Port 6 UART2 Port C SIO0 INT0 to INT7 SIO1 AD SMIIC0 RTC SLIIC0 No.A1860-8/33 LC88F5LA4ACS Pin Description Pin Name I/O Description VSS1, VSS2 - - Power supply VSSA - - Power supply for AD VDD1, VDD2 - + Power supply VDD3 - + Power supply for port2’s I/O VDDA - + Power supply for AD Port 0 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P00 to P07 • Pull-up resistors can be turned on and off in 1 bit units • HOLD release input (P00 to P03, P04, P05) • Port 0 interrupt input (P00 to P03, P04, P05) • Pin functions AN0 (P00) to AN1 (P01): AD converter input port P06: Timer 0L output P07: Timer 0L output/UART0 clock input Port 1 I/O • 8-bit I/O port • I/O specifiable in 1-bit units P10 to P17 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P10: SIO0 data output P11: SIO0 data input/pulse input/output P12: SIO0 clock input/output P13: UART0 transmit P14: Timer 3L output/UART0 receive/ INT2 input/HOLD release/timer 2 event input/timer 2L capture input P15: Timer 3H output/ INT3 input/HOLD release/timer 2 event input/timer 2H capture input P16: UART2 receive P17: UART2 transmit Interrupt acknowledge type INT2, INT3: H level, L level, H edge, L edge, both edges Port 2 I/O • 6-bit I/O port • I/O specifiable in 1-bit units P20 to P25 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P20: INT4 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P21: INT5 input/HOLD release input/timer 3 event input/timer 2L capture input/timer 2H capture input P22: SLIIC0 clock input/output P23: SLIIC0 bus input/output/data input P24: SLIIC0 data output (used in 3-wire SIO mode)/ INT6 input/HOLD release input P25: Timer 5 output/ INT7 input/HOLD release input Interrupt acknowledge type INT4, INT5, INT6, INT7: H level, L level, H edge, L edge, both edges Port 3 P30 to P37 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1 bit units • Pin functions P30: INT0 input/HOLD release/timer 2L capture input P31: INT1 input/HOLD release/timer 2H capture input/SMIIC0 data output (used in 3-wire SIO mode) P32: SMIIC0 clock input/output P33: SMIIC0 bus input/output/data input P34: SIO1 data output P35: SIO1 data input/bus input/output P36: SIO1 clock input/output P37: Timer 4 output Interrupt acknowledge type INT0, INT1: H level, L level, H edge, L edge, both edges Continued on next page. No.A1860-9/33 LC88F5LA4ACS Continued from preceding page. Pin Name Port 6 I/O Description • 3-bit I/O port I/O • I/O specifiable in 1-bit units P60 to P62 • Pull-up resistors can be turned on and off in 1 bit units • Pin functions AN2 (P60) to AN3 (P61): AD converter input port Port C • 2-bit I/O port I/O • I/O specifiable in 1-bit units PC0 to PC1 • Pin functions PC0: 32.768kHz crystal oscillator input (XT1) PC1: 32.768kHz crystal oscillator output (XT2) TEST • TEST pin I/O • Used to communicate with on-chip debugger. • Connects an external 100kΩ pull-down resistor. RESB I Reset pin CF1 I Ceramic resonator input pin CF2 O Ceramic resonator output pin Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Output Type Units of 1 bit Pull-up Resistor CMOS Programmable P60 to P62 P10 to P17 Able to program special functions’ output type from CMOS P20 to P25 output or Nch-opendrain P30 to P37 PC0 - N-channel open drain (32.768kHz crystal oscillator input) None PC1 - Nch-open drain (32.768kHz crystal oscillator output) None * Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. * Power supply must be VDD1 ≤ VDD3. * Be sure to electrically short the VSS1, VSS2 and VSSA pins. Example 1: When data is being backed up in the HOLD mode, the H level signals to the output ports are fed by the backup capacitors. LSI VDD1 Power supply For Backup VDDA VDD2 Power supply VDD3 VSS1 VSS2 VSSA No.A1860-10/33 LC88F5LA4ACS Example 2: When data is being backed up in the HOLD mode, the H level output at any ports is not sustained and is unpredictable. LSI VDD1 Power supply For backup VDDA VDD2 Power supply VDD3 VSS1 VSS2 VSSA Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSSA = 0V Parameter Maximum supply Symbol Applicable Pin /Remarks Specification Conditions VDD[V] VDD max VDD1, VDD2, VDDA VDD1=VDD2=VDDA VDD3 max VDD3 VDD3≤VDD Input voltage VI(1) CF1, RESB Input/output VIO(1) Ports 0, 1, 3 voltage voltage Port 6 min typ -0.3 +4.0 -0.3 +4.0 -0.3 VDD +0.3 -0.3 VDD +0.3 -0.3 VDD3 +0.3 PC0, PC1 VIO(2) Peak output IOPH (1) current IOPH (2) Ports 2 VDD3≤VDD P04 to P07, P62 CMOS output selected Ports 1, 2, 3 Per applicable pin P00 to P03 Per applicable pin P60 to P61 High level output current Average IOMH (1) output current IOMH (2) (Note 1-1) Total output P04 to P07, P62 CMOS output selected Ports 1, 2, 3 Per applicable pin P00 to P03 Per applicable pin P60 to P61 ΣIOAH (1) current ΣIOAH (2) ΣIOAH (3) ΣIOAH (4) ΣIOAH (5) P60 to P61 Total of currents at P00 to P03 applicable pins P04 to P07 Total of currents at P31 to p37 applicable pins Port 1 Total of currents at P30, P62 applicable pins P04 to P07, P62 Total of currents at Ports 1, 3 applicable pins Port 2 Total of currents at applicable pins max unit V -7.5 -4.5 -5 -2.5 mA -10 -15 -15 -30 -15 Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page. No.A1860-11/33 LC88F5LA4ACS Continued from preceding page. Parameter Peak output Symbol IOPL(1) current Applicable Pin /Remarks P04 to P07, P62 Specification Conditions VDD[V] min typ Per applicable pin P00 to P03 unit 12.5 Ports 1, 2, 3 IOPL(2) max Per applicable pin P60 to P61 7.5 PC0 to PC1 Average IOML(1) output current Low level output current (Note 1-1) P04 to P07, P62 Per applicable pin 10 Port 1, 2, 3 IOML(2) P00 to P03 Per applicable pin P60 to P61 5 PC0 to PC1 Total output ΣIOAL(1) PC0 to PC1 current Total of currents at 10 applicable pins ΣIOAL(2) ΣIOAL(3) P60 to P61 Total of currents at P00 to P03 applicable pins P00 to P03 Total of currents at P60 to P61 applicable pins mA 10 15 PC0 to PC1 ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) Allowable power Pd max dissipation P04 to P07 Total of currents at P31 to P37 applicable pins Ports 1, 2 Total of currents at P30, P62 applicable pins P04 to P07, P62 Total of currents at Ports 1, 2, 3 applicable pins WLP46 (3.03×3.03) 30 60 80 Ta=-40 to +85°C With thermal resistance T.B.D mW board (Note 1-2) Operating ambient Topr temperature Storage ambient temperature Tstg -40 +85 -55 +125 °C Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Note 1-2: Thermal resistance board is used. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A1860-12/33 LC88F5LA4ACS Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Operating Applicable Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDDA Specification Conditions VDD[V] min typ max unit 0.098μs≤tCYC≤66μs 2.6 3.6 0.245μs≤tCYC≤66μs 2.2 3.6 1.8 3.6 2.2 to 3.6 0.7VDD VDD 2.2 to 3.6 0.75VDD VDD 2.2 to 3.6 0.7VDD VDD 2.2 to 3.6 0.7VDD3 VDD3 2.2 to 3.6 VSS 0.25VDD 2.2 to 3.6 VSS 0.25VDD supply voltage (Note 2-1) Memory VHD VDD1=VDD2=VDDA sustaining RAM and register contents sustained in HOLD mode supply voltage High level input VIH(1) Ports 0, 1, 3, 6 voltage VIH(2) CF1, RESB PC0, PC1 VIH(3) 2 P32, P33 I C side VIH(4) Port 2 Low level input VIL(1) Ports 0, 1, 3, 6 voltage VIL(2) CF1, RESB VDD3= 1.6V to 3.6V PC0, PC1 Instruction VIL(3) P32, P33 I2C side VIL(4) Port 2 VDD3= 1.6V to 3.6V tCYC 2.2 to 3.6 VSS 0.3VDD 2.2 to 3.6 VSS 0.3VDD3 2.6 to 3.6 0.098 66 2.2 to 3.6 0.245 66 2.6 to 3.6 0.1 10 2.2 to 3.6 0.1 4 2.6 to 3.6 0.2 20 2.2 to 3.6 0.2 8 V μs cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio = 1/1 • External system clock DUTY50±5% • CF2 pin open • System clock frequency division ratio = 1/2 MHz Note 2-1: VDD≥2.6V must be maintained when making onboard programming into flash ROM. Note 2-2: Relationship between tCYC and oscillation frequency is 1/FmCF when frequency division ratio is 1/1 and 2/FmCF when the ratio is 1/2. Continued on next page. No.A1860-13/33 LC88F5LA4ACS Continued from preceding page Parameter Oscillation Symbol FmCF(1) CF1, CF2 frequency range Specification Applicable Conditions Pin /Remarks VDD[V] 10MHz ceramic oscillator mode See Fig. 1. FmCF(2) CF1, CF2 (Note 2-3) 4MHz ceramic oscillator mode See Fig. 1. FmMRC(1) min typ max 2.2 to 3.6 10 2.2 to 3.6 4 unit Multivaliable RC oscillation When SEL4M=0 center range 2.6 to 3.6 7.5 10 12.5 2.2 to 3.6 2 4 6 MHz setting (Note 2-4) FmMRC(2) Multivaliable RC oscillation When SEL4M=1 center range setting (Note 2-4) FmRC Internal RC oscillation 2.2 to 3.6 0.5 1.0 2.0 FmSLRC Internal low-speed RC oscillation 2.2 to 3.6 18 30 45 FsX'tal XT1, XT2 32.768kHz crystal oscillator mode See Fig. 2. kHz 2.2 to 3.6 32.768 Note 2-3: See Tables 1 and 2 for oscillator constant values. Note 2-4: To change to a multivaliable RC oscillation as a system clock, wait more than 20μs oscllation stabilizing time after multivaliable RC oscillation is disabled to enabled. No.A1860-14/33 LC88F5LA4ACS Electrical Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter High level input Symbol IIH(1) current Specification Applicable/ Conditions Remarks VDD[V] Ports 0, 1, 3, 6 Output disabled PC0, PC1 Pull-up resistor off RESB VIN=VDD (including output Tr. off leakage min typ max 2.2 to 3.6 1 2.2 to 3.6 15 2.2 to 3.6 1 unit current) IIH(2) CF1 VIN=VDD IIH(3) Port 2 Output disabled Pull-up resistor off VIN=VDD3 VDD3= 1.6V to 3.6V (including output Tr. off leakage current) Low level input IIL(1) Ports 0, 1, 3, 6 Output disabled PC0, PC1 Pull-up resistor off RESB VIN=VSS (including output Tr. off leakage IIL(2) CF1 VIN=VSS IIL(3) Port 2 Output disabled current μA 2.2 to 3.6 -1 2.2 to 3.6 -15 2.2 to 3.6 -1 IOH=-0.6mA 2.6 to 3.6 VDD-0.4 IOH=-0.4mA 2.2 to 3.6 VDD-0.4 2.6 to 3.6 VDD3-0.4 3.0 to 5.5 VDD3-0.4 2.2 to 5.5 VDD3-0.4 current) Pull-up resistor off VIN=VSS3 VDD3= 1.6V to 3.6V (including output Tr. off leakage current) High level output VOH(1) voltage VOH(2) VOH(3) Ports 0, 1, 3, 6 Port 2 IOH=-0.6mA VDD3= 2.6V to 3.6V VOH(4) IOH=-0.4mA VDD3= 2.6V to 3.6V Low level output VOH(5) IOH=-0.2mA VOL(1) VDD3= 1.6V to 3.6V IOL=3.0mA 2.6 to 3.6 0.4 IOL=1.3mA 2.2 to 3.6 0.4 2.2 to 3.6 0.4 2.6 to 3.6 0.4 2.2 to 3.6 0.4 2.2 to 3.6 0.4 2.6 to 3.6 0.32 voltage Ports 0, 1, 6 P30 to P31, VOL(2) P34 to P37 VOL(3) P32, P33 IOL=3.0mA VOL(4) P20 to P21, IOL=3.0mA P24 to P25 VDD3=1.6V to 3.6V VOL(5) IOL=1.3mA VDD3=1.6V to 3.6V VOL(6) P22, P23 VOL(7) IOL=3.0mA VDD3=1.6V to 3.6V IOL=3.0mA VDD3=1.6V to 3.6V Pull-up resistor Rpu(1) Ports 0, 1, 3, 6 VOH=0.9VDD 2.2 to 3.6 18 55 150 Rpu(2) Port 2 VOH=0.9VDD VDD3=2.2V to 3.6V 2.2 to 3.6 18 55 150 2.2 to 3.6 30 80 200 Rpu(3) VOH=0.9VDD VDD3=1.6V to 2.2V Hysteresis VHYS(1) RESB voltage VHYS(2) Port 2 VDD3= 1.6V to 3.6V PnFSA=1 or other function is in 2.2 to 3.6 0.1VDD 2.2 to 3.6 0.1VDD3 2.2 to 3.6 0.1VDD 2.2 to 3.6 10 input state VHYS(3) Ports 0, 1, 3 PnFSA=1 or other function is in input state Pin capacitance CP All pins V kΩ V Pins other than that under test VIN=VSS, f=1MHz, Ta=25°C pF No.A1860-15/33 LC88F5LA4ACS Serial I/O Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Serial I/O Characteristics (Wakeup Function Disabled) (Note 4-1-1) Parameter Symbol Period tSCK(1) Low level tSCKL(1) Specification Applicable Conditions Pin/Remarks SCK0 (P12) VDD[V] • See Fig. 6. tSCKHA(1) Input clock tSCKH(1) pulse width typ max unit 4 2 pulse width High level min 2 • Automatic communication mode • See Fig. 6. 6 2.2 to 3.6 tCYC • Automatic communication tSCKHBSY(1a) mode 23 • See Fig. 6. • Mode other than automatic tSCKHBSY(1b) communication mode 4 Serial clock • See Fig. 6. Period tSCK(2) SCK0 (P12) • CMOS output selected 4 • See Fig. 6. Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 1/2 pulse width • Automatic communication Output clock tSCKHA(2) mode • CMOS output selected 2.2 to 3.6 6 • See Fig. 6. • Automatic communication tSCKHBSY(2a) mode 4 • CMOS output selected 23 tCYC • See Fig. 6. • Mode other than automatic tSCKHBSY(2b) communication mode 4 Data setup time tsDI(1) SI0 (P11), SB0 (P11) thDI(1) Output tdD0(1) Input clock Data hold time Output clock Serial output Serial input • See Fig. 6. delay time • Specified with respect to rising 0.03 edge of SIOCLK • See Fig. 6. 2.2 to 3.6 0.03 SO0 (P10), • (Note 4-1-2) SB0 (P11) 1tCYC +0.05 tdDO(2) • (Note 4-1-2) μs 2.2 to 3.6 1tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. No.A1860-16/33 LC88F5LA4ACS SIO0 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-2-1) Input clock Serial clock Parameter Period tSCK(3) Low level tSCKL(3) SCK0 (P12) Specification Conditions VDD[V] • See Fig. 6. High level tSCKH(3) pulse width tSCKHBSY(3) Data hold time min typ max tsDI(2) unit 2 1 2.2 to 3.6 tCYC 1 2 SI0 (P11), SB0 (P11) • Specified with respect to thDI(2) 0.03 rising edge of SIOCLK • See Fig. 6. 2.2 to 3.6 0.03 Output Input clock Serial input Applicable Pin/Remarks pulse width Data setup time Serial output Symbol delay time tdD0(3) SO0 (P10), μs • (Note 4-2-2) SB0 (P11) 2.2 to 3.6 1tCYC +0.05 Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Note 4-2-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig.6. No.A1860-17/33 LC88F5LA4ACS SIO1 Serial Input/Output Characteristics (Wakeup Function Disabled) (Note 4-3-1) Parameter Symbol Period tSCK(4) Low level tSCKL(4) Specification Applicable Conditions Pin/Remarks SCK1 (P36) VDD[V] • See Fig. 6. tSCKHA(4) Input clock tSCKH(4) pulse width typ max unit 4 2 pulse width High level min 2 • Automatic communication mode • See Fig. 6. 6 2.2 to 3.6 tCYC • Automatic communication tSCKHBSY(4a) mode 23 • See Fig. 6. • Mode other than automatic tSCKHBSY(4b) communication mode 4 Serial clock • See Fig. 6. Period tSCK(5) SCK1 (P36) • CMOS output selected 4 • See Fig. 6. Low level tSCKL(5) 1/2 pulse width High level tSCK tSCKH(5) 1/2 pulse width • Automatic communication Output clock tSCKHA(5) mode • CMOS output selected 2.2 to 3.6 6 • See Fig. 6. • Automatic communication tSCKHBSY(5a) mode 4 • CMOS output selected 23 tCYC • See Fig. 6. • Mode other than automatic tSCKHBSY(5b) communication mode 4 • See Fig. 6. Serial input Data setup time SI1 (P35), SB1 (P25) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time thDI(3) 0.03 2.2 to 3.6 0.03 Input clock Output tdD0(4) delay time SO1 (P34), • (Note 4-3-2) SB1 (P35) 1tCYC μs +0.05 tdDO(5) Output clock Serial output tsDI(3) • (Note 4-3-2) 2.2 to 3.6 1tCYC +0.05 Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. No.A1860-18/33 LC88F5LA4ACS SIO1 Serial Input/Output Characteristics (Wakeup Function Enabled) (Note 4-4-1) Input clock Serial clock Parameter Period tSCK(6) Low level tSCKL(6) Specification Applicable Conditions Pin/Remarks SCK1 (P36) VDD[V] min • See Fig. 6. typ 1 High level tSCKH(6) 1 pulse width tSCKHBSY(6) 2 tsDI(4) SI1 (P35), SB1 (P35) unit tCYC • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time max 2 2.2 to 3.6 pulse width Data setup time Serial input Symbol thDI(4) 0.03 2.2 to 3.6 0.03 Input clock Serial output μs Output tdD0(6) delay time SO1 (P34), • (Note 4-4-2) SB1 (P35) 1tCYC 2.2 to 3.6 +0.05 Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: Specified with respect to the falling edge of SIOCLK. Specified as the interval up to the time an output change begins in the open drain output mode. See Fig. 6. SMIIC0 Simple SIO Mode Input/Output Characteristics Input clock Symbol Period tSCK(7) Low level tSCKL(7) Specification Applicable Conditions Pin/Remarks SM0CK (P32) VDD[V] See Fig. 6. 2.2 to 3.6 pulse width High level Period SM0CK (P32) • CMOS output selected tSCKL(8) 4 1/2 tSCK tSCKH(8) 1/2 pulse width Serial input Data setup time SM0DA (P33) • Specified with respect to rising edge of SIOCLK • See Fig. 6. Data hold time thDI(5) 0.03 2.2 to 3.6 0.03 Output delay Serial output tsDI(5) unit 2 2.2 to 3.6 pulse width High level max 2 • See Fig. 6. Low level typ tCYC tSCKH(7) tSCK(8) min 4 pulse width Output clock Serial clock Parameter time tdD0(7) SM0DO (P34), SM0DA (P33) μs • Specified with respect to falling edge of SIOCLK • Specified as interval up to time when output state starts 2.2 to 3.6 1tCYC +0.05 changing. • See Fig. 6. Note 4-5-1: These specifications are theoretical values. Add margin depending on its use. No.A1860-19/33 LC88F5LA4ACS SMIIC0 I2C Mode Input/Output Characteristics Clock Input clock Parameter Symbol Period tSCL Low level tSCLL Specification Applicable Conditions Pin/Remarks SM0CK (P32) VDD[V] • See Fig. 8. High level Output clock SM0CK (P32) • Specified as interval up to time tSCLLx 2.2 to 3.6 pulse width High level 2.5 10 when output state starts changing. Low level 1/2 tSCL tSCLHx 1/2 pulse width SM0CK and SM0DA tsp pins input spike unit 2 pulse width tSCLx max Tfilt tSCLH Period typ 5 2.2 to 3.6 pulse width min SM0CK (P32) • See Fig. 8. SM0DA (P33) 2.2 to 3.6 1 Tfilt suppression time time between start and stop tBUF SM0CK (P32) • See Fig. 8. SM0DA (P33) Input Bus release 2.5 SM0CK (P32) • Standard clock mode SM0DA (P33) • Specified as interval up to time Output tBUFx Tfilt 2.2 to 3.6 5.5 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.6 when output state starts changing. Start/restart tHD;STA condition hold SM0DA (P33) • When SMIIC register control bit, SHDS=0 2.0 • See Fig. 8. Input time SM0CK (P32) Tfilt • When SMIIC register control bit, SHDS=1 • See Fig. 8. SM0CK (P32) • Standard clock mode SM0DA (P33) • Specified as interval up to time Output tHD;STAx 2.5 2.2 to 3.6 4.1 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.0 when output state starts changing. time tSU;STA SM0CK (P32) • See Fig. 8. SM0DA (P33) 1.0 tSU;STAx Output condition setup Input Restart SM0CK (P32) • Standard clock mode SM0DA (P33) • Specified as interval up to time 2.2 to 3.6 5.5 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time Tfilt 1.6 when output state starts changing. Continued on next page. No.A1860-20/33 LC88F5LA4ACS Continued from preceding page Parameter Symbol setup time tSU;STO Input Stop condition Specification Applicable Conditions Pin/Remarks SM0CK (P32) VDD[V] SM0DA (P33) typ max 1.0 SM0CK (P32) • Standard clock mode SM0DA (P33) • Specified as interval up to time Output tSU;STOx min unit • See Fig. 8. 2.2 to 3.6 Tfilt 4.9 when output state starts changing. μs • High-speed clock mode • Specified as interval up to time 1.6 when output state starts changing. tHD;DAT Input Data hold time Output Input • Specified as interval up to time 2.2 to 3.6 when output state starts changing. Output Tfilt 1 1.5 • See Fig. 8. 1 • Specified as interval up to time 2.2 to 3.6 when output state starts changing. Tfilt 1tSCL -1.5Tfilt tF SM0CK (P32) • See Fig. 8. SM0DA (P33) tF Output SM0CK (P32) SM0DA (P33) Input time SM0CK (P32) 0 SM0DA (P33) tSU;DATx SM0DA pins fall SM0CK (P32) SM0DA (P33) tSU;DAT SM0CK and • See Fig. 8. SM0DA (P33) tHD;DATx Data setup time SM0CK (P32) SM0CK (P32) SM0DA (P33) 2.2 to 3.6 • When SMIIC register control bits, 2.8 PSLW=1, PHV=1 300 20 +0.1Cb 250 ns • SM0CK, SM0DA port output FAST mode 2.6 to 3.6 100 • Cb≤100pF Note 4-6-1: These specifications are theoretical values. Add margin depending on its use. Note 4-6-2: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC×1 0 1 tCYC×2 1 0 tCYC×3 1 1 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt >140ns Note 4-6-3: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100pF Note 4-6-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 1 SCL frequency setting ≤ 100kHz The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows: 250ns ≥ Tfilt >140ns BRDQ (bit5) = 0 SCL frequency setting ≤ 400kHz No.A1860-21/33 LC88F5LA4ACS SLIIC0 Simple SIO Mode Input/Output Characteristics Input clock Serial clock Parameter Symbol Period tSCK(7) Low level tSCKL(7) Specification Applicable Conditions Pin/Remarks SL0CK (P22) VDD[V] See Fig. 8. High level tSCKH(7) Serial input tsDI(5) SL0DA (P23) unit tCYC 2 • Specified with respect to rising edge of SIOCLK • See Fig. 8. Data hold time max 2 pulse width Data setup time typ 4 2.2 to 3.6 pulse width min thDI(5) 0.03 2.2 to 3.6 0.03 Serial output μs Output delay time tdD0(7) SL0DO (P24), SL0DA (P23) • Specified with respect to falling edge of SIOCLK • Specified as interval up to time 2.2 to 3.6 when output state starts changing. 1tCYC +0.05 • See Fig. 8. Note 4-7-1: These specifications are theoretical values. Add margin depending on its use. Note 4-7-2: When not specified, VDD3=1.6V to 3.6V (VDD3≤VDD) No.A1860-22/33 LC88F5LA4ACS SLIIC1 I2C Mode Input/Output Characteristics Input clock Clock Parameter Symbol Period tSCL Low level tSCLL Specification Applicable Conditions Pin/Remarks SL0CK (P22) VDD[V] • See Fig. 8. High level tSCLH tsp pins input spike max unit Tfilt 2.5 2 pulse width SL0CK and SL0DA typ 5 2.2 to 3.6 pulse width min SL0CK (P22) • See Fig. 8. SL0DA (P23) 2.2 to 3.6 1 Tfilt suppression time time between start and stop tBUF Start/restart • See Fig. 8. 2.2 to 3.6 tHD;STA condition hold SL0CK (P22) SL0DA (P23) 2.5 Tfilt • When SLIIC register control bit, SHDS=0 • See Fig. 8. Input time SL0CK (P22) SL0DA (P23) Input Bus release • When SLIIC register control bit 2.0 2.2 to 3.6 SHDS=1 Tfilt 2.5 • See Fig. 8. condition setup time tSU;STA setup time tSU;STO tHD;DAT SL0CK (P22) SL0CK (P22) Output SL0DA (P23) Tfilt 2.2 to 3.6 1.0 Tfilt • See Fig. 8. • See Fig. 8. • Specified as interval up to time 2.2 to 3.6 Tfilt when output state starts changing. 1 tSU;DAT SL0CK (P22) 1.5 • See Fig. 8. Input SL0DA (P23) 1 tSU;DATx Output 1.0 0 tHD;DATx Data setup time SL0CK (P22) 2.2 to 3.6 SL0DA (P23) Input Data hold time • See Fig. 8. SL0DA (P23) Input Stop condition SL0CK (P22) SL0DA (P23) Input Restart SL0CK (P22) SL0DA (P23) • Specified as interval up to time when output state starts changing. 2.2 to 3.6 Tfilt 1tSCL -1.5Tfilt Continued on next page. No.A1860-23/33 LC88F5LA4ACS Continued from preceding page Parameter Symbol SM0DA pins fall time tF Input SM0CK and Specification Applicable Conditions Pin/Remarks SM0CK (P32) VDD[V] SM0DA (P33) tF SM0CK (P32) SM0DA (P33) 2.2 to 3.6 • When SLIIC0 register control bits PSLW=1, PHV=1 2.8 to 3.6 When VDD3=2.8V typ max unit PSLW=1, PHV=1 300 20 +0.1Cb 250 ns • When SLIIC0 register control bits Output min • See Fig. 8. 2.2 to 3.6 When VDD=1.8 20 +0.1Cb 250 • SL0CK, SL0DA port output FAST mode 2.6 to 3.6 100 • Cb≤100pF Note 4-8-1: The value of Tfilt is determined by the values of the register SLIC0PCNT, bits 5 and 4 (BRP1, BRP0) and the system clock frequency. BRP1 BRP0 Tfilt 0 0 tCYC×1 0 1 tCYC×2 1 0 tCYC×3 1 1 tCYC×4 Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range: 250ns ≥ Tfilt > 140ns Note 4-8-2: Cb represents the total loads (in pF) connected to the bus pins. Cb ≤ 100pF Note 4-8-3: When not specified, VDD3=1.6V to 3.6V (VDD3≤VDD) No.A1860-24/33 LC88F5LA4ACS UART0 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Transfer rate Symbol UBR0 Applicable Pin/Remarks Specification Conditions VDD[V] min typ max unit U0RX (P13), U0TX (P14), 2.2 to 3.6 4 8 tBGCYC U0BRG (P07) Note 4-9: tBGCYC denotes one cycle of the baudrate clock source. UART2 Operating Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Transfer rate Symbol UBR2 Applicable Pin/Remarks Specification Conditions VDD[V] U2RX (P16), min 2.2 to 3.6 U2TX (P17) typ max 8 4096 unit tBGCYC Note 4-10: tBGCYC denotes one cycle of the baudrate clock source. Pulse Input Conditions at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V Parameter Symbol Applicable Pin/Remarks Specification Conditions VDD[V] High/low level tPIH(1) INT0 (P30), • Interrupt source flag can be set. pulse width tPIL(1) INT1 (P31), • Event inputs for timers 2 and 3 INT2 (P14), min typ max unit are enabled. INT3 (P15), INT4 (P20), 2.2 to 3.6 2 tCYC 2.2 to 3.6 10 μs INT5 (P21), INT6 (P24), INT7 (P25) tPIL(2) RESB Resetting is enabled. Note 4-11: When not specified, VDD3=1.6V to 3.6V (VDD3≤VDD) No.A1860-25/33 LC88F5LA4ACS AD Converter Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSSA = 0V 12-bit AD Conversion Mode Parameter Applicable Pin Symbol /Remarks Resolution NAD AN0 (P00), Absolute accuracy ETAD AN1 (P01), Conversion time TCAD12 AN2 (P60), Specification Conditions VDD[V] typ 2.6 to 3.6 max unit 12 bit (Note 6-1) 2.6 to 3.6 Conversion time calculated 3.0 to 3.6 32 209 2.6 to 3.6 67 209 2.6 to 3.6 VSSA VDDA AN3 (P61) Analog input min VAIN voltage range Analog port IAINH VAIN=VDD 2.6 to 3.6 input current IAINL VAIN=VSS 2.6 to 3.6 ±16 1 -1 LSB μs V μA Conversion time calculation formula: TCAD12= ((52/(AD division ratio))+2) × tCYC 8-bit AD Conversion Mode Parameter Symbol Applicable Pin /Remarks Resolution NAD AN0 (P00), Absolute accuracy ETAD AN1 (P01), Conversion time TCAD8 AN2 (P60), Specification Conditions VDD[V] typ max unit 8 bit (Note 6-1) 2.6 to 3.6 Conversion time calculated 3.0 to 3.6 20 129 2.6 to 3.6 42 129 2.6 to 3.6 VSSA VDDA AN3 (P61) Analog input min 2.6 to 3.6 VAIN voltage range Analog port IAINH VAIN=VDD 2.6 to 3.6 input current IAINL VAIN=VSS 2.6 to 3.6 ±1.5 1 -1 LSB μs V μA Conversion time calculation formula: TCAD8= ((32/(AD division ratio))+2) × tCYC Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital value against the analog input value is loaded in the result register. The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion is executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion is executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A1860-26/33 LC88F5LA4ACS Consumption Current Characteristics at Ta=-40 to +85°C, VSS1=VSS2=VSSA=0V typ: 3.0V Parameter Normal mode Symbol IDDOP(1) consumption current (Note 7-1) Applicable Pin/Remarks Specification Conditions VDD[V] VDD1 =VDD2 • FmCF=10MHz ceramic oscillation mode =VDDA ≥VDD3 • FmX'tal=32.768kHz crystal oscillation mode min typ max unit • FmMRC=0MHz (oscillation stoped) • System clock set to 10MHz 2.6 to 3.6 3.89 7.2 2.6 to 3.6 3.72 6.6 • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(2) • FmCF=0Hz (oscillation stopped) • FmMRC=10MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(3) mA • FmCF=0Hz (oscillation stopped) • FmMRC=4MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 4MHz 2.2 to 3.6 2.28 3.2 2.2 to 3.6 0.62 1.8 2.2 to 3.6 24.4 65 • Internal RC oscillation stopped • 1/1 frequency division mode IDDOP(4) • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to internal RC oscillation • 1/1 frequency division mode IDDOP(5) • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to 32.768kHz μA • Internal RC oscillation stopped • 1/1 frequency division mode Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. Continued on next page. No.A1860-27/33 LC88F5LA4ACS Continued from preceding page. Parameter Symbol HALT mode IDDHALT(1) consumption current (Note 7-1) Specification Applicable Conditions Pin/Remarks VDD[V] VDD1 =VDD2 • HALT mode =VDDA ≥VDD3 • FmMRC=0MHz (oscillation stoped) min typ max unit • FmCF=10MHz ceramic oscillation mode • FmX'tal=32.768kHz crystal oscillation mode 2.6 to 3.6 1.18 2.0 2.6 to 3.6 1.05 1.8 • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode • HALT mode IDDHALT(2) • FmCF=0Hz (oscillation stopped) • FmMRC=10MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode • System clock set to 10MHz • Internal RC oscillation stopped • 1/1 frequency division mode mA • HALT mode IDDHALT(3) • FmCF=0Hz (oscillation stopped) • FmMRC=4MHz oscillator mode • FmX'tal=32.768kHz crystal oscillation mode 2.2 to 3.6 0.44 0.8 2.2 to 3.6 0.12 0.5 2.2 to 3.6 8.21 40 • System clock set to 4MHz • Internal RC oscillation stopped • 1/1 frequency division mode • HALT mode IDDHALT(4) • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to internal RC oscillation • 1/1 frequency division mode • HALT mode IDDHALT(5) • FmCF=0Hz (oscillation stopped) • FmMRC=0Hz (oscillation stopped) • FmX'tal=32.768kHz crystal oscillator mode • System clock set to 32.768kHz • Internal RC oscillation stopped • 1/1 frequency division mode HOLD mode IDDHOLD(1) VDD1 • CF1=VDD or open (external clock mode) consumption μA HOLD mode 2.2 to 3.6 0.02 20 2.2 to 3.6 5.2 35 current HOLDX IDDHOLD(2) HOLDX mode mode • CF1=VDD or open (external clock mode) consumption • FmX'tal=32.768kHz crystal oscillator mode current Note 7-1: The consumption current value includes none of the currents that flow into the output transistor and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1=VSS2=VSSA=0V Parameter Onboard Symbol IDDFW(1) Specification Applicable Conditions Pin/Remarks VDD1 VDD[V] typ max unit • Microcontroller erase current current is excluded. programming min 2.6 to 3.6 7 mA current Onboard tFW(1) • 128-/1K-byte erase operation 2.6 to 3.6 30 ms tFW(2) • 2-byte programming operation 2.6 to 3.6 60 μs programming time No.A1860-28/33 LC88F5LA4ACS Power Pin Treatment Conditions 1 (VDD1, VSS1) Connect capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1 pins and the capacitors C1 and C2 with the shortest possible lead wires, of the same length (L1=L1', L2=L2') wherever possible. • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF or larger. • The VDD1 and VSS1 traces must be thicker than the other traces. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ Power Pin Treatment Conditions 2 (VDD(2, 3), VSS(2)) Connect capacitors that meet the following condition between the VDD(2) and VSS(2), VDD(3) and VSS(2) pins: • Connect among the VDD(2, 3) and VSS(2) pins and the capacitor C3 with the shortest possible lead wires, of the same length (L3=L3') wherever possible. • The capacitance of C3 should be approximately 0.1μF or larger. • The VDD(2, 3) and VSS(2) traces must be thicker than the other traces. L3 VSS(2) C3 VDD(2, 3) L3’ Power Pin Treatment Conditions 3 (VDDA, VSSA) Connect capacitors that meet the following condition between the VDDA and VSSA pins: • Connect among the VDDA and VSSA pins and the capacitor C4 with the shortest possible lead wires, of the same length (L4=L4') wherever possible. • The capacitance of C4 should be approximately 0.1μF or larger. • The VDDA and VSSA traces must be thicker than the other traces. L4 VSSA C4 VDDA L4’ No.A1860-29/33 LC88F5LA4ACS Characteristics of a Sample OSC1 System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Resonator Nominal Vendor Frequency Name 10MHz 8MHz MURATA 4MHz Circuit Constant Resonator Operating Oscillation Voltage Stabilization Time C3 C4 Rf Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [ms] [ms] CSTCE10M0G52-R0 (10) (10) OPEN 0 2.2 to 3.6 0.02 0.2 CSTCE8M00G52-R0 (10) (10) OPEN 0 2.2 to 3.6 0.02 0.2 CSTCR4M00G53-R0 (15) (15) OPEN 680 2.2 to 3.6 0.02 0.2 Remarks C1, C2 integrated type C1, C2 integrated type C1, C2 integrated type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the lower limit level of the operating voltage range (see Figure 4) Characteristics of a Sample System Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Resonator Nominal Vendor Frequency Name 32.768kHz EPSON TOYOCOM Circuit Constant Oscillator Name Operating Oscillation Voltage Stabilization Time C3 C4 Rf2 Rd2 Range typ max [pF] [pF] [Ω] [Ω] [V] [s] [s] 18 18 OPEN 0 2.2 to 3.6 0.9 2 MC-306 Remarks Applicable CL value=12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is executed plus the time interval that is required for the oscillation to get stabilized after the HOLD mode is released (see Figure 4). Note: The traces to and from the components that are involved in oscillation should be kept as short as possible as the oscillation characteristics are affected by their trace pattern. CF2 CF1 Rf1 C1 XT1 Rf2 Rd1 C2 XT2 Rd2 C3 C4 CF X’tal Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A1860-30/33 LC88F5LA4ACS VDD Operating VDD lower limit 0V Power Reset time RESB Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 Operating mode Unpredictable Reset Initialization instruction execution User instruction execution Reset Time and Oscillation Stabilization Time HOLD release No HOLD release signal HOLD release signal valid Interrupt operation Internal RC oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2 State HOLD HALT Instruction execution HOLD Release and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Timing Charts No.A1860-31/33 LC88F5LA4ACS VDD Note: Reset signal must be present when power supply rises. Determine the value of CRES and RRES so that the reset signal is present for 10μs after the supply voltage gets stabilized. RRES RES CRES Figure 5 Reset Circuit tSCKHBSY tSCKHBSY RUN: SIOCLK: DATAIN: DI0 DI1 DI6 DI7 DI8 DIx DATAOUT: DO0 DO1 DO6 DO7 DO8 DOx Data RAM transfer period (SIO0 and SIO1 only) tSCK SIOCLK: tSCKL tSCKH tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 and SIO1 only) SIOCLK: tSCKL tSCKHA tsDI thDI DATAIN: tdDO DATAOUT: * Remarks: DIx and DOx denote the last bits communicated; x = 0 to 32768 Figure 6 Serial I/O Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A1860-32/33 LC88F5LA4ACS P S Sr P SDA tBUF tHD;STA tR tF tHD;STA tsp SCK tLOW tHD;DAT tHIGH tSU;DAT tSU;STA tSU;STO S: Start condition P: Stop condition Sr: Restart condition Figure 8 I2C Timing ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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