LC87FC096A - ON Semiconductor

Ordering number : ENA2150
LC87FC096A
CMOS IC
FROM 98K byte, RAM 4096 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87FC096A is an 8-bit microcomputer, integrates a number of hardware features such as 98K-byte flash ROM,
4096-byte RAM, On-chip debugging function, 16-bit timers/counter, four 8-bit timers, a 16-bit timer, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports, a single master
I2C/synchronous SIO interface, an 11-channel AD converter, four PWM channels, a system clock frequency divider,
a infrared remote controller receiver function, and interrupt feature.
unit : mm (typ)
3159A
17.2
14.0
48
0.8
Flash ROM
• 100352 × 8 bits
(Address: 00000H to 17FFFH, 1F800H to 1FFFFH)
• Capable of on-board-programing with 2.7 to 3.6V,
of voltage source.
• Block-erasable in 2K byte units
Package Dimensions
33
49
32
64
17
14.0
RAM
• 4096 × 9 bits (LC87FC096A)
Package Form
• QIP64E (14×14):
Lead-free and halogen-free type
1
17.2
Features
16
0.8
0.35
0.15
0.1
3.0max
(2.7)
(1.0)
SANYO : QIP64E(14X14)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.0
D1912HKIM 20121015-S00005 No.A2150-1/26
LC87FC096A
Minimum Bus Cycle
• 83.3ns (12MHz) VDD=2.7 to 3.6V
• 125ns (8MHz)
VDD=2.5 to 3.6V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time
• 250ns (12MHz) VDD=2.7V to 3.6V
• 375ns (8MHz)
VDD=2.5V to 3.6V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
• Power pins
46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6(VSS1 to 3, VDD1 to 3)
Timers
• Timer 0:16-bit timer/counter with a capture register
Mode 0:8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1:8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2:16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3:16-bit counter (with a 16-bit capture register)
• Timer 1:16-bit timer/counter that supports PWM/toggle outputs
Mode 0:8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1:8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2:16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3:16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM)
• Timer 4:8-bit timer with a 6-bit prescaler
• Timer 5:8-bit timer with a 6-bit prescaler
• Timer 6:8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7:8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer A:16-bit timer
Mode 0:8-bit timer with an 8-bit programmable prescaler × 2-channels
Mode 1:16-bit timer with an 8-bit programmable prescaler
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-Speed Clock Counter
• Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz)
• Can generate output real-time
No.A2150-2/26
LC87FC096A
SIO
• SIO0:8-bit Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1:8-bit asynchronous/synchronous serial interface
Mode 0:Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1:Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2:Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3:Bus mode 2 (start detect, 8 data bits, stop detect)
• SMIIC0:Single master I2C/8-bit synchronous SIO
Mode 0:Single-master mode communication
Mode 1:Synchronous 8-bit serial I/O (MSB first)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 12 bits × 11 channels
PWM: Multifrequency 12-bit PWM × 4-channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
• The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Infrared Remote Controller Receiver Circuit
• Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the reference clock source)
• Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording
• X’tal HOLD mode release function
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
• Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
• Able to output oscillation clock of sub clock.
No.A2150-3/26
LC87FC096A
Interrupts
• 31 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/TAL/Infrared remote control receiver
4
0001BH
H or L
INT3/INT5/base timer0/base timer1
5
00023H
H or L
T0H/INT6/TAH
6
0002BH
H or L
T1L/T1H/INT7/SMIIC0
7
00033H
H or L
SIO0/UART1 receive/ UART2 receive
8
0003BH
H or L
SIO1/UART1 transmit/ UART2 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3/RMPWM
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
For system clock
For system clock, with internal Rf
For low-speed system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
Continued on next page.
No.A2150-4/26
LC87FC096A
Continued from preceding page.
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base
timer and infrared remote controller receiver circuit.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the infrared remote controller receiver circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Development Tools
• On-chip debugger: TCB87-TypeC (3wire version) + LC87FC096A
Programming Boards
Package
Programming boards
QIP64E
W87F50256Q
Flash ROM Programmer
Maker
Model
Supported version
Device
Application Version:
Our company
SKK/SKK Type-B/SKK DBG Type-B
After 1.08
(SANYO FWS)
Chip Data Version:
LC87FC096
After 2.42
No.A2150-5/26
LC87FC096A
P31
P30
VSS3
VDD3
PC7/DBGP2
PC6DBGP1
PC5/DBGP0
PC4/RMPWM1
PC3/RMPWM0
PC2/SM0DO
PC1/SM0DA
PC0/SM0CK
P86/AN6
P85/AN5
P84/AN4
P83/AN3
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
P32/UTX1
P71/INT1/T0HCP/AN9
50
31
P33/URX1
P72/INT2/T0IN/NKIN
51
30
P34/UTX2
P73/INT3/T0IN/RMIN
52
29
P35/URX2
RES
53
28
P36
XT1/AN10
P70/INT0/T0LCP/AN8
54
27
P37
XT2/AN11
55
26
P27/INT5/T1IN
VSS1
56
25
P26/INT5/T1IN
CF1
57
24
P25/INT5/T1IN
CF2
58
23
P24/INT5/T1IN/INT7
VDD1
LC87FC096A
59
22
P23INT4/T1IN
P80/AN0
60
21
P22/INT4/T1IN
P81/AN1
61
20
P21/INT4/T1IN
8
9 10 11 12 13 14 15 16
P05/CKO
7
P04
6
P03
5
P02
4
P01
3
P00
2
VSS2
1
VDD2
P06/T6O
PWM3
17
PWM2
64
P17/T1PWMH/BUZ
P11/SI0/SB0
P16/T1PWML
P07/T7O
P15/SCK1
P20/INT4/T1IN/INT6
18
P14/SI1/SB1
19
63
P13/SO1
62
P12/SCK0
P82/AN2
P10/SO0
Top view
QIP64E (14×14) “Lead-free and halogen-free type”
No.A2150-6/26
LC87FC096A
System Block Diagram
Interrupt control
IR
PLA
Standby control
RC
X’tal
Clock
generator
Flash ROM
CF
PC
SIO0
Bus interface
SIO1
Port 0
ACC
SMIIC0
Port 1
B register
Timer 0
Port 2
C register
Timer 1
Port 7
ALU
Timer 4
Port 8
Timer 5
ADC
PSW
Timer 6
INT0 to INT7
Noise filter
RAR
Timer 7
Port 3
RAM
Timer A
Port C
Stack pointer
Base timer
UART1
Watchdog timer
UART2
On-chip Debugger
PWM2/3
Remote control
receiver circuit
RMPWM
No.A2150-7/26
LC87FC096A
Pin Description
Pin Name
I/O
Description
Option
VSS1, VSS2, VSS3
-
- Power supply pin
VDD1, VDD2, VDD3
-
+ Power supply pin
No
• 8-bit I/O port
Yes
Port 0
I/O
No
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Shared Pins
P05 : Clock output (system clock / can selected from sub clock)
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input/bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1 PWML output
P17 : Timer 1 PWMH output/beeper output
Port 2
P20 to P27
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A2150-8/26
LC87FC096A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Shared pins
P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71 : INT1 input/HOLD reset input/timer 0H capture input
P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
remote control receiver input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared pins
AD converter input port : AN0 (P80) to AN6 (P86)
PWM2
I/O
No
• General-purpose I/O available
PWM3
Port 3
• PWM2 and PWM3 output ports
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P37
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PC0: SMIIC0 clock input/output
PC1: SMIIC0 bus input/output/data input
PC2: SMIIC0 data output (used in 3-wire SIO mode)
PC3: RMPWM0 output
PC4: RMPWM1 output
PC5: DBGP0
PC6: DBGP1
PC7: DBGP2
DBGP0 to DBGP2: On-chip Debugger
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A2150-9/26
LC87FC096A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
Option Type
P00 to P07
1 bit
1
P10 to P17
1 bit
P20 to P27
1 bit
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
P70
-
No
Nch-open drain
P71 to P73
-
No
CMOS
Programmable
P80 to P86
-
No
Nch-open drain
No
PWM2, PWM3
-
No
CMOS
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
P30 to P37
PC0 to PC7
1 bit
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
XT1
-
No
Input for 32.768kHz crystal oscillator (Input only)
No
XT2
-
No
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose output
mode)
Note 1:Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2 and VSS3 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Back-up
capacitor
LSI
VDD1
Power
Supply
VDD2
VDD3
VSS1 VSS2 VSS3
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up
capacitor
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A2150-10/26
LC87FC096A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Maximum supply
VDD max
VDD 1, VDD2, VDD3
VDD1=VDD2=VDD3
voltage
Input voltage
VI(1)
XT1, CF1
Input/output voltage
VIO(1)
Ports 0, 1, 2
min
typ
max
unit
-0.3
+4.6
-0.3
VDD+0.3
V
Ports 7, 8
-0.3
Ports 3, C
VDD+0.3
PWM2, PWM3, XT2
Peak output
IOPH(1)
current
High level output current
Mean output
CMOS output select
Per 1 applicable pin
PWM2, PWM3
Per 1 applicable pin
-12.5
IOPH(3)
P71 to P73
Per 1 applicable pin
-4.5
IOMH(1)
Ports 0, 1, 2
CMOS output select
Ports 3, C
Per 1 applicable pin
IOMH(2)
PWM2, PWM3
Per 1 applicable pin
IOMH(3)
P71 to P73
Per 1 applicable pin
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
current
ΣIOAH(2)
Port 1
Total of all applicable pins
PWM2, PWM3
ΣIOAH(3)
Ports 0, 2
Total of all applicable pins
ΣIOAH(4)
Ports 0, 1, 2
Total of all applicable pins
PWM2, PWM3
Peak output
-7.5
IOPH(2)
current
(Note 1-1)
Ports 0, 1, 2
Ports 3, C
-5
-10
-3
-10
-15
-15
-30
ΣIOAH(5)
Port 3
Total of all applicable pins
-15
ΣIOAH(6)
Port C
Total of all applicable pins
-15
ΣIOAH(7)
Ports 3, C
Total of all applicable pins
-30
P02 to P07
Per 1 applicable pin
IOPL(1)
current
Ports 1, 2
10
Ports 3, C
PWM2, PWM3
Low level output current
Mean output
IOPL(2)
P00, P01
IOPL(3)
IOML(1)
mA
Per 1 applicable pin
15
Ports 7, 8, XT2
Per 1 applicable pin
7.5
P02 to P07
Per 1 applicable pin
current
Ports 1, 2
(Note 1-1)
Ports 3, C
7.5
PWM2, PWM3
Total output
IOML(2)
P00, P01
Per 1 applicable pin
10
IOML(3)
Ports 7, 8, XT2
Per 1 applicable pin
5
ΣIOAL(1)
Port 7
Total of all applicable pins
current
15
P83 to P86, XT2
ΣIOAL(2)
P80 to P82
Total of all applicable pins
10
ΣIOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
25
ΣIOAL(4)
Port 1
Total of all applicable pins
25
PWM2, PWM3
ΣIOAL(5)
Ports 0, 2
Total of all applicable pins
ΣIOAL(6)
Ports 0, 1, 2
Total of all applicable pins
25
50
PWM2, PWM3
Maximum power
ΣIOAL(7)
Port 3
Total of all applicable pins
25
ΣIOAL(8)
Port C
Total of all applicable pins
25
ΣIOAL(9)
Ports 3, C
Total of all applicable pins
50
Pdmax
QIP64E(14×14)
Ta=-40 to +85°C
300
dissipation
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
-40
85
-55
125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A2150-11/26
LC87FC096A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD (1)
VDD1=VDD2=VDD3
supply voltage
(Note 2-1)
Memory
VHD
VDD1=VDD2=VDD3
sustaining
min
typ
max
unit
0.245μs ≤ tCYC ≤ 200μs
2.7
3.6
0.367μs ≤ tCYC ≤ 200μs
2.5
3.6
2.0
3.6
RAM and register contents
sustained in HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2
P71 to P73
2.5 to 3.6
P70 port input
0.3VDD
VDD
+0.7
/interrupt side
VIH(2)
Ports 0, 8, 3, C
PWM2, PWM3
VIH(3)
Port 70 watchdog
timer side
VIH(4)
Low level input
VIL(1)
voltage
XT1, XT2, CF1, RES
2.5 to 3.6
0.3VDD
2.5 to 3.6
0.9VDD
VDD
2.5 to 3.6
0.75VDD
VDD
2.5 to 3.6
VSS
0.25VDD
2.5 to 3.6
VSS
0.2VDD
2.5 to 3.6
VSS
2.5 to 3.6
VSS
0.25VDD
2.7 to 3.6
0.245
200
2.5 to 3.6
0.367
200
2.7 to 3.6
0.1
12
2.5 to 3.6
0.1
8
2.7 to 3.6
0.2
24
2.5 to 3.6
0.2
16
VDD
+0.7
V
Ports 1, 2
P71 to P73
P70 port input/
interrupt side
VIL(2)
Ports 0, 8, 3, C
PWM2, PWM3
VIL(3)
Port 70 watchdog
timer side
VIL(4)
Instruction cycle
XT1, XT2, CF1, RES
tCYC
0.8VDD
-1.0
μs
time
(Note 2-2)
External system
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
clock frequency
division rate=1/1
• External system clock
duty=50±5%
• CF2 pin open
• System clock frequency
division rate=1/2
Oscillation
FmCF(1)
CF1, CF2
frequency range
(Note 2-3)
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
8MHz ceramic oscillation
See Fig. 1.
FmRC
FsX’tal
Internal RC oscillation
XT1, XT2
2.7 to 3.6
12
2.5 to 3.6
8
2.5 to 3.6
0.3
1.0
MHz
MHz
2.0
32.768kHz crystal oscillation
See Fig. 2.
2.5 to 2.6
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A2150-12/26
LC87FC096A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
High level input
Symbol
IIH(1)
current
IIH(2)
Low level input
Pins
Conditions
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports 3, C
RES
VIN=VDD
(Including output Tr's off leakage
PWM2, PWM3
current)
XT1, XT2
For input port specification
IIH(3)
CF1
VIN=VDD
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports 3, C
VIN=VSS
(Including output Tr's off leakage
current
RES
PWM2, PWM3
IIL(2)
XT1, XT2
voltage
voltage
1
2.5 to 3.6
1
2.5 to 3.6
15
2.5 to 3.6
-1
For input port specification
2.5 to 3.6
-1
CF1
VIN=VSS
2.5 to 3.6
-15
Ports 0, 1, 2
IOH=-0.4mA
3.0 to 3.6
Ports 3, C
IOH=-0.2mA
2.5 to 3.6
VDD-0.4
VDD-0.4
VOH(3)
P71 to P73
VOH(5)
VOH(6)
PWM2, PWM3
VOL(1)
Ports 0, 1, 2
VOL(2)
Ports 3, C
PWM2, PWM3
max
2.5 to 3.6
VOH(1)
VOH(2)
IOH=-0.4mA
3.0 to 3.6
VDD-0.4
IOH=-0.2mA
2.5 to 3.6
IOH=-1.6mA
3.0 to 3.6
VDD-0.4
VDD-0.4
IOH=-1mA
2.5 to 3.6
VDD-0.4
IOL=1.6mA
3.0 to 3.6
0.4
IOL=1mA
2.5 to 3.6
0.4
VOL(3)
Ports 7, 8
IOL=1.6mA
3.0 to 3.6
0.4
VOL(4)
XT2
IOL=1mA
2.5 to 3.6
0.4
VOL(5)
P00, P01
IOL=5mA
3.0 to 5.5
0.4
IOL=2.5mA
2.2 to 5.5
VOH=0.9VDD
3.0 to 3.6
15
35
80
15
35
100
VOL(6)
Pull-up
Rpu(1)
Ports 0, 1, 2, 7
resistance
Rpu(2)
Ports 3, C
2.5 to 3.6
Hysteresis
VHYS
RES
Ports 1, 2, 7
2.5 to 3.6
voltage
Pin capacitance
typ
IIL(3)
VOH(4)
Low level output
min
CP
All pins
unit
μA
current)
VIN=VSS
High level output
VDD[V]
V
0.4
kΩ
0.1
VDD
V
For pins other than that under test:
VIN=VSS
f=1MHz
2.5 to 3.6
10
pF
Ta=25°C
No.A2150-13/26
LC87FC096A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 =0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pin/
Conditions
Remarks
SCK0(P12)
VDD [V]
See Fig. 6.
tSCKH(1)
2.5 to 3.6
pulse width
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.5 to 3.6
pulse width
1/2
• Continuous data
tSCKHA(2)
transmission/reception mode
tSCKH(2)
• CMOS output selected
+2tCYC
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
tSCKHA(1)
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect
to rising edge of SIOCLK.
2.5 to 3.6
0.03
2.5 to 3.6
0.03
• See Fig. 6.
Data hold time
Output clock
Input clock
Output delay
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
2.5 to 3.6
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
2.5 to 3.6
(1/3)tCYC
+0.05
μs
1tCYC
+0.05
(Note 4-1-3)
2.5 to 3.6
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans / rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A2150-14/26
LC87FC096A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig. 6.
2.5 to 3.6
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.5 to 3.6
0.03
2.5 to 3.6
0.03
• See Fig. 6.
Data hold time
Output delay time
Serial output
tsDI(2)
unit
1
2.5 to 3.6
pulse width
High level
max
1
• See Fig. 6.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
VDD [V]
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of
2.5 to 3.6
output state change in
(1/3)tCYC
+0.05
open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A2150-15/26
LC87FC096A
3-1. SMIIC0 Simple SIO Mode Input/Output Characteristics
Input clock
Symbol
Period
tSCK (4)
Low level
tSCKL (4)
Specification
Applicable
Conditions
Pin/Remarks
SM0CK (PC0)
VDD[V]
See Fig. 6.
Period
SM0CK (PC0)
• CMOS output selected
tSCKL (5)
2/3
4/3
2.5 to 3.6
pulse width
High level
1/2
tSCK
tSCKH (5)
1/2
Serial output
Serial input
pulse width
Data setup time
tsDI (3)
SM0DA (PC1)
• Specified with respect to
rising edge of SIOCLK
Data hold time
thDI (3)
Output delay
tdD0 (5)
time
unit
2/3
• See Fig. 6.
Low level
max
tCYC
tSCKH (4)
tSCK (5)
typ
4/3
2.5 to 3.6
pulse width
High level
min
pulse width
Output clock
Serial clock
Parameter
• See Fig. 6.
SM0DO (PC2),
• Specified with respect to
SM0DA (PC1)
falling edge of SIOCLK
• Specified as interval up to
time when output state
0.03
2.5 to 3.6
0.03
μs
2.5 to 3.6
1/3tCYC
+0.05
starts changing.
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
No.A2150-16/26
LC87FC096A
3-2. SMIIC0 I2C Mode Input/Output Characteristics
Clock
Input clock
Parameter
Symbol
Period
tSCL
Low level
tSCLL
Applicable
Pin/Remarks
SM0CK (PC0)
Specification
Conditions
VDD[V]
• See Fig. 8.
High level
Output clock
SM0CK (PC0)
• Specified as interval up to
starts changing.
tSCLLx
pulse width
High level
2.5
10
time when output state
Low level
2.5 to 3.6
1/2
tSCL
tSCLHx
1/2
pulse width
SM0CK and SM0DA
tsp
pins input spike
Unit
2
pulse width
tSCLx
max
Tfilt
tSCLH
Period
typ
5
2.5 to 3.6
pulse width
Min
SM0CK (PC0)
• See Fig. 8.
SM0DA (PC1)
2.5 to 3.6
1
Tfilt
Bus release time
between start
Input
suppression time
tBUF
SM0CK (PC0)
• See Fig. 8.
SM0DA (PC1)
2.5
Tfilt
and stop
tBUFx
SM0CK (PC0)
• Standard clock mode
SM0DA (PC1)
• Specified as interval up to
Output
time when output state
2.5 to 3.6
5.5
starts changing.
μs
• High-speed clock mode
• Specified as interval up to
1.6
time when output state
starts changing.
Start/restart
tHD;STA
condition hold
SM0DA (PC1)
• When SMIIC register
control bit, SHDS=0
2.0
• See Fig. 8.
Input
time
SM0CK (PC0)
Tfilt
• When SMIIC register
control bit, SHDS=1
2.5
• See Fig. 8.
tHD;STAx
SM0CK (PC0)
• Standard clock mode
SM0DA (PC1)
• Specified as interval up to
2.5 to 3.6
4.1
Output
time when output state
starts changing.
μs
• High-speed clock mode
• Specified as interval up to
1.0
time when output state
condition setup
Input
starts changing.
Restart
tSU;STA
SM0CK (PC0)
• See Fig. 8.
SM0DA (PC1)
1.0
Tfilt
time
tSU;STAx
SM0CK (PC0)
• Standard clock mode
SM0DA (PC1)
• Specified as interval up to
Output
time when output state
2.5 to 3.6
5.5
starts changing.
μs
• High-speed clock mode
• Specified as interval up to
time when output state
1.6
starts changing.
Continued on next page.
No.A2150-17/26
LC87FC096A
Continued from preceding page.
Stop condition
setup time
Symbol
Input
Parameter
tSU;STO
Specification
Applicable
Conditions
Pin/Remarks
SM0CK (PC0)
VDD[V]
SM0DA (PC1)
tSU;STOx
typ
max
1.0
SM0CK (PC0)
• Standard clock mode
SM0DA (PC1)
• Specified as interval up to time
when output state starts
Output
Min
Unit
• See Fig. 8.
2.5 to 3.6
Tfilt
4.9
changing.
μs
• High-speed clock mode
• Specified as interval up to time
1.6
when output state starts
Data setup
Output
time
Input
Output
Input
changing.
Data hold time
tHD;DAT
SM0CK (PC0)
• See Fig. 8.
SM0DA (PC1)
tHD;DATx
SM0CK (PC0)
SM0DA (PC1)
0
• Specified as interval up to time
2.5 to 3.6
when output state starts
Tfilt
1
1.5
changing.
tSU;DAT
SM0CK (PC0)
• See Fig. 8.
SM0DA (PC1)
tSU;DATx
SM0CK (PC0)
SM0DA (PC1)
1
• Specified as interval up to time
when output state starts
changing.
2.5 to 3.6
Tfilt
1tSCL1.5Tfilt
Note 4-3-2: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-3: The value of Tfilt is determined by the values of the register SMIC0BRG, bits 7 and 6 (BRP1, BRP0) and
the system clock frequency.
BRP1
BRP0
Tfilt
0
0
(1/3)tCYC×1
0
1
(1/3)tCYC×2
1
0
(1/3)tCYC×3
1
1
(1/3)tCYC×4
Set bits (BPR1, BPR0) so that the value of Tfilt falls between the following range:
250ns Tfilt > 140ns
Note 4-3-4: The standard clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 1
SCL frequency setting ≤ 100kHz
The high-speed clock mode refers to a mode that is entered by configuring SMIC0BRG as follows:
250ns ≥ Tfilt > 140ns
BRDQ (bit5) = 0
SCL frequency setting ≤ 400kHz
No.A2150-18/26
LC87FC096A
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD [V]
High/low level
tPIH(1)
INT0(P70), INT1(P71),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT2(P72), INT4(P20 to P23),
• Event inputs for timer 0 or 1
are enabled.
INT5(P24 to P27)
min
typ
2.5 to 3.6
1
2.5 to 3.6
2
max
unit
INT6(P20), INT7(P24)
tPIH(2)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is 1/1
• Event inputs for timer 0 are
enabled.
tCYC
tPIH(3)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is 1/32
• Event inputs for timer 0 are
2.5 to 3.6
64
2.5 to 3.6
256
2.5 to 3.6
200
enabled.
tPIH(4)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is 1/128
• Event inputs for timer 0 are
enabled.
tPIL(5)
RES
Resetting is enabled.
μs
AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V
<12bits AD Converter Mode at Ta = -40°C to +85°C >
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P80) to
Absolute
ET
AN6(P86),
Conversion time
TCAD
IAINH(1)
IAINL(1)
12
bit
±16
See Conversion time calculation
3.0 to 3.6
64
115
AN10(XT1),
formulas. (Note 6-2)
2.7 to 3.6
128
230
2.5 to 3.6
256
460
2.5 to 3.6
VSS
VDD
VAIN
input current
unit
AN9(P71),
voltage range
Analog port
max
2.5 to 3.6
AN11(XT2)
Analog input
typ
2.5 to 3.6
(Note 6-1)
AN8(P70),
accuracy
min
analog channel
VAIN=VDD
2.5 to 3.6
VAIN=VSS
2.5 to 3.6
1
-1
LSB
μs
V
μA
<8bits AD Converter Mode at Ta = -40°C to +85°C >
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P80) to
Absolute
ET
AN6(P86),
min
2.5 to 3.6
(Note 6-1)
typ
max
unit
8
bit
±1.5
2.5 to 3.6
accuracy
AN8(P70),
Conversion
AN9(P71),
See Conversion time calculation
3.0 to 3.6
39
71
AN10(XT1),
formulas. (Note 6-2)
2.7 to 3.6
79
140
2.5 to 3.6
157
280
2.5 to 3.6
VSS
VDD
TCAD
time
AN11(XT2)
Analog input
VAIN
voltage range
Analog port
IAINH(1)
input current
IAINL(1)
analog channel
VAIN=VDD
2.5 to 3.6
VAIN=VSS
2.5 to 3.6
1
-1
LSB
μs
V
μA
12bits AD Converter Mode: TCAD(Conversion time)= ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time)=((32/(AD division ratio))+2)×(1/3)×tCYC
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A2150-19/26
LC87FC096A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
IDDOP(1)
Conditions
rks
consumption
VDD1
=VDD2
current
=VDD3
Normal mode
Specification
Pins/Rema
VDD[V]
Typ
Max
unit
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
(Note 7-1)
min
2.7 to 3.6
3.6
9.5
2.5 to 3.6
2.9
7.1
2.5 to 3.6
0.186
0.96
2.5 to 3.6
11.5
58
2.7 to 3.6
1.5
2.9
2.5 to 3.6
1
1.8
2.5 to 3.6
0.067
0.28
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=8MHz ceramic oscillation mode
IDDOP(2)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
mA
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
IDDOP(3)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• FmCF=0Hz (oscillation stopped)
IDDOP(4)
• FmX'al=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
μA
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FmX’tal=32.768kHz by crystal oscillation
HALT mode
IDDHALT(1)
(Note 7-1)
• FmCF=12MHz ceramic oscillation mode
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(2)
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
mA
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(3)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A2150-20/26
LC87FC096A
Continued from preceding page.
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FmX'al=32.768kHz by crystal oscillation
HALT mode
IDDHALT(4)
(Note 7-1)
min
typ
Max
unit
• FmCF=0Hz (oscillation stopped)
mode.
• System clock set to 32.768kHz side.
2.5 to 3.6
7.4
49
2.5 to 3.6
0.04
20
μA
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
HOLD mode
IDDHOLD(1)
VDD1
• HOLD mode
• CF1=VDD or open (External clock mode)
consumption
current
Timer HOLD
μA
• Timer HOLD mode
IDDHOLD(2)
mode
• CF1=VDD or open (External clock mode)
consumption
• FmX'tal=32.768kHz by crystal oscillation
current
2.5 to 3.6
5.9
35
mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
Min
Typ
Max
unit
• Without CPU curent
programming
2.7 to 3.6
7
11
mA
current
Programming
tFW(1)
• 2k byte Erasing
2.7 to 3.6
12
15
ms
time
tFW(2)
• 2 byte Programming
2.7 to 3.6
35
45
µs
No.A2150-21/26
LC87FC096A
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Transfer rate
UBR
min
typ
max
unit
8192/3
tCYC
P32(UTX1),
P33(URX1),
2.5 to 3.6
P34(UTX2),
16/3
P35(URX2)
Data length:
Stop bits:
Parity bits:
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Stop bit
Start of
transmission
Transmit data (LSB first)
End of
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
Start bit
Receive data (LSB first)
Start of
reception
End of
reception
UBR
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1µF.
• Use thicker pattern for VDD1 and VSS1.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
No.A2150-22/26
LC87FC096A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Frequency
Circuit Constant
Vendor Name
12MHz
Oscillator Name
Operating
C1
C2
Rf1
Rd1
[pF]
[pF]
[Ω]
[Ω]
CSTCE12M0G52-R0
(10)
(10)
Open
330
CSTCE8M00G52-R0
(10)
(10)
Open
CSTLS8M00G53-B0
(15)
(15)
CSTCR4M00G53-R0
(15)
CSTLS4M00G53-B0
(15)
Voltage Range
Oscillation
Stabilization Time
typ
max
[ms]
[ms]
2.2 to 3.6
0.02
0.2
680
2.2 to 3.6
0.02
0.2
Open
680
2.2 to 3.6
0.02
0.2
(15)
Open
1.5K
2.2 to 3.6
0.02
0.2
(15)
Open
1.5K
2.2 to 3.6
0.01
0.1
[V]
C1, C2
integrated type
C1, C2
integrated type
8MHz
MURATA
Remarks
C1, C2
integrated type
C1, C2
integrated type
4MHz
C1, C2
integrated type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
EPSON
TOYOCOM
Circuit Constant
Oscillator Name
MC-306
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
9
9
OPEN
330K
2.2 to 3.6
1.0
3.0
Remarks
CL=7pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
Rf
XT1
XT2
Rf
Rd1
C1
C2
Rd2
C3
C4
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A2150-23/26
LC87FC096A
VDD
Power supply
Operating VDD lower limit
0V
Reset time
RES
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating
mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A2150-24/26
LC87FC096A
VDD
Note :
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RRES
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial Input/Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A2150-25/26
LC87FC096A
P
SDA
S
P
Sr
tBUF
tHD;STA tR
tHD;STA
tF
tsp
SCK
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
S: Start condition
P: Stop condition
Sir: Restart condition
Figure 8 I2C Timing
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PS No.A2150-26/26