KAE02150 D

KAE-02150
1920 (H) x 1080 (V)
Interline CCD Image Sensor
The KAE−02150 Image Sensor is a 1080p (1920 × 1080) CCD in
a 2/3″ optical format that provides exceptional imaging performance
in extreme low light applications. Each of the sensor’s four outputs
incorporate both a conventional horizontal CCD register and a high
gain EMCCD register.
An intra-scene switchable gain feature samples each charge packet
on a pixel-by-pixel basis. This enables the camera system to determine
whether the charge will be routed through the normal gain output or
the EMCCD output based on a user selectable threshold. This feature
enables imaging in extreme low light, even when bright objects are
within a dark scene, allowing a single camera to capture quality
images from sunlight to starlight.
This image sensor is based on the 5.5-micron Interline Transfer
CCD Platform, and features extended dynamic range, excellent
imaging performance, and a flexible readout architecture that enables
use of 1, 2, or 4 outputs. A vertical overflow drain structure suppresses
image blooming, provides excellent MTF, and enables electronic
shuttering for precise exposure control.
www.onsemi.com
Figure 1. KAE−02150 Interline CCD
Image Sensor
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CCD; with EMCCD
Features
Total Number of Pixels
2004 (H) × 1144 (V)
Number of Effective Pixels
1960 (H) × 1120 (V)
Number of Active Pixels
1920 (H) × 1080 (V)
Pixel Size
5.5 mm (H) × 5.5 mm (V)
Active Image Size
10.56 mm (H) × 5.94 mm (V)
12.1 mm (Diag.), 2/3″ Optical Format
Aspect Ratio
16:9
Number of Outputs
1, 2, or 4
Charge Capacity
20,000 e−
•
•
•
•
•
•
•
Output Sensitivity
44 mV/e−
Quantum Efficiency
Mono/Color (RGB)
50% / 33%, 41%, 43%
Read Noise (20 MHz)
Normal Mode (1× Gain)
Intra-Scene Mode (20× Gain)
9 e− rms
< 1 e− rms
Dark Current (0°C)
Photodiode, VCCD
< 0.1 e−/s, 6 e−/s
Intra-Scene Switchable Gain
Wide Dynamic Range
Low Noise Architecture
Exceptional Low Light Imaging
Global Shutter
Excellent Image Uniformity and MTF
Bayer Color Pattern and Monochrome
Applications
•
•
•
•
Surveillance
Scientific Imaging
Medical Imaging
Intelligent Transportation
ORDERING INFORMATION
Dynamic Range
Normal Mode (1× Gain)
Intra-Scene Mode (20× Gain)
68 dB
86 dB
Charge Transfer Efficiency
0.999999
Blooming Suppression
> 1000 X
Smear
−100 dB
Image Lag
< 1 e−
Maximum Pixel Clock Speed
40 MHz
Maximum Frame Rate
Normal Mode, Intra-Scene Mode
60 fps (40 MHz), 30 fps (20 MHz)
Package
135 pin PGA
Cover Glass
Clear Glass, Taped
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 0°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 2
1
Publication Order Number:
KAE−02150/D
KAE−02150
ORDERING INFORMATION
US export controls apply to all shipments of this product
designated for destinations outside of the US and Canada,
requiring ON Semiconductor to obtain an export license
from the US Department of Commerce before image sensors
or evaluation kits can be exported.
Table 2. ORDERING INFORMATION
Part Number
Description
KAE−02150−ABB−JP−FA
Monochrome, Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Standard Grade
KAE−02150−ABB−JP−EE
Monochrome, Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Grade
KAE−02150−FBB−JP−FA
Color (Bayer RGB), Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Standard Grade
KAE−02150−FBB−JP−EE
Color (Bayer RGB), Microlens, PGA Package,
Taped Clear Cover Glass (No Coatings), Engineering Grade
Marking Code
KAE−02150−ABB
Serial Number
KAE−02150−FBB
Serial Number
Table 3. EVALUATION SUPPORT
Part Number
Description
KAE−02150−AB−A−GEVK
KAE−02150 Evaluation Kit
LENS−MOUNT−KIT−C−GEVK
Lens Mount Kit for IT−CCD Evaluation Hardware
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
www.onsemi.com
2
KAE−02150
DEVICE DESCRIPTION
Architecture
VOUTC3
VOUTD3
2072
1
28
1 10
2072
24 8
960
960
8 24
10 1
28
4
1
4
14
VOUTD2
8 24
VOUTB2
VOUTA1
VOUTA2
VOUTD1
1920 y 1080
5.5 mm Pixels
24 8
VOUTB1
VOUTC2
VOUTC1
8
8
14
4
1
4
28
1 10
24 8
2072
960
960
2070
8 24
2070
VOUTA3
10 1
28
1
2072
VOUTB3
Figure 2. Block Diagram
Dark Reference Pixels
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photo-site. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent upon light level
and exposure time and non-linearly dependent on
wavelength. When the photodiodes charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming
There are 14 dark reference rows at the top and bottom of
the image sensor, as well as 24 dark reference columns on the
left and right sides. However, the rows and columns at the
very edges should not be included in acquiring a dark
reference signal, since they may be subject to some light
leakage.
Active Buffer Pixels
8 unshielded pixels adjacent to any leading or trailing dark
reference regions are classified as active buffer pixels. These
pixels are light sensitive but are not tested for defects and
non-uniformities.
ESD Protection
Adherence to the power-up and power-down sequence is
critical. Failure to follow the proper power-up and
power-down sequences may cause damage to the sensor. See
Power-Up and Power-Down Sequence section.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
www.onsemi.com
3
KAE−02150
Bayer Color Filter Pattern
VOUTC3
VOUTD3
2072
1
28
1 10
2072
24 8
960
960
8 24
10 1
28
4
1
4
14
VOUTD2
8 24
VOUTB2
VOUTA1
VOUTA2
VOUTD1
1920 y 1080
5.5 mm Pixels
24 8
VOUTB1
VOUTC2
VOUTC1
8
8
14
4
1
4
28
1 10
24 8
2072
960
960
2070
8 24
2070
VOUTA3
VOUTB3
Figure 3. Bayer Color Filter Pattern
www.onsemi.com
4
2072
10 1
28
1
KAE−02150
Physical Description
Pin Grid Array and Pin Description
H
G
F
E
D
C
B
A
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Figure 4. PGA Package Designations (Bottom View)
Table 4. PIN DESCRIPTION
Pin
Label
Description
A02
V3B
VCCD Bottom Phase 3
A03
N/C
No Connection
A04
RG2a
Amplifier 2 Reset, Quadrant A
A05
N/C
A06
VDD23ab
No Connection
Amplifier 2 and 3 Supply, Quadrants A, B
A07
H1BEMa
EMCCD Barrier Phase 1, Quadrant A
A08
H2Ba
HCCD Barrier Phase 2, Quadrant A
A09
GND
Ground
A10
H2Bb
HCCD Barrier Phase 2, Quadrant B
A11
H1BEMb
EMCCD barrier phase 1, Quadrant B
A12
VDD23ab
Amplifier 2 and 3 Supply, Quadrants A, B
A13
N/C
A14
RG2a
No Connection
A15
N/C
No Connection
A16
V3B
VCCD Bottom Phase 3
A17
ESD
ESD Protection Disable
B01
DEVID
B02
V4B
B03
VOUT1a
Amplifier 2 Reset, Quadrant B
Device ID Resistor
VCCD Bottom Phase 4
Amplifier 1 Output, Quadrant A
www.onsemi.com
5
KAE−02150
Table 4. PIN DESCRIPTION (continued)
Pin
Label
Description
B04
VOUT2a
Video Output 2, Quadrant A
B05
H2SW3a
HCCD Output 3 Selector, Quadrant A
B06
VOUT3a
Video Output 3, Quadrant A
B07
H2BEMa
EMCCD Barrier Phase 2, Quadrant A
B08
H1Ba
HCCD Barrier Phase 1, Quadrant A
B09
GND
Ground
B10
H1Bb
HCCD Barrier Phase 1, Quadrant B
B11
H2BEMb
EMCCD Barrier Phase 2, Quadrant B
B12
VOUT3b
Video Output 3, Quadrant B
B13
H2SW3b
HCCD Output 3 Selector, Quadrant B
B14
VOUT2b
Video Output 2, Quadrant B
B15
VOUT1b
Amplifier 1 Output, Quadrant B
B16
V4B
VCCD Bottom Phase 4
B17
SUB
Substrate
C01
V1B
VCCD Bottom Phase 1
C02
N/C
No Connection
C03
VSS1a
C04
VDD23ab
Amplifier 1 Return, Quadrant A
Amplifier 2 and 3 Supply, Quadrants A, B
C05
H2SW2a
HCCD Output 2 Selector, Quadrant A
C06
N/C
C07
H1SEMa
C08
H2Sa
HCCD Storage Phase 2, Quadrant A
C09
GND
Ground
C10
H2Sb
HCCD Storage Phase 2, Quadrant B
C11
H1SEMb
No Connection
EMCCD Storage Multiplier Phase 1, Quadrant A
EMCCD Storage Multiplier Phase 1, Quadrant B
C12
N/C
C13
H2SW2b
No Connection
HCCD Output 2 Selector, Quadrant B
C14
VDD23ab
Amplifier 2 and 3 Supply, Quadrants A, B
C15
VSS1b
Amplifier 1 Return, Quadrant B
C16
N/C
No Connection
C17
V1B
VCCD Bottom Phase 1
D01
V2B
VCCD Bottom Phase 2
D02
VDD1a
Amplifier 1 Supply, Quadrant A
D03
RG1a
Amplifier 1 Reset, Quadrant A
D04
H2Xa
Floating Gate Exit HCCD Gate, Quadrant A
D05
H2La
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant A
D06
RG3a
Amplifier 3 Reset, Quadrant A
D07
H2SEMa
D08
H1Sa
HCCD Storage Phase 1, Quadrant A
D09
GND
Ground
D10
H1Sb
HCCD Storage Phase 1, Quadrant B
D11
H2SEMb
D12
RG3b
Amplifier 3 Reset, Quadrant B
D13
H2Lb
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant B
D14
H2Xb
Floating Gate Exit HCCD Gate, Quadrant B
EMCCD Storage Multiplier Phase 2, Quadrant A
EMCCD Storage Multiplier Phase 2, Quadrant B
www.onsemi.com
6
KAE−02150
Table 4. PIN DESCRIPTION (continued)
Pin
Label
Description
D15
RG1b
Amplifier 1 Reset, Quadrant B
D16
VDD1b
Amplifier 1 Supply, Quadrant B
D17
V2B
VCCD Bottom Phase 2
E01
V2T
VCCD Top Phase 2
E02
VDD1c
Amplifier 1 Supply, Quadrant C
E03
RG1c
Amplifier 1 Reset, Quadrant C
E04
H2Xc
Floating Gate Exit HCCD Gate, Quadrant C
E05
H2Lc
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant C
E06
RG3c
Amplifier 3 Reset, Quadrant C
E07
H2SEMc
E08
H1Sc
HCCD Storage Phase 1, Quadrant C
E09
GND
Ground
E10
H1Sd
HCCD Storage Phase 1, Quadrant D
E11
H2SEMd
E12
RG3d
Amplifier 3 Reset, Quadrant D
E13
H2Ld
HCCD Last Gate, Outputs 1, 2 and 3, Quadrant D
E14
H2Xd
Floating Gate Exit HCCD Gate, Quadrant D
E15
RG1d
Amplifier 1 Reset, Quadrant D
E16
VDD1d
Amplifier 1 Supply, Quadrant D
E17
V2T
VCCD Top Phase 2
F01
V1T
VCCD Top Phase 1
F02
N/C
No Connection
EMCCD Storage Multiplier Phase 2, Quadrant C
EMCCD Storage Multiplier Phase 2, Quadrant D
F03
VSS1c
F04
VDD23cd
Amplifier 1 Return, Quadrant C
Amplifier 2 and 3 Supply, Quadrants C, D
F05
H2SW2c
HCCD Output 2 Selector, Quadrant C
F06
N/C
F07
H1SEMc
No Connection
F08
H2Sc
HCCD Storage Phase 2, Quadrant C
F09
GND
Ground
F10
H2Sd
HCCD Storage Phase 2, Quadrant D
F11
H1SEMd
EMCCD Storage Multiplier Phase 1, Quadrant C
EMCCD Storage Multiplier Phase 1, Quadrant D
F12
N/C
F13
H2SW2d
No Connection
HCCD Output 2 Selector, Quadrant D
F14
VDD23cd
Amplifier 2 and 3 Supply, Quadrants C, D
F15
VSS1d
Amplifier 1 Return, Quadrant D
F16
N/C
No Connection
F17
V1T
VCCD Top Phase 1
G01
ESD
ESD Protection Disable
G02
V4T
VCCD Top Phase 4
G03
VOUT1c
Amplifier 1 Output, Quadrant C
G04
VOUT2c
Video Output 2, Quadrant C
G05
H2SW3c
HCCD Output 3 Selector, Quadrant C
G06
VOUT3c
Video Output 3, Quadrant C
G07
H2BEMc
EMCCD Barrier Phase 2, Quadrant C
G08
H1Bc
HCCD Barrier Phase 1, Quadrant C
www.onsemi.com
7
KAE−02150
Table 4. PIN DESCRIPTION (continued)
Pin
Label
Description
G09
GND
Ground
G10
H1Bd
HCCD Barrier Phase 1, Quadrant D
G11
H2BEMd
EMCCD Barrier Phase 2, Quadrant D
G12
VOUT3d
Video Output 3, Quadrant D
G13
H2SW3d
HCCD Output 3 Selector, Quadrant D
G14
VOUT2d
Video Output 2, Quadrant D
G15
VOUT1d
Amplifier 1 Output, Quadrant D
G16
V4T
VCCD Top Phase 4
G17
SUB
Substrate
H01
TD
Temperature Diode Sensor
H02
V3T
VCCD Top Phase 3
H03
N/C
No Connection
H04
RG2c
H05
N/C
H06
VDD23cd
Amplifier 2 and 3 Supply, Quadrants C, D
H07
H1BEMc
EMCCD Barrier Phase 1, Quadrant C
H08
H2Bc
HCCD Barrier Phase 2, Quadrant C
H09
GND
Ground
H10
H2Bd
HCCD Barrier Phase 2, Quadrant D
H11
H1BEMd
EMCCD Barrier Phase 1, Quadrant D
H12
VDD23cd
Amplifier 2 and 3 Supply, Quadrants C, D
H13
N/C
H14
RG2d
H15
N/C
No Connection
H16
V3T
VCCD Top Phase 3
H17
SUBREF
Amplifier 2 Reset, Quadrant C
No Connection
No Connection
Amplifier 2 Reset, Quadrant D
Substrate Voltage Reference
www.onsemi.com
8
KAE−02150
IMAGING PERFORMANCE
Table 5. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Condition
Description
Notes
Light Source
Continuous Red, Green and Blue LED Illumination
Operation
Nominal Operating Voltages and Timing
Temperature
0°C
1
1. For monochrome sensor, only green LED used.
Table 6. SPECIFICATIONS
Description
Dark Field Global
Non-Uniformity
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
Temperature
Tested at (5C)
DSNU
−
−
2.0
mV pp
Die
TBD
−
2.0
5.0
% rms
Die
TBD
1
−
5.0
15.0
% pp
Die
TBD
1
−
1.0
2.0
% rms
Die
TBD
1
Bright Field Global
Non-Uniformity
Bright Field Global Peak to
Peak Non-Uniformity
PRNU
Bright Field Center
Non-Uniformity
Notes
Maximum Photoresponse
Nonlinearity
(EMCCD Gain = 1)
NL
−
2
−
%
Design
2
Maximum Gain Difference
Between Outputs
(EMCCD Gain = 1)
DG
−
10
−
%
Design
2
Maximum Signal Error due
to Nonlinearity Differences
(EMCCD Gain = 1)
DNL
−
1
−
%
Design
2
Horizontal CCD Charge
Capacity
HNe
−
30
−
ke−
Design
Vertical CCD Charge
Capacity
VNe
−
30
−
ke−
Design
Photodiode Charge
Capacity
PNe
−
20
−
ke−
Die
Horizontal CCD Charge
Transfer Efficiency
HCTE
0.999995
0.999999
−
Die
Vertical CCD Charge
Transfer Efficiency
VCTE
0.999995
0.999999
−
Die
IPD
−
0.1
70
−
6
−
Photodiode Dark Current
(Average)
Vertical CCD Dark Current
e−/p/s
e−
Die
0
TBD
0
Image Lag
Lag
−
−
<1
Antiblooming Factor
XAB
1,000
−
−
Vertical Smear (blue light)
Smr
−
−100
−
dB
Design
Read Noise
(EMCCD Gain = 1)
ne−T
Design
−
9
−
Read Noise
(EMCCD Gain = 20)
−
<1
−
e− rms
EMCCD Excess Noise
Factor (Gain = 20x)
−
1.4
−
9
3
Design
Design
e− rms
www.onsemi.com
TBD
Design
4
0
KAE−02150
Table 6. SPECIFICATIONS (continued)
Symbol
Min.
Nom.
Max.
Units
Sampling
Plan
DR
−
68
−
dB
Design
Dynamic Range
(High Gain)
−
60
−
dB
Dynamic Range
(Intra-Scene)
−
86
−
dB
Description
Dynamic Range
(ECCD Gain = 1)
Output Amplifier DC Offset
(VOUT2, VOUT3)
VODC
8.0
10
12.0
V
Die
Output Amplifier DC Offset
(VOUT1)
VODC
−0.5
1.0
2.5
V
Die
Output Amplifier
Bandwidth
f−3dB
−
250
−
MHz
Die
Output Amplifier
Impedance
ROUT
−
140
−
W
Die
Output Amplifier
Sensitivity (Normal output)
DV/DN
−
44
−
mV/e−
Design
Output Amplifier
Sensitivity
(Floating Gate Amplifier)
DV/DN
(FG)
−
6.2
−
mV/e−
Design
Quantum Efficiency (Peak)
Monochrome
Red
Green
Blue
QEMAX
%
Design
−
−
−
−
50%
33%
41%
43%
−
−
−
−
W
Design
Power
4-Output Mode
(20MHz)
(40MHz)
2-Output Mode
(20MHz)
(40MHz)
1-Output Mode
(20MHz)
(40MHz)
1.
2.
3.
4.
5.
6.
−
−
0.8
0.7
−
−
−
−
0.5
0.5
−
−
−
−
0.4
0.4
−
−
Per color
Value is over the range of 10% to 90% of photodiode saturation.
The operating value of the substrate reference voltage, VAB, can be read from pin 60.
At 40 MHz.
Uses 20LOG (PNe / ne−T).
Calculated from f−3dB = 1 / 2p ⋅ ROUT ⋅ CLOAD where CLOAD = 5 pF.
www.onsemi.com
10
Temperature
Tested at (5C)
Notes
4, 5
TBD
6
TBD
KAE−02150
TYPICAL PERFORMANCE CURVES
Quantum Efficiency
Monochrome with Microlens
60
Quantum Efficiency (%)
50
40
30
20
10
0
300
400
500
600
700
800
1,000
900
Wavelength (nm)
Figure 5. Monochrome QE with Microlens
Color (Bayer RGB) with Microlens
45
Red
Quantum Efficiency (%)
40
Green
35
Blue
30
25
20
15
10
5
0
350
400
450
500
550
600
650
700
750
800
850
Wavelength (nm)
Figure 6. Color (Bayer RGB) QE with Microlens
www.onsemi.com
11
900
950
1,000
KAE−02150
Angular Response
The incident light angle is varied in a plane parallel to the HCCD.
Monochrome with Microlens
100
90
80
Response
70
60
50
40
30
20
10
0
−30
−20
−10
0
10
20
30
Angle (Deg)
Figure 7. Monochrome with Microlens Angle Response
Color (Bayer RGB) with Microlens
100
Red
90
Green
80
Blue
Response
70
60
50
40
30
20
10
0
−30
−20
−10
0
Angle (Deg)
10
20
Figure 8. Color with Microlens Angle Response
www.onsemi.com
12
30
KAE−02150
Frame Rates
80
Quad
70
Dual
Single
60
Frames/Sec
50
40
30
20
10
0
10
15
20
25
30
Frequency (MHz)
Figure 9. Frame Rates vs. Frequency
www.onsemi.com
13
35
40
KAE−02150
DEFECT DEFINITIONS
Table 7. DEFECT DEFINITIONS
Description
Threshold/Definition
Maximum Number Allowed
Notes
Major Dark Field Defective Bright Pixel
≥ 10 mV
20
1, 2
Major Bright Field Defective Dark Pixel
≥ 12%
Minor Dark Field Defective Bright Pixel
≥ 5 mV
200
Cluster Defect
A Group of 2 to 10 Contiguous Major Defective
Pixels No Greater than 2 Pixels in Width
8
3
Column Defect
A Group of More than 10 Contiguous Major
Dark Defective Pixels along a Single Column or
10 Contiguous Bright Defective Pixels along
a Single Column
0
3, 4
1. The thresholds are defined for an operating temperature of 0°C, quad output mode, gain of 20X and a readout rate of 20 MHz. For operation
at 22°C, thresholds of 30 mV for major bright pixels and 10 mV for minor bright pixels would give approximately the same numbers of defects.
2. For the color device, a bright field defective pixel deviates by 12% with respect to pixels of the same color.
3. Column and cluster defects are separated by no less than 2 good pixels in any direction (excluding single pixel defects).
4. Low exposure dark column defects are not counted at temperatures above 0°C.
www.onsemi.com
14
KAE−02150
OPERATION
Table 8. ABSOLUTE MAXIMUM RATINGS
(Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the
condition is exceeded, the device will be degraded and may be damaged. Operation at these values will reduce MTTF.)
Symbol
Minimum
Maximum
Units
Notes
Operating Temperature
TOP
−70
40
°C
1
Humidity
RH
5
90
%
2
Output Bias Current
IOUT
−
5
mA
3
CL
−
10
pF
Description
Off-Chip Load
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Noise performance will degrade at higher temperatures.
2. T = 25°C. Excessive humidity will degrade MTTF.
3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during
operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).
Table 9. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND
Minimum
Maximum
Units
Notes
VDD23ab, VDD23cd
Description
−0.4
17.5
V
1
VOUT2, VOUT3
−0.4
15
V
VDD1, VOUT1
−0.4
7.0
V
V1B, V1T
ESD – 0.4
ESD + 22.0
V
V2B, V2T, V3B, V3T, V4B, V4T
ESD – 0.4
ESD + 14.0
V
H1S, H1B, H2S, H2B, H1BEM, H2BEM, H2SL, H2X,
H2SW2, H2SW3, RG1, RG2, RG3
– 0.4
10
V
H1SEM, H2SEM
−0.4
20
V
ESD
−9.0
0.0
V
SUB
6.5
40
V
1
2, 3
1. “a” denotes a, b, c or d.
2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
3. The measured value for VSUBREF is a diode drop higher than the recommended minimum VSUB bias.
Power-Up and Power-Down Sequence
until VDD23ab has been powered, therefore the SUB
voltage cannot be directly derived from the SUBREF pin.
The SUB pin should be at least 4 V before powering up
VDD23ab or VDD23cd.
SUB and ESD power up first, then power up all other
biases in any order. No pin may have a voltage less than ESD
at any time. All HCCD pins must be greater than or equal to
GND at all times. The SUBREF pin will not become valid
Table 10. DC BIAS OPERATING CONDITIONS
Description
Pins
Symbol
Minimum
Nominal
Maximum
Units
Maximum
DC Current
Output Amplifier Return
VSS1
VSS1
−8.3
−8.0
−7.7
V
4 mA
Output Amplifier Supply
VDD1
VDD1
4.5
5.0
6.0
V
15 mA
Output Amplifier Supply
VDD23
VDD23
+14.7
+15.0
+15.3
V
37.0 mA
Ground
GND
GND
0.0
0.0
0.0
V
17.0 mA
Substrate
SUB
VSUB
6.5
VSUBREF
− 0.5
VSUBREF
+ 28
V
Up to 1 mA
(Determined by
Photocurrent)
ESD
ESD
−8.3
−8.0
−7.7
V
0.25 mA
VOUT
IOUT
2.0
2.5
5.0
mA
ESD Protection Disable
Output Bias Current
Notes
1
2
1. VDD bias pins for all four quadrants must be maintained at 15 V during operation.
2. For each image sensor the voltage output on the VSUBREF pin is programmed to be one diode drop, 0.5 V, above the nominal SUB voltage.
The voltage output on VSUBREF is unique to each image sensor and may vary from 6.5 to 10.0 V. The output impedance of VSUBREF is
approximately 100 k. The applied VSUB should be one diode drop lower than the VSUBREF value measured on the device, when VDD23
is at the specified voltage.
www.onsemi.com
15
KAE−02150
AC Operating Conditions
Table 11. CLOCK LEVELS
HCCD and RG
Low Level
Amplitude
Function
Low
Nominal
High
Low
Nominal
High
Reversible HCCD Barrier 2
−0.2
0.0
0.2
3.1
3.3
3.6
H1B(a,b,c,d)
Reversible HCCD Barrier 1
−0.2
0.0
0.2
3.1
3.3
3.6
H2S(a,b,c,d)
Reversible HCCD Storage 2
−0.2
0.0
0.2
3.1
3.3
3.6
H2B(a,b,c,d)
Reversible HCCD Storage 1
−0.2
0.0
0.2
3.1
3.3
3.6
HCCD Switch 2 and 3
−0.2
0.0
0.2
3.1
3.3
3.6
H2L(a,b,c,d)
HCCD Last Gate
−0.2
0.0
0.2
3.1
3.3
3.6
H2X(a,b,c,d)
Floating Gate Exit
−0.2
0.0
0.2
6.0
6.4
6.8
Pin
H2B(a,b,c,d)
H2SW(2,3)(a,b,c,d)
RG1(a,b,c,d)
Floating Gate Reset
Cap
3.1
3.3
3.6
RG(2,3)(a,b,c,d)
Floating Diffusion Reset
Cap
3.1
3.3
3.6
H1BEM(a,b,c,d)
Multiplier Barrier 1
−0.2
0.0
0.2
4.6
5.0
5.4
H2BEM(a,b,c,d)
Multiplier Barrier 2
−0.2
0.0
0.2
4.6
5.0
5.4
H1SEM(a,b,c,d)
Multiplier Storage 1
−0.3
0.0
0.3
7.0
−
18.0
H2SEM(a,b,c,d)
Multiplier Storage 2
−0.3
0.0
0.3
7.0
−
18.0
1. HCCD Operating Voltages. There can be no overshoot on any horizontal clock below −0.4 V: the specified absolute minimum. The H1SEM
and H2SEM clock amplitudes need to be software programmable to adjust the charge multiplier gain.
2. Reset Clock Operation: The RG1, RG2, and RG3 signals must be capacitive coupled into the image sensor with a 0.01 mF to 0.1 mF capacitor.
The reset clock overshoot can be no greater than 0.3 V, as shown in Figure 10, below:
3.1 V Minimum
0.3 V Maximum
Figure 10. RG Clock Overshoot
Clock Capacitances
Pin
Capacitance
(pF)
Pin
Capacitance
(pF)
Pin
Capacitance
(pF)
Pin
Capacitance
(pF)
H1Sa
76
H1Ba
39
H1BEMa
56
H1SEMa
66
H1Sb
76
H1Bb
39
H1BEMb
56
H1SEMb
66
H1Sc
76
H1Bc
39
H1BEMc
56
H1SEMc
66
H1Sd
76
H1Bd
39
H1BEMd
56
H1SEMd
66
H2Sa
76
H2Ba
39
H2BEMa
56
H2SEMa
66
H2Sb
76
H2Bb
39
H2BEMb
56
H2SEMb
66
H2Sc
76
H2Bc
39
H2BEMc
56
H2SEMc
66
H2Sd
76
H2Bd
39
H2BEMd
56
H2SEMd
66
NOTE: The capacitances of all other HCCD pins is 15 pF or less.
www.onsemi.com
16
KAE−02150
High
H1SEMa
H2SEMa
Low
+18 V
High
4 Output
DAC
A
H1SEMb
H2SEMb
Low
B
C
D
High
H1SEMc
H2SEMc
Low
High
H1SEMd
H2SEMd
Low
Figure 11. EMCCD Clock Adjustable Levels
For the EMCCD clocks, each quadrant must have
independently adjustable high levels. All quadrants have
a common low level of GND. The high level adjustments
must be software controlled to balance the gain of the four
outputs.
3.3 V
0 to 75 W
RG1 Clock
Generator
RG1
0.01 to 0.1 mF
3.3 V
0 to 75 W
RG2
RG2,3 Clock
Generator
0.01 to
0.1 mF
RG3
Figure 12. Reset Clock Drivers
vary between 0 and 75 W depending on the layout of the
circuit board.
The reset clock drivers must be coupled by capacitors to
the image sensor. The capacitors can be anywhere in the
range 0.01 to 0.1 mF. The damping resistor values would
www.onsemi.com
17
KAE−02150
Table 12. VCCD
Pin
Low
Nominal
High
V(1,2,3,4)(T,B)
Vertical CCD Clock, Low Level
Function
−8.0
−8.0
−6
V(1,2,3,4)(T,B)
Vertical CCD Clock, Mid Level
−0.2
0
0.2
V(1)(T,B)
Vertical CCD Clock, High (3rd) Level
8.5
9.0
12.5
1. The Vertical CCD operating voltages. The VCCD low level will be −8.0 V for operating temperatures of 0°C and above. Below 0°C the VCCD
low level should be increased for optimum noise performance.
Table 13. BIAS VOLTAGES
Pin
Function
Low
Nominal
High
−8.3
−8.0
−7.7
ESD
ESD
SUB (Notes 1, 2)
Electronic Shutter
VSUBREF + 22
−
VSUBREF + 28
VDD1(a,b,c,d)
Floating Gate Power
4.5
5.0
6.0
VSS1(a,b,c,d)
Floating Gate Return
−8.3
−8.0
−7.7
VDD(2,3)(a,b,c,d)
Floating Diffusion Power
14.7
15.0
15.3
VOUT1(a,b,c,d)
Floating Gate Output Range
−0.5
1.0
2.5
VOUT(2,3)(a,b,c,d)
Floating Diffusion Output Range
8.0
10.0
12.0
1. Caution: Do not clock the EMCCD register while the electronic shutter pulse is high.
2. The substrate bias (SUB) should normally be kept at VAB, which can be read from Pin 60. However, this value was determined from operation
at 0°C, and has an approximate temperature dependence of 0.01 V/degree.
Device Identification
The device identification pin (DevID) may be used to
determine which ON Semiconductor 5.5 micron pixel
interline CCD sensor is being used.
Table 14. DEVICE IDENTIFICATION
Description
Device Identification
Pins
Symbol
Minimum
Nominal
Maximum
Units
Maximum
DC Current
Notes
DevID
DevID
44,000
50,000
56,000
W
0.3 mA
1, 2, 3
1. Nominal value subject to verification and/or change during release of preliminary specifications.
2. If the Device Identification is not used, it may be left disconnected.
3. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent
localized heating of the sensor due to current flow through the R_DeviceID resistor.
Recommended Circuit
V1
DevID
V2
R_External
ADC
R_DeviceID
GND
KAE−02150
Figure 13. Device Identification Recommended Circuit
www.onsemi.com
18
KAE−02150
THEORY OF OPERATION
Image Acquisition
VCCD
VCCD
Photo
Diode
Figure 14. Illustration of 2 Columns and 3 Rows of Pixels
This image sensor is capable of detecting up to
20,000 electrons with a small signal noise floor of 1 electron
all within one image. Each 5.5 mm square pixel, as shown in
Figure 14 above, consists of a light sensitive photodiode and
a portion of the vertical CCD (VCCD). Not shown is
a microlens positioned above each photodiode to focus light
away from the VCCD and into the photodiode. Each photon
incident upon a pixel will generate an electron in the
photodiode with a probability equal to the quantum
efficiency.
The photodiode may be cleared of electrons (electronic
shutter) by pulsing the SUB pin of the image sensor up to
a voltage of 30 V to 40 V (VSUBREF + 22 V to VSUBREF
+ 28 V) for a time of at least 1 ms. When the SUB pin is
above 30 V, the photodiode can hold no electrons, and the
electrons flow downward into the substrate. When the
voltage on SUB drops below 30 V, the integration of
electrons in the photodiode begins. The HCCD clocks
should be stopped when the electronic shutter is pulsed, to
avoid having the large voltage pulse on SUB coupling into
the video outputs and altering the EMCCD gain.
It should be noted that there are certain conditions under
which the device will have no anti-blooming protection:
when the V1T and V1B pins are high, very intense
illumination generating electrons in the photodiode will
flood directly into the VCCD. When the electronic shutter
pulse overlaps the V1T and V1B high-level pulse that
transfers electrons from the photodiode to the VCCD, then
photo-electrons will flow to the substrate and not the VCCD.
This condition may be desirable as a means to obtain very
short integration times.
The VCCD is shielded from light by metal to prevent
detection of more photons. For very bright spots of light,
some photons may leak through or around the metal light
shield and result in electrons being transferred into the
VCCD. This is called image smear.
Image Readout
At the start of image readout, the voltage on the V1T and
V1B pins is pulsed from 0 V up to the high level for at least
1 ms and back to 0 V, which transfers the electrons from the
photodiodes into the VCCD. If the VCCD is not empty, then
the electrons will be added to what is already in the VCCD.
The VCCD is read out one row at a time. During a VCCD
row transfer, the HCCD clocks are stopped. All gates of type
H1 stop at the high level and all gates of type H2 stop at the
low level. After a VCCD row transfer, charge packets of
electrons are advanced one pixel at a time towards the output
amplifiers by each complimentary clock cycle of the H1 and
H2 gates.
The charge multiplier has a maximum charge handling
capacity (after gain) of 20,000 electrons. This is not the
average signal level. It is the maximum signal level.
Therefore, it is advisable to keep the average signal level at
15,000 electrons or less to accommodate a normal
distribution of signal levels. For a charge multiplier gain of
20x, no more than 15,000/20 = 750 electrons should be
allowed to enter the charge multiplier. Overfilling the charge
multiplier beyond 20,000 electrons will shorten its useful
operating lifetime. In addition, sending signals larger than
180–200 electrons into the EMCCD will produce images
with lower signal-to-noise ratio than if they were read out of
the normal floating diffusion output. See Application Note
AND9244.
www.onsemi.com
19
KAE−02150
provided on each quadrant of the image sensor as shown in
Figure 15.
To prevent overfilling the charge multiplier,
a non-destructive floating gate output amplifier (VOUT1) is
To VOUT2
VOUT1
4 Clock Cycles
1 Clock
Cycle
1 Clock Cycle
28 Clock Cycles
SW
10 Clock Cycles
24 Clock Cycles
Empty Pixels
From the Dark
VCCD Columns
FG
Empty Pixels
From the Photo-Active
VCCD Columns
Charge Transfer
2072 Clock Cycles
To the Charge Multiplier
and VOUT3
Figure 15. The Charge Transfer Patch of One Quadrant
The transfer sequence of a charge packet through the
floating gate amplifier is shown in Figure 16 below.
The time steps of this sequence are labeled A through D, and
are indicated in the timing diagram shown as Figure 17.
The RG1 gate is pulse high during the time that the H2X gate
is pulsed high. This holds the floating gate at a constant
voltage so the H2X gate can pull the charge packet out of the
floating gate. The RG1 pulse should be at least as wide as the
H2X pulse. The H2X pulse width should be at least 12 ns.
The rising edge of H2X relative to the falling edge of H1S
is critical. The H2X pulse cannot begin its rising edge
transition until the H1S edge is less than 0.4 V. If the H2X
rising edge comes too soon then there may be some
backwards flow of charge for signals above
10,000 electrons.
The non-destructive floating gate output amplifier is able
to sense how much charge is present in a charge packet
without altering the number of electrons in that charge
packet. This type of amplifier has a low charge-to-voltage
conversion gain (about 6.2 mV/e−) and high noise (about
60 electrons), but it is being used only as a threshold
detector, and not an imaging detector. Even with
60 electrons of noise, it is adequate to determine whether
a charge packet is greater than or less than the recommended
threshold of 180 electrons.
After one row has been transferred from the VCCD into
the HCCD, the HCCD clock cycles should begin. After 10
clock cycles, the first dark VCCD column pixel will arrive
at VOUT1. After another 24 (34 total) clock cycles, the first
photo-active charge packet will arrive at VOUT1.
VDD1
Floating Gate Amp
VREF
H2S
H1S
VOUT1
H2X RG1
OG1
H2L
H1S
A
B
C
Channel
Potential
D
NOTE: The blue and green rectangles represent two separate charge packets. The direction of charge transfer is from right to left.
Figure 16. Charge Packet Transfer Sequence through the Floating Gate Amplifier
www.onsemi.com
20
KAE−02150
A
B
C
D
H1S
50%
10%
90%
H2S
50%
H2X
10%
RG1
VOUT1
Figure 17. Timing Signals that Control the Transfer of Charge through the Floating Gate Amplifier
H2SW3 pins to route the charge packet to the charge
multiplier. This action must take place 28 clock cycles after
the charge packet was under the floating gate amplifier.
The 28 clock cycle delay is to allow for pipeline delays of the
A/D converter inside the analog front end. The timing
generator must examine the output of the analog front end
and dynamically alter the timing on H2SW2 and H2SW3. To
route a charge packet to the charge multiplier (VOUT3),
H2SW2 is held at GND and H2SW3 is clocked with the
same timing as H2S for that one clock cycle. To route
a charge packet to the low gain output amplifier (VOUT2),
H2SW3 is held at GND and H2SW2 is clocked with the
same timing as H2S for that one clock cycle.
The charge packet is transferred under the floating gate on
the falling edge of H2L. When this transfer takes place the
floating gate is not connected to any voltage source.
The presence of charge under the gate causes a change in
voltage on the floating gate according to V = Q / C, where
Q is the size of the charge packet and C is the capacitance of
the floating gate. With an output sensitivity of 6.2 mV/e−,
each electron on the floating gate would give a 6.2 mV
change in VOUT1 voltage. Therefore if the decision
threshold is to only allow charge packets of 180 electrons or
less into the charge multiplier, this would correspond to
180 × 6.2 = 1.1 mV. If the video output is less than 1.1 mV,
then the camera must set the timing of the H2SW2 and
www.onsemi.com
21
KAE−02150
EMCCD OPERATION
H1BEM
H2SEM
H2BEM
H1SEM
H1BEM
H2SEM
H2BEM H1SEM
A
B
C
Channel
Potential
D
NOTE: Charge flows from right to left.
Figure 18. The Charge Multiplication Process
H2SEM are both returned to 0 V at the same time that
H1SEM is ramped up to its maximum voltage. Now the
process can repeat again with charge transferring into the
H1SEM gate.
The alignment of clock edges is shown in Figure 19.
The rising edge of the H1BEM and H2BEM gates must be
delayed until the H1SEM or H2SEM gates have reached
their maximum voltage. The falling edge of H1BEM and
H2BEM must reach 0 V before the H1SEM or H2SEM
reach 0 V. There are a total of 1,800 charge multiplying
transfers through the EMCCD on each quadrant.
The charge multiplication process, shown in Figure 18
above, begins at time step A, when an electron is held under
the H1SEM gate. The H2BEM and H1BEM gates block the
electron from transferring to the next phase until the H2SEM
has reached its maximum voltage. When the H2BEM is
clocked from 0 to 5 V, the channel potential under H2BEM
increases until the electron can transfer from H1SEM to
H2SEM. When the H2SEM gate is above 10 V, the electric
field between the H2BEM and H2SEM gates gives the
electron enough energy to free a second electron which is
collected under H2SEM. Then the voltages on H2BEM and
www.onsemi.com
22
KAE−02150
A
B
C
D
H2S
100%
H2SEM
H2BEM
0%
100%
H1SEM
H1BEM
0%
Figure 19. The Timing Diagram for Charge Multiplication
The amount of gain through the EMCCD will depend on
temperature and H1SEM and H2SEM voltage as shown in
Figure 20. Gain also depends on substrate voltage, as shown
in Figure 21, and on the input signal, as shown in Figure 22.
Gain
100
10
0
12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
EMCCD Voltage
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 20. The Variation of Gain vs. EMCCD High Voltage and Temperature
www.onsemi.com
23
KAE−02150
15.4
T = 0°C
EMCCD Voltage for 20x Gain
15.2
15.0
14.8
14.6
14.4
14.2
6
7
8
9
10
11
12
13
VSUB (V)
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 21. The Change in the Required EMCCD Voltage for a Gain of 20x vs. the Substrate Voltage
22
21
EMCCD Gain
20
19
18
17
16
0
50
100
150
200
250
300
Input Signal (e)
NOTE: The EMCCD voltage was set to provide 20x gain with an input of 180 electrons.
Figure 22. EMCCD Gain vs. Input Signal
unpredictably from one image sensor to the next, as in
Figure 23. Because of this, the gain vs. voltage relationship
must be calibrated for each image sensor, although within
each quadrant, the H1SEM and H2SEM high level voltage
should be equal.
If more than one output is used, then the EMCCD high
level voltage must be independently adjusted for each
quadrant. This is because each quadrant will require
a slightly different voltage to obtain the same gain. In
addition, the voltage required for a given gain differs
www.onsemi.com
24
KAE−02150
Gain
100
10
1
9
10
11
12
13
14
15
H1SEM, H2SEM High Level (V)
Figure 23. An Example Showing How Two Image Sensors Can Have Different Gain vs. Voltage Curves
driver and sensor for a small RC time constant are all that is
needed. However, the pixel array may acquire spurious
charge as a function of VCCD clock driver characteristics.
Also, the VCCD is sensitive to hot electron luminescence
emitted from the output amplifiers during image readout.
These two factors limit the noise floor of the total imaging
array.
The effective output noise of the image sensor is defined
as the noise of the output signal divided by the gain. This is
measured with zero input signal to the EMCCD. Figures 24
and 25 show the EMCCD by itself has a very low noise that
goes as the noise at gain = 1 divided by the gain. The
EMCCD has very little clock-induced charge and does not
require elaborate sinusoidal waveform clock drivers.
Simple square wave clock drivers with a resistor between the
Effective Noise (e)
10
1
0.1
0.01
1
10
100
Gain
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 24. EMCCD Output Noise vs. EMCCD Gain in Single Output Mode at −50 to 225C
www.onsemi.com
25
KAE−02150
Effective Noise (e)
10
1
0.1
0.01
1
10
100
Gain
NOTE: This figure represents data from only one example image sensor, other image sensors will vary.
Figure 25. EMCCD Output Noise vs. EMCCD Gain in Quad Output Mode at −50 to 225C
dark current noise sources when the temperature is below
25°C. Therefore, cooling below 25°C will not provide
a significant improvement to the noise floor. Lower
temperatures will reduce the number of hot pixel defects
observed only during image integration times longer than
1 s. Note the useful plot below:
Because of these pixel array noise sources, it is
recommended that the maximum gain used be 40x at 0°C,
which typically gives a noise floor between 1e and 0.4e.
Using higher gains will provide limited benefit and will
degrade the signal to noise ratio due to the EMCCD excess
noise factor. Furthermore, the image sensor is not limited by
1,000
Gain
100
10
1
13.0
13.5
14.5
14.0
15.0
15.5
EMCCD Voltage
CAUTION:
The EMCCD should not be operated near saturation for an extended period, as this may result in gain aging and
permanently reduce the gain. It should be noted that device degradation associated with gain aging is not covered under
the device warranty.
Figure 26. Gain vs. Voltage with Maximum Recommended Operating Gains Marked
www.onsemi.com
26
KAE−02150
Choosing the Operating Temperature
When operating in quad output mode at 0°C either −6 V
or −8 V may be used for the VCCD clock low level voltage
because the dark signal will be equal. But if the operating
temperature is −20°C then the VCCD clock low level
voltage should be set to −6 V for the lowest VCCD dark
signal. For single output mode, the VCCD clock low level
voltage should be set to −6 V for temperatures of −10°C or
lower and −8 V for temperatures of −10°C or higher.
The reasons for lowering the operating temperature are to
reduce dark current noise and to reduce image defects.
The average dark signal from the VCCD and photodiodes
must be less than 1e in order to have a total system noise less
than 1e when using the EMCCD. Figures 27 and 28 illustrate
how the amount of dark signal in the VCCD is dependent on
both temperature and voltage, and may be used to choose the
operating temperature and VCCD clock low level voltage.
Average Dark Signal (e)
1.0
0.8
0.6
0.4
0.2
0.0
−50
−40
−30
−20
−10
0
10
20
Temperature (5C)
NOTE: Both are for a HCCD frequency of 20 MHz. The VCCD low level voltage is shown for each curve.
Figure 27. Dark Signal from VCCD in Quad and Single Output Modes
Average Dark Signal (e)
1.0
0.8
0.6
0.4
0.2
0.0
−50
−40
−30
−20
−10
0
10
20
Temperature (5C)
Figure 28. Dark Signal from VCCD in Dual Output Mode at HCCD Frequency 20 MHz
The reason for the different temperature dependencies
with the VCCD low level voltage at −6 V vs. −8 V is spurious
charge generation (sometimes called clock-induced charge).
When the VCCD low level is at −8 V, the VCCD is
accumulated with holes, which reduces the rate of dark
current signal generation. However, the amount of clock
induced charge is greater. At VCCD low level of −6 V,
the VCCD is no longer accumulated with holes. So,
clock-induced charge generation is less, but dark current is
increased.
www.onsemi.com
27
KAE−02150
In addition to dark noise, image defects also impact the
optimum operating temperature. Although the average
photodiode dark current is negligible at temperatures below
20°C, as shown by Figure 29, the number of photodiode
hot-pixel defects is a function of temperature and will
decrease with lower temperature.
In quad output mode, the clock induced charge generated
and the dark current signal are equal at T = 0°C. Below
T = 0°C, the dark current signal is smaller than the clock
induced charge, so −6 V is the best voltage. Above T = 0°C,
the dark current signal dominates, and −8 V is the best
voltage. The dark signal stops decreasing below T = −20°C
because the VCCD is detecting hot electron luminescence
from the output amplifiers during image readout.
Average PD Dark Current (e/s)
0.1000
0.0100
0.0010
0.0001
−30
−20
−10
0
10
20
Temperature (5C)
Figure 29. Photodiode Dark Current vs. Temperature
to at least 3 times the floating gate amplifier noise, or 180 e−.
Sending signals larger than 180 e− into the EMCCD will
produce images with lower S/N than if they were read out of
the normal floating diffusion output of VOUT2. See
Application Note AND9244.
Note that the preceding figures are representative data
only, and are not intended as a defect specification.
Choosing the Charge Switch Threshold
The floating gate output amplifier (VOUT1) is used to
decide the routing of a pixel at the charge switch. Pixels with
large signals should be routed to the normal floating
diffusion amplifier at VOUT2. Pixels with small signals
should be routed to the EMCCD and VOUT3. The routing
of pixels is controlled by the timing on H2SW2 and H2SW3.
The optimum signal threshold for that transition between
VOUT2 and VOUT3 is when the signal to noise ratio (S/N)
of VOUT2 is equal to the S/N of VOUT3. This signal is
given by
S + s 2T @
G)1
G
Temperature Diode
There is a diode integrated on the same silicon die as the
image sensor that can be used to assist temperature
regulation. It is not accurate enough to provide a calibrated
temperature value, but it can be used to maintain a constant
temperature.
The temperature is sensed by forward biasing the diode
with 50 mA of current and measuring the resulting voltage
drop. The current value most preferred is 50 mA. It is
recommended that it not be less than 40 mA or more than
60 mA.
The primary source of inaccuracy in temperature
measurement is noise contributed by other clock inputs to
the image sensor. The small amount of coupling of the other
clocks to the temperature diode is rectified by the
temperature diode and causes an offset error in the voltage
reading. The magnitude of the offset error is dependent upon
factors such as the number of outputs used, and the layout of
the camera circuit board. While the error frustrates obtaining
(eq. 1)
where G is the EMCCD gain, S is the signal level, and sT is
the total system noise on VOUT2 in the dark. For values of
G greater than 10, the optimum signal threshold occurs when
then signal equals the square of the total system noise floor
sT. Depending on the skill of the camera designer, sT will
range from 8 to 12 e−. If the camera has a total system noise
of 10 e−, then the threshold should be set to 100 e−. However,
the floating gate amplifier noise is approximately 60 e−, and
so would dominate, making it preferable to set the threshold
www.onsemi.com
28
KAE−02150
an accurate absolute temperature value, it is expected to be
constant and allow the diode to be used for maintaining
a constant temperature.
Figure 30 shows the forward biased voltage drop across
the diode vs. temperature with a current of 50 mA. There are
two curves showing the offset error. One curve shows the
temperature dependence with all image sensor clocks
stopped, and the second with all clocks operating at 20 MHz,
The offset between the clocks-on and clocks-off curves will
be different for every camera design.
−0.55
Diode Voltage (V)
−0.60
−0.65
−0.70
−0.75
−0.80
−0.85
−50
−40
−30
−20
−10
0
10
20
30
40
50
Temperature (5C)
NOTE: The “clocks on” voltage curve will vary significantly from one camera design to the next.
Figure 30. Voltage Drop across Temperature Sensing Diode with Current of 50 mA
www.onsemi.com
29
KAE−02150
TIMING DIAGRAMS
Pixel Timing
50 ns
H2S, H2L
H1S
H2X
RG1
RG2
H2SEM
H2BEM
H1SEM
H1BEM
NOTE: The minimum time for one pixel is 50 ns.
Figure 31. Pixel Timing Pattern P1
www.onsemi.com
30
KAE−02150
Black Clamp, VOUT1, VOUT2, and VOUT3 Alignment
at Line Start
VOUT3 on the same clock cycle and exactly two rows after
they would have arrived at VOUT2.Changing the number of
HCCD clock cycles with introduce an offset between when
pixels arrive at VOUT2 or VOUT3.
When in single mode, each row must have exactly 2,072
HCCD clock cycles. The pixels arrive at VOUT3 on the
same clock cycle and exactly one row after they would have
arrived at VOUT2.Changing the number of HCCD clock
cycles with introduce an offset between when pixels arrive
at VOUT2 or VOUT3.
The black level clamp should start 3 clock cycles into the
line and be active for 28 clock cycles of each row. The first
photoactive pixel will arrive at the VOUT1 (floating gate)
output after 34 clock cycles. The first photoactive pixel will
arrive at either the VOUT2 or VOUT3 after 68 clock cycles,
depending on the timing of H2SW2 and H2SW3.
When in dual or quad output mode, each row must have
exactly 1,036 HCCD clock cycles. The pixels arrive at
Black Clamp
H2L
VOUT1
VOUT2, VOUT3
active pixel 1
68 pixels
34 pixels
active pixel 1
1036 H2L clock cycles
28 pixels
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Time (ms)
Figure 32. Video Output at Each Line Start
H2L, VOUT1, VOUT2, and VOUT3 Alignment at End of
Line
output mode, the pixels arrive at VOUT3 one line delayed
from when they would have arrived at VOUT2. When in
dual or quad output modes, the pixels arrive at VOUT3 two
lines delayed from when they would have arrived at
VOUT2.
The last active pixel (the center column of the image),
arrives at VOUT2 or VOUT3 on the 1,036th clock cycle of
the HCCD. The last photoactive pixel arrives at VOUT1 34
clock cycles before VOUT2 or VOUT3. When in single
H2L
VOUT1
VOUT2, VOUT3
active pixel 968
active pixel 968
34 pixels
H2L clock cycle 1036
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Time (ms)
Figure 33. Video Output at End of Each Line for Dual or Quad Output Modes
www.onsemi.com
31
4.0
KAE−02150
VCCD Timing
Table 15. TIMING DEFINITIONS
Symbol
Minimum
Nominal
Maximum
Units
tVA
VCCD Transfer Time A
0.46
0.50
0.50
ms
tVB
VCCD Transfer Time B
0.46
1.30
7.50
ms
tSUB
Electronic Shutter Pulse
1.0
1.5
10.0
ms
Photodiode to VCCD Transfer Time
1.0
1.5
5.0
ms
t3
Note
V1, V2, V3, V4 Alignment
V1B, V1T
V2B, V4T
V3B, V3T
V4B, V2T
tVA
tVB
tVA
tVB
t3
tVB
tVA
tVB
tVA
tVB
Figure 34. Timing Pattern F1. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD
when Using the Bottom HCCD, Outputs A or B
V1B
V2B, V3T
V3B, V4T
V4B
V1T
V2T
tVA
tVB
tVA
tVB
t3
tVB
tVA
tVB
tVA
tVB
Figure 35. Timing Pattern F2. VCCD Frame Timing to Transfer Charge from Photodiodes to the VCCD
when Using All Four Outputs in Quad Mode
www.onsemi.com
32
KAE−02150
V1B, V1T
V2B, V4T
V3B, V3T
V4B, V2T
tVA
tVB
tVA
tVB
tVA
tVB
tVA
tVB
Figure 36. Line Timing L1. VCCD Line Timing to Transfer One Line of Charge from VCCD to the HCCD
when Using the Bottom HCCD, Outputs A or B in Single or Dual Output Modes
V1B, V2T
V2B, V3T
V3B, V4T
V4B, V1T
tVA
tVB
tVA
tVB
tVA
tVB
tVA
tVB
Figure 37. Line Timing L2. VCCD Line Timing to Transfer One Line of Charge from VCCD to the HCCD
when Using All Four Outputs in Quad Mode
www.onsemi.com
33
KAE−02150
Electronic Shutter
VAB + VES
VSUB
VAB
3.3 V
HCCD
0V
0V
VCCD
−8 V
tVB
tSUB
tVB
Last HCCD
Clock Edge
CAUTION:
First VCCD
Clock Edge
Do not clock the EMCCD register while the electronic shutter pulse is high.
Figure 38. Electronic Shutter Timing Pattern S1
Clock
State
H1S
High
H2S
Low
H2SW
Low
H2L
Low
H2X
Low
H1SEM
High
H1BEM
High
H2SEM
Low
H2BEM
Low
Figure 39. The State of the HCCD and EMCCD Clocks during the Frame, Line,
and Electronic Shutter Timing Sequences
www.onsemi.com
34
KAE−02150
HCCD Timing
To reverse the direction of charge transfer in a Horizontal
CCD, exchange the timing pattern of the H1B and H2B
inputs of that HCCD. If a HCCD is not used, hold all of its
gates at the high level.
When operating in single or dual output modes,
the VDD23cd, VDD1c, and VDD1d amplifiers must still be
powered. The outputs VOUT1, VOUT2, and VOUT3 for
quadrants c and d may be left unloaded.
Table 16. HCCD TIMING
Mode
HCCD a, b Timing
HCCD c, d Timing
Single
H1Ba = H2Bb = H1Sa = H1Sb
H2Ba = H1Bb = H2Sa = H2Sb
3.3 V
Dual
H1Ba = H1Bb = H1Sa = H1Sb
H2Ba = H2Bb = H2Sa = H2Sb
3.3 V
Quad
H1Ba = H1Bb = H1Sa = H1Sb
H2Ba = H2Bb = H2Sa = H2Sb
H1Bc = H1Bd = H1Sc = H1Sd
H2Bc = H2Bd = H2Sc = H2Sd
Image Exposure and Readout
obtain an exposure time equal to the image read out time.
NEXP is the number of lines exposure time and NV is the
number of VCCD clock cycles (row transfers).
The flowchart for image exposure and readout is shown in
Figure 40. The electronic shutter timing may be omitted to
Table 17. IMAGE EXPOSURE AND READOUT
Mode
NH
NV
Line Timing
Frame Timing
Pixel Timing
Single
2,072
1,124
L1
F1
P1
Dual
1,036
562
L1
F1
P1
Quad
1,036
562
L2
F2
P1
Frame Timing
Line Timing
Line Timing
Pixel Timing
Pixel Timing
Repeat NH Times
Repeat NH Times
Repeat NV − NEXP
Times
Repeat NEXP Times
Electronic
Shutter Timing
Figure 40. The Image Readout Timing Flow Chart
www.onsemi.com
35
KAE−02150
Long Integrations and Readout
output SUBV will be invalid. For cameras with long
integration times, the value of SUBV will have to digitized
by and ADC and stored at the time when VDD23 is +15 V.
The SUB pin voltage would be set by a DAC. The HCCD
and EMCCD may be continue to clock during integration.
If they are stopped during integration then the EMCCD
should be re-started at +7 V to flush out any undesired signal
before increasing the voltage to charge multiplying levels.
The timing flow chart for long integration time is shown
in Figure 41.
For extended integrations the output amplifiers need to be
powered down. When powered up, the output amplifiers
emit near infrared light that is sensed by the photodiodes. It
will begin to be visible in images of 30 second integrations
or longer.
To power down the output amplifiers set VDD1 and VSS1
to 0 V, and VDD23 to +5 V. Do not set VDD23 to 0 V during
the integration of an image. During the time the VDD2
supply is reduced to +5 V the substrate voltage reference
Stop All VCCD Clocks at
the VLOW (−8 V) Level.
Pulse the Electronic Shutter on VSUB
to Empty All Photodiodes.
Integration Begins on the Falling Edge
of the Electronic Shutter Pulse.
Set VDD23 = +5.0 V
Set VDD1 = 0.0 V
Set VSS1 = 0.0 V
Wait…
Set VDD23 = +15.0 V
Set VDD1 = +5.0 V
Set VSS1 = −8.0 V
Begin Normal Line Timing
Repeat for at Least 2,048 Lines
in Single or Dual Output Mode,
1,024 Lines in Quad Output
Mode.
Readout the Photodiodes
and One Image.
Figure 41. Timing Flow Chart for Long Integration Time
www.onsemi.com
36
KAE−02150
STORAGE AND HANDLING
Table 18. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−55
80
°C
1
Humidity
RH
5
90
%
2
1. Long-term storage toward the maximum temperature will accelerate color filter degradation.
2. T = 25°C. Excessive humidity will degrade Mean Time to Failure (MTTF).
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
www.onsemi.com
37
KAE−02150
MECHANICAL INFORMATION
PGA Completed Assembly
Notes:
1. Substrate is a 141-pin ceramic PGA package.
2. Body is black alumina.
3. Pins are Kovar or equivalent, plated with 1.00 microns of gold over 2.00 microns of nickel.
4. Wire is wedge bonded aluminum (1% Si).
5. Ablebond 967−1 epoxy for die attach.
6. No materials to obstruct the clearance through the package holes.
7. Exposed metal is 1.00 micron minimum gold over 2.00 micron minimum nickel.
8. Glass lid is Schott E263Teco, nD 1.5231. Thickness 0.76 ± 0.05 mm.
9. Recommended mounting screws: 1.6 × 0.35 mm (ISO standard), 0−80 (unified fine thread standard).
Figure 42. Completed Assembly (1/2)
www.onsemi.com
38
KAE−02150
Notes:
1. Die is standard thickness for 150 mm silicon wafer: 0.675 ± 0.020 mm.
2. Singulated die is approximately 12.910 × 8.500 mm, for a 50 micron saw kerf.
3. The optical center of the image area is at the center of the die and the center of the package.
Figure 43. Completed Assembly (2/2)
www.onsemi.com
39
KAE−02150
PGA Clear Cover Glass
Notes:
1. Dust and Scratch: 10 micron maximum (“A” zone)
2. Glass Material: Schott D263T eco
Figure 44. PGA Clear Cover Glass
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
40
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
KAE−02150/D