KAI 1010 D

KAI-1010
1008 (H) x 1018 (V) Interline
CCD Image Sensor
Description
The KAI−1010 Image Sensor is a high-resolution monochrome
charge coupled device (CCD) device whose non-interlaced
architecture makes it ideally suited for video, electronic still and
motion/still camera applications. The device is built using an
advanced true two-phase, double-polysilicon, NMOS CCD
technology. The p+npn− photodetector elements eliminate image lag
and reduce image smear while providing antiblooming protection and
electronic-exposure control. The total chip size is 10.15 (H) mm ×
10.00 (V) mm
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CCD, Non-Interlaced
Total Number of Pixels
1024 (H) × 1024 (V)
Number of Effective Pixels
1008 (H) × 1018 (V)
Number of Active Pixels
1008 (H) × 1018 (V)
Number of Outputs
1 or 2
Pixel Size
9 mm (H) × 9 mm (V)
Active Image Size
9.1 mm (H) × 9.2 mm (V)
12.9 mm (Diagonal)
1″ Optical Format
Optical Fill-Factor
60%
Saturation Signal
> 50,000 e−
Output Sensitivity
12 mV/e−
Dark Noise
50 e− rms
Dark Current
< 0.5 nA/cm2
•
•
•
•
•
•
•
•
•
Quantum Efficiency
(Wavelength = 500 nm)
37%
Application
Blooming Suppression
> 100 X
• Machine Vision
Maximum Data Rate
20 MHz/Channel (2 Channels)
Image Lag
Negligible
Package
CERDIP
Cover Glass
AR Coated (Both Sides)
Figure 1. KAI−1010 Interline
CCD Image Sensor
Features
Front Illuminated Interline Architecture
Progressive Scan (Non-Interlaced)
Electronic Shutter
On-Chip Dark Reference
Low Dark Current
High Sensitivity Output Structure
Anti-Blooming Protection
Negligible Lag
Low Smear (0.1% with Microlens)
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 2
1
Publication Order Number:
KAI−1010/D
KAI−1010
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−1010 Image Sensor
Part Number
Description
KAI−1010−ABA−CD−AE
Monochrome, Telemetric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1010−ABA−CD−BA
Monochrome, Telemetric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Standard Grade
KAI−1010−ABA−CR−AE
Monochrome, Telemetric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample
KAI−1010−ABA−CR−BA
Monochrome, Telemetric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade
Marking Code
KAI−1010M
Serial Number
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−1010
DEVICE DESCRIPTION
Architecture
4 Dark Lines at Bottom of Image
fV2
fV2
KAI−1010
Active Image Area
1008 (H) × 1018 (V)
9.0 mm × 9.0 mm Pixels
VRD
fR
10 Dark Columns
fV1
6 Dark Columns
fV1
2 Dark Lines at Top of Imate
VDD
VSS/OG
H1A
Horizontal Register A
VOUTA
H2
2 Dummies
6 Dummies
VDD
Horizontal Register B
VOUTB
H1B
VSS/OG
WELL
VSUB
Figure 2. Functional Block Diagram
The KAI−1010 consists of 1024 × 1024 photodiodes,
1024 vertical (parallel) CCD shift registers (VCCDs), and
dual 1032 pixel horizontal (serial) CCD shift registers
(HCCDs) with independent output structures. The device
can be operated in either single or dual line mode. The
advanced, progressive-scan architecture of the device
allows the entire image area to be read out in a single scan.
The active pixels are arranged in a 1008 (H) × 1018 (V) array
with an additional 16 columns and 6 rows of light-shielded
dark reference pixels.
Charge Transport
The accumulated or integrated charge from each
photodiode is transported to the output by a three step
process. The charge is first transported from the photodiodes
to the VCCDs by applying a large positive voltage to the
phase-one vertical clock (fV1). This reads out every row, or
line, of photodiodes into the VCCDs.
The charge is then transported from the VCCDs to the
HCCDs line by line. Finally, the HCCDs transport these
rows of charge packets to the output structures pixel by
pixel. On each falling edge of the horizontal clock, fH2,
these charge packets are dumped over the output gate (OG,
Figure 4) onto the floating diffusion (FDA and FDB,
Figure 4).
Both the horizontal and vertical shift registers use
traditional two-phase complementary clocking for charge
transport. Transfer to the HCCDs begins when fV2 is
clocked high and then low (while holding fH1A high)
causing charge to be transferred from fV1 to fV2 and
subsequently into the A HCCD. The A register can now be
read out in single line mode. If it is desired to operate the
device in a dual line readout mode for higher frame rates, this
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent on light level
and exposure time and non-linearly dependent on
wavelength. When the photodiode’s charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
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3
KAI−1010
line is transferred into the B HCCD by clocking fH1A to
a low state, and fH1B to a high state while holding fH2 low.
After fH1A is returned to a high state, the next line can be
transferred into the A HCCD. After this clocking sequence,
both HCCDs are read out in parallel.
The charge capacity of the horizontal CCDs is slightly
more than twice that of the vertical CCDs. This feature
allows the user to perform two-to-one line aggregation in the
charge domain during V-to-H transfer. This device is also
equipped with a fast dump feature that allows the user to
selectively dump complete lines (or rows) of pixels at a time.
This dump, or line clear, is also accomplished during the
V-to-H transfer time by clocking the fast dump gate.
Pixel PN
−V
Pixel PN+1
+V
−V
f
+V
Q2
Q1
Direction of Transfer
Figure 3. True 2 Phase CCD Cross Section
fR
RD
VDD
VOUTA
FDA (N/C)
HCCDA
VSS & OG
HCCDB
FDB (N/C)
VOUTB
VWELL
Figure 4. Output Structure
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4
VSUB
KAI−1010
Output Structure
After returning the substrate voltage to the nominal value,
charge can accumulate in the diodes and the charge packet
is subsequently readout onto the VCCD at the next
occurrence of the high level on fV1. The integration time is
then the time between the falling edges of the substrate
shutter pulse and fV1. This scheme allows electronic
variation of the exposure time by a variation in the clock
timing while maintaining a standard video frame rate.
Application of the large shutter pulse must be avoided
during the horizontal register readout or an image artifact
will appear due to feedfthrough. The shutter pulse VES
must be “hidden” in the horizontal retrace interval.
The integration time is changed by skipping the shutter
pulse from one horizontal retrace interval to another.
The smear specification is not met under electronic shutter
operation. Under constant light intensity and spot size, if the
electronic exposure time is decreased, the smear signal will
remain the same while the image signal will decrease
linearly with exposure. Smear is quoted as a percentage of
the image signal and so the percent smear will increase by
the same factor that the integration time has decreased. This
effect is basic to interline devices.
Extremely bright light can potentially harm solid state
imagers such as Charge-Coupled Devices (CCDs). Refer to
Application Note Using Interline CCD Image Sensors in
High Intensity Visible Lighting Conditions.
Charge packets contained in the horizontal register are
dumped pixel by pixel, onto the floating diffusion output
node whose potential varies linearly with the quantity of
charge in each packet. The amount of potential change is
determined by the expression DVFD = DQ / CFD. A three
stage source-follower amplifier is used to buffer this signal
voltage off chip with slightly less than unity gain. The
translation from the charge domain to the voltage domain is
quantified by the output sensitivity or charge to voltage
conversion in terms of mV/e−. After the signal has been
sampled off-chip, the reset clock (fR) removes the charge
from the floating diffusion and resets its potential to the
reset-drain voltage (VRD).
Electronic Shutter
The KAI−1010 provides a structure for the prevention of
blooming which may be used to realize a variable exposure
time as well as performing the anti-blooming function. The
anti-blooming function limits the charge capacity of the
photodiode by draining excess electrons vertically into the
substrate (hence the name Vertical Overflow Drain or
VOD). This function is controlled by applying a large
potential to the device substrate (device terminal SUB). If
a sufficiently large voltage pulse (VES ≈ 40 V) is applied to
the substrate, all photodiodes will be emptied of charge
through the substrate, beginning the integration period.
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KAI−1010
Physical Description
Pin Description and Device Orientation
1
24 fV1R
fV1L 2
23 fV2R
fV2L 3
22 WELL
SUB 4
21 GND
GND
5
20 GND
FDG
6
19 IDHA
VDD
7
18 IDHB
VOUTA 8
17 fH1A
GND
VSS 9
16 GND
Pixel 1, 1
fR
10
15 fH1B
VDR
11
14 GND
13 fH2
VOUTB 12
Figure 5. Pinout Diagram
Table 3. PIN DESCRIPTION
Pin
Name
Pin
Description
Name
Description
1
GND
Ground
13
fH2
A & B Horizontal CCD Clock − Phase 2
2
fV1L
Vertical CCD Clock − Phase 1
14
GND
Ground
3
fV2L
Vertical CCD Clock − Phase 2
15
fH1B
B Horizontal CCD Clock − Phase 1
4
SUB
Substrate
16
GND
Ground
fH1A
A Horizontal CCD Clock − Phase 1
5
GND
Ground
17
6
FDG
Fast Dump Gate
18
IDHB
Input Diode B Horizontal CCD
IDHA
Input Diode B Horizontal CCD
7
VDD
Output Amplifier Supply
19
8
VOUTA
Video Output Channel A
20
GND
Ground
Output Amplifier Return & OG
21
GND
Ground
9
VSS
10
fR
Reset Clock
22
WELL
P-Well
11
VDR
Reset Drain
23
fV2R
Vertical CCD Clock − Phase 2
12
VOUTB
Video Output Channel B
24
fV1R
Vertical CCD Clock − Phase 1
1. All GND pins should be connected to WELL (P-Well).
2. Pins 2 and 24 must be connected together − only 1 Phase 1 clock driver is required.
3. Pins 3 and 23 must be connected together − only 1 Phase 2 clock driver is required.
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KAI−1010
IMAGING PERFORMANCE
All the following values were derived using nominal
operating conditions using the recommended timing. Unless
otherwise stated, readout time = 140 ms, integration time =
140 ms and sensor temperature = 40°C. Correlated double
sampling of the output is assumed and recommended. Many
units are expressed in electrons, to convert to voltage,
multiply by the amplifier sensitivity.
Defects are excluded from the following tests and the
signal output is referenced to the dark pixels at the end of
each line unless otherwise specified.
Table 4. ELECTRO-OPTICAL IMAGE SPECIFICATIONS KAI−1010−ABA
Parameter
Symbol
Min.
Optical Fill Factor
Nom.
Max.
Unit
Notes
FF
−
55.0
−
%
ESAT
−
0.037
−
mJ/cm2
1
QE
−
37
−
%
2
Photoresponse Non-Uniformity
PRNU
−
10.0
−
% pp
3, 4
Photoresponse Non-Linearity
PRNL
−
5.0
−
%
Saturation Exposure
Peak Quantum Efficiency
1.
2.
3.
4.
For l = 550 nm wavelength, and VSAT = 350 mV.
Refer to typical values from Figure 6.
Under uniform illumination with output signal equal to 280 mV.
Units: % Peak to Peak. A 200 by 200 sub ROI is used.
Monochrome with Microlens Quantum Efficiency
0.4
0.35
Absolute Quantum Efficiency
0.3
0.25
0.2
0.15
0.1
0.05
0
400
450
500
550
600
650
700
750
800
850
Wavelength (nm)
Figure 6. Nominal KAI−1010−ABA Spectral Response
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7
900
950
1000
KAI−1010
Angular Quantum Efficiency
110
100
Quantum Efficiency (percent relative to normal incidence)
Vertical
90
80
70
60
50
Horizontal
40
30
20
10
0
0
5
10
15
20
Angle from Normal Incidence (degrees)
Notes:
1. For the curve marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
2. For the curve marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Figure 7. Angular Dependance of Quantum Efficiency
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25
30
KAI−1010
Frame Rates
KAI−1010 Frame Rate vs. Horizontal Clock Frequency
60
50
Frame Rate (Frames per Second)
Dual Channel
Estimated
40
30
Dual Channel
20
Single Channel
Estimated
10
Single Channel
0
0
5
10
15
20
25
30
Horizontal Clock Frequency (MHz)
Figure 8. Frame Rate vs. Horizontal Clock Frequency
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35
40
KAI−1010
CCD Image Specifications
Table 5. CCD IMAGE SPECIFICATIONS
Parameter
Symbol
Min.
Nom.
VSAT
−
ID
−
DCDT
Charge Transfer Efficiency
Horizontal CCD Frequency
Output Saturation Voltage
Dark Current
Dark Current Doubling Temp
Image Lag
Max.
Unit
Notes
350
−
mV
1, 2, 8
−
0.5
nA
7
8
10
°C
CTE
−
0.99999
−
fH
−
−
40
MHz
4
−
100
e−
5
IL
−
Blooming Margin
XAB
−
−
100
Vertical Smear
Smr
−
0.01
−
2, 3
6, 8
%
7
1.
2.
3.
4.
5.
VSAT is the green pixel mean value at saturation as measured at the output of the device with XAB = 1. VSAT can be varied by adjusting VSUB.
Measured at sensor output.
With stray output load capacitance of CL = 10 pF between the output and AC ground.
Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
This is the first field decay lag measured by strobe illuminating the device at (HSAT, VSAT), and by then measuring the subsequent frame’s
average pixel output in the dark.
6. XAB represents the increase above the saturation-irradiance level (HSAT) that the device can be exposed to before blooming of the vertical
shift register will occur. It should also be noted that VOUT rises above VSAT for irradiance levels above HSAT, as shown in Figure 9.
7. Measured under 10% (~ 100 lines) image height illumination with white light source and without electronic shutter operation and below VSAT.
8. It should be noted that there is tradeoff between XAB and VSAT.
Output Amplifier @ VDD = 15 V, VSS = 0.0 V
Table 6. OUTPUT AMPLIFIER IMAGE SPECIFICATIONS
Parameter
Output DC Offset
Power Dissipation
Output Amplifier Bandwidth
Off-Chip Load
1.
2.
3.
4.
Symbol
Min.
Nom.
Max.
Unit
Notes
VODC
−
7
−
V
1, 2
PD
−
225
−
mW
3
f−3dB
−
140
−
MHz
1, 4
CL
−
−
10
pF
Measured at sensor output with constant current load of IOUT = 5 mA per output.
Measured with VRD = 9 V during the floating-diffusion reset interval, (fR high), at the sensor output terminals.
Both channels.
With stray output load capacitance of CL = 10 pF between the output and AC ground.
General
Table 7. GENERAL IMAGE SPECIFICATIONS
Parameter
Total Sensor Noise
Dynamic Range
Symbol
Min.
Nom.
Max.
Unit
Notes
VN−TOTAL
−
0.5
−
mV rms
1
DR
−
7
60
dB
2
1. Includes amplifier noise and dark current shot noise at data rates of 10 MHz. The number is based on the full bandwidth of the amplifier. It
can be reduced when a low pass filter is used.
2. Uses 20LOG (VSAT / VN−TOTAL) where VSAT refers to the output saturation signal.
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KAI−1010
400
350
Output Signal − VOUT − (mV)
300
(HSAT, VSAT)
250
200
150
100
50
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Sensor Plane Irradiance − H − (arb)
Figure 9. Typical KAI−1010−ABA Photoresponse
600
VSUB = 8 V
500
Output Signal − VOUT − (mV)
VSUB = 9 V
VSUB = 10 V
400
VSUB = 11 V
300
VSUB = 12 V
VSUB = 13 V
200
VSUB = 14 V
VSUB = 15 V
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Sensor Plane Irradiance − H − (arb)
Notes:
1. As VSUB is decreased, VSAT increases and anti-blooming protection decreases.
2. As VSUB is increased, VSAT decreases and anti-blooming protection increases.
Figure 10. Example of VSAT vs. VSUB
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11
0.9
KAI−1010
DEFECT DEFINITIONS
All values are derived under normal operating conditions at 40°C operating temperature.
Table 8. DEFECT DEFINITIONS
Defect Type
Defect Definition
Number Allowed
Notes
Defective Pixel
Under uniform illumination with mean pixel output at 80% of VSAT,
a defective pixel deviates by more than 15% from the mean value of
all pixels in its section.
12
1
Bright Defect
Under dark field conditions, a bright defect deviates more than 15 mV
from the mean value of all pixels in its section.
5
1
Cluster Defect
Two or more vertically or horizontally adjacent defective pixels.
0
1008,1
756,1
504,1
252,1
1,1
1. Sections are 252 (H) × 255 (V) pixel groups, which divide the imager into sixteen equal areas as shown below.
1,1
1008,1
1008,765
1,1018
1008,1018
1008,1018
1,765
756,1018
1008,510
504,1018
1,510
252,1018
1008,255
1,1018
1,255
Figure 11.
Table 9.
Test Conditions
Value
Junction Temperature
(TJ) = 40°C
Integration Time
(tINT) = 70 ms
Readout Rate
(tREADOUT) = 70 ms
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KAI−1010
OPERATION
Table 10. ABSOLUTE MAXIMUM RATINGS
Rating
Description
Min.
Max.
Unit
Notes
Temperature
(@ 10% ±5%RH)
Operation Without Damage
−50
+70
°C
5, 6
Voltage
(Between Pins)
SUB−WELL
0
+40
V
1, 7
VRD, VDD, OG & VSS − WELL
0
+15
V
2
IDHA,B & VOUTA,B − WELL
0
+15
V
2
fV1 − fV2
−12
+20
V
2
fH1A, fH1B − fH2
−12
+15
V
2
fH1A, fH1B, fH2, FDG − fV2
−12
+15
V
2
fH2 − OG & VSS
−12
+15
V
2
fR – SUB
−20
0
V
1, 2, 4
All Clocks − WELL
−12
+15
V
2
Output Bias Current (IOUT)
−
10
mA
3
Current
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Under normal operating conditions the substrate voltage should be above +7 V, but may be pulsed to 40 V for electronic shuttering.
2. Care must be taken in handling so as not to create static discharge which may permanently damage the device.
3. Per Output. IOUT affects the band-width of the outputs.
4. fR should never be more positive than VSUB.
5. The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy.
6. The image sensor shall continue to function but not necessarily meet the specifications of this document while operating at the specified
conditions.
7. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Table 11. DC OPERATING CONDITIONS
Description
Symbol
Min.
Nom.
Max.
Unit
Pin Impedance (Note 6)
Reset Drain
VRD
Reset Drain Current
IRD
8.5
9
−
0.2
Output Amplifier Return & OG
VSS
−
Output Amplifier Return Current
ISS
Output Amplifier Supply
Output Bias Current
9.5
V
5 pF, > 1.2 MW
−
mA
0
−
V
−
5
−
mA
VDD
12
15.0
15.0
V
IOUT
−
5
10
mA
P-Well
WELL
−
0.0
−
V
Ground
GND
−
0.0
−
V
Fast Dump Gate
FDG
−7.0
−6.0
−5.5
V
20 pF, > 1.2 MW
2
Substrate
SUB
7
VSUB
15
V
1 nF, > 1.2 MW
3, 8
IDHA,
IDHB
12.0
15.0
15.0
V
5 pF, > 1.2 MW
4
Input Diode A, B Horizontal CCD
1.
2.
3.
4.
5.
6.
7.
Notes
30 pF, > 1.2 MW
30 pF, > 1.2 MW
5
Common
1
1
The WELL and GND pins should be connected to P-Well ground.
The voltage level specified will disable the fast dump feature.
This pin may be pulsed to VES = 40 V for electronic shuttering
Electrical injection test pins. Connect to VDD power supply.
Per output. Note also that IOUT affects the bandwidth of the outputs.
Pins shown with impedances greater than 1.2 MW are expected resistances. These pins are only verified to 1.2 MW.
The operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments of these
voltages.
8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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13
KAI−1010
+15 V
0.1 mF
5 mA
2N3904
or Equivalent
VOUT
Buffered Output
140 W
1 kW
Figure 12. Recommended Output Structure Load Diagram
Table 12. AC CLOCK LEVEL CONDITIONS
Description
Vertical CCD Clock
Vertical CCD Clock
Symbol
Level
Min.
Nom.
Max.
Unit
Pin Impedance
(Note 2)
fV1
Low
−10.0
−9.5
−9.0
V
25 nF, > 1.2 MW
Mid
0.0
0.2
0.4
High
8.5
9.0
9.5
Low
−10.0
−9.5
−9.0
V
25 nF, > 1.2 MW
High
0.0
0.2
0.4
Low
−7.5
−7.0
−6.5
V
100 pF, > 1.2 MW
fV2
f1 Horizontal CCD A Clock
fH1A
High
2.5
3.0
3.5
f1 Horizontal CCD B Clock
(Single Register Mode)
(Note 4)
fH1B
Low
−7.5
−7.0
−6.5
V
100 pF, > 1.2 MW
f1 Horizontal CCD B Clock
(Dual Register Mode)
(Note 4)
fH1B
Low
−7.5
−7.0
−6.5
V
100 pF, > 1.2 MW
High
2.5
3.0
3.5
Low
−7.5
−7.0
−6.5
V
125 pF, > 1.2 MW
High
2.5
3.0
3.5
Low
−6.5
−6.0
−5.5
V
5 pF, > 1.2 MW
High
−0.5
0.0
0.5
Low
−7.0
−6.0
−5.5
V
20 pF, > 1.2 MW
High
4.5
5.0
5.5
f2 Horizontal CCD Clock
Reset Clock
Fast Dump Gate Clock
(Note 3)
fH2
fR
fFDG
1. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments
of these voltages.
2. Pins shown with impedances greater than 1.2 MW are expected resistances. These pins are only verified to 1.2 MW.
3. When not used, refer to DC operating condition.
4. For single register mode, set fH1B to −7.0 V at all times rather than clocking it.
5. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult ON Semiconductor in
those situations in which operating conditions meet or exceed minimum or maximum levels.
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KAI−1010
Table 13. AC TIMING REQUIREMENTS FOR 20 MHZ OPERATION
Symbol
Min.
Nom.
Max.
Unit
Figure
Reset Pulse Width
Description
tfR
−
10
−
ns
Figure 12
Electronic Shutter Pulse Width
tES
10
25
−
ms
Figure 13
Integration Time (Note 1)
tINT
0.1
−
ms
Figure 13
Photodiode to VCCD Transfer Pulse Width (Note 2)
tfVH
4
5
−
ms
Figure 9
Clamp Delay
tCD
−
15
−
ns
Figure 12
Clamp Pulse Width
tCP
−
15
−
ns
Figure 12
Sample Delay
tSD
−
35
−
ns
Figure 12
Sample Pulse Width
tSP
−
15
−
ns
Figure 12
Vertical Readout Delay
tRD
10
−
−
ms
Figure 9
fV1, fV2 Pulse Width
tfV
3
−
−
ms
Figure 10
Clock Frequency fH1A, fH1B, fH2
tfH
−
20
−
MHz
Figure 12
Line A to Line B Transfer Pulse Width
tfAB
−
3
−
ms
Figure 15
Horizontal Delay
tfHD
3
−
−
ms
Figure 10
Vertical Delay
tfVD
25
−
−
ns
Figure 10
tfHVES
1
−
−
ms
Figure 13
Horizontal Delay with Electronic Shutter
1. Integration time varies with shutter speed. It is to be noted that smear increases when integration time decreases below readout time (frame
time). Photodiode dark current increases when integration time increases, while CCD dark current increases with readout time (frame time).
2. Anti-blooming function is off during photodiode to VCCD transfer.
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15
KAI−1010
TIMING
Frame Timing − Single Register Readout
1 Frame = 1024 Lines
Frame Time
fV1
2
1
0
1023
1022
1021
1020
1019
1018
4
3
2
1
0
1023
1022
fV2
tRD
tfVH
fV1
fV2
1021
1023
1022
0
NOTE: When no electronic shutter is used, the integration time is equal to the frame time.
Figure 13. Frame Timing − Single Resistor Readout
Line Timing − Single Register Readout
fV1
tfV
tfHD
fV2
fH1A
tfVD
fH1B
fH2
fR
H1B held low or single register operation.
Empty Shift Register Phases
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
Line Content
Dark Reference Pixels
Photoactive Pixels
Figure 14. Frame Timing − Single Resistor Readout
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16
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17
Video after
Double
Correlated
Sampling
(Inverted)
SAMPLE
CLAMP
VOUTA
fR
fH1A
fH2
Reference
tfR
tSD
tCD
tCP
1 Count = 1 Pixel
tSP
Signal
Reference
Signal
tfH = 50 ns min
KAI−1010
Pixel Timing − Single Register Readout
Figure 15. Pixel Timing − Single Resistor Readout
KAI−1010
Electronic Shutter Timing − Single Register Readout
Electronic Shutter − Frame Timing
fV1
fV2
Integration Time tINT
VES
(SUB)
Electronic Shutter − Placement
fV1
fV2
fH1A
fH2
tfHMES
VES
(SUB)
tES
Electronic Shutter − Operating Voltages
VES
VES
(SUB)
VSUB
Reference
Figure 16. Electronic Shutter Timing − Single Register Readout
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18
KAI−1010
Frame Timing − Dual Register Readout
1 Frame = 512 Line Pairs
Frame Time
fV1
4,5
2,3
0,1
1022,1023
1020,1021
1018,1019
1016,1017
1014,1015
1012,1013
8,9
6,7
4,5
2,3
0,1
1022,1023
1020,1021
fV2
tRD
tfVH
fV1
1018,1019
fV2
1020,1021
1022,1023
0,1
NOTE: When no electronic shutter is used, the integration time is equal to the frame time.
Figure 17. Frame Timing − Dual Resistor Readout
Line Timing − Dual Register Readout
tfV
tfV
tfVD
fV1
tfV
tfHD
fV2
fH1A
tfA/B
fH1B
fH2
fR
Empty Shift Register Phases
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
Line Content
Dark Reference Pixels
Photoactive Pixels
Figure 18. Line Timing − Dual Resistor Readout
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19
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20
Figure 19. Pixel Timing − Dual Resistor Readout
Video after
Double
Correlated
Sampling
(Inverted)
SAMPLE
CLAMP
VOUTA
fR
fH2
fH1B
fH1A
Reference
tfR
tSD
tCD
tCP
1 Count = 1 Pixel
tSP
Signal
Reference
Signal
tfH = 50 ns min
KAI−1010
Pixel Timing − Dual Register Readout
KAI−1010
Fast Dump Timing − Removing Four Lines
fV1
fV2
FDG
fH1A
fH1B
fH2
Dumped Line #4
Dumped Line #3
Dumped Line #2
Dumped Line #1
End of a Valid Line
fR
Valid Line
fV2
Valid Line
fV2
Min 0.5 ms
Min 0.5 ms
FDG
FDG
Fast Dump Rising Edge wrt V2
Falling Edge
Fast Dump Falling Edge wrt V2
Falling Edge
fV2
Max 0.1 ms
FDG
Fast Dump Falling Edge wrt V2
Rising Edge
Figure 20. Fast Dump Timing − Removing Four Lines
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21
KAI−1010
Binning − Two to One Line Binning
fV1
fV2
fH1A
fH1B
fH2
fR
tfVD
tfV
tfHD
Figure 21. Binning − 2 to 1 Line Binning
Timing − Sample Video Waveform
VOUTA
H1A
H2
Figure 22. Sample Video Waveform at 5 MHz
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22
KAI−1010
STORAGE AND HANDLING
Table 14. CLIMATIC REQUIREMENTS
Operation to Specification
Storage
Description
Min.
Max.
Unit
Conditions
Notes
Temperature
−25
40
°C
@ 10% ±5% RH
1, 2
Humidity
10
86
% RH
@ 36±2°C Temp.
1, 2
Temperature
−55
70
°C
@ 10% ±5% RH
2, 3
Humidity
−
95
% RH
@ 49±2°C Temp.
2, 3
1. The image sensor shall meet the specifications of this document while operating at these conditions.
2. The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy.
3. The image sensor shall meet the specifications of this document after storage for 15 days at the specified condition.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
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23
KAI−1010
MECHANICAL INFORMATION
Completed Assembly
Note: Cover Glass is manually placed and visually aligned over die – location accuracy is not guaranteed.
Figure 23. Completed Assembly (1 of 2)
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24
KAI−1010
Notes:
1. Center of image area is offset from center of package by (−0.02, −0.06) mm nominal.
2. Die is aligned within ±2 degree of any package cavity edge.
Figure 24. Completed Assembly (2 of 2)
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25
KAI−1010
Cover Glass
Notes:
1. DUST/SCRATCH COUNT – 20 MICRON MAX. (ZONE−A)
2. EPOXY: NCO−110SZ
THICKNESS: 0.002–0.007″
3. GLASS: SCHOTT D263 eco or equivalent
4. DOUBLE−SIDED AR COATING REFLECTANCE
a. 420–435 nm < 2.0 %
b. 435–630 nm < 0.8 %
c. 630–680 nm < 2.0 %
Figure 25. Glass Drawing
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26
KAI−1010
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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27
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
KAI−1010/D