KAF 1001 D

KAF-1001
1024 (H) x 1024 (V) Full
Frame CCD Image Sensor
Description
T h e K A F −1 0 0 1 I m a g e S e n s o r i s a h i g h - p e r f o r m a n c e
charge-coupled device (CCD) designed for a wide range of image
sensing applications.
The sensor incorporates true two-phase CCD technology,
simplifying the support circuits required to drive the sensor as well as
reducing dark current without compromising charge capacity.
The sensor also utilizes the TRUESENSE Transparent Gate Electrode
to improve sensitivity compared to the use of a standard front side
illuminated polysilicon electrode.
Selectable on-chip output amplifiers allow operation to be
optimized for different imaging needs: Low Noise (when using the
high-sensitivity output) or Maximum Dynamic Range (when using the
low-sensitivity output).
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Table 1. GENERAL SPECIFICATIONS
Parameter
Figure 1. KAF−1001 CCD Image Sensor
Typical Value
Architecture
Full Frame CCD
Pixel Count
1024 (H) × 1024 (V)
Features
Pixel Size
24 mm (H) × 24 mm (V)
Active Image Size
24.6 mm (H) × 24.6 mm (V)
34.8 mm (Diagonal)
APS−H Optical Format
• True Two Phase Full Frame Architecture
• TRUESENSE Transparent Gate Electrode
Chip Size
28.6 mm (H) × 25.5 mm (V)
Optical Fill-Factor
100%
Saturation Signal
High Sensitivity Output
High Dynamic Range
240,000 electrons
650,000 electrons
Output Sensitivity
High Sensitivity Output
High Dynamic Range
11 mV/electron
2 mV/electron
Readout Noise (1 MHz)
15 electrons rms
Dark Current
(25°C, Accumulation Mode)
< 30 pA/cm2
Dark Current Doubling Rate
5−6°C
Dynamic Range (Sat Sig/Dar Noise)
High Sensitivity Output
High Dynamic Range
Quantum Efficiency
(450, 550, 650 nm)
•
•
•
•
for High Sensitivity
100% Fill Factor
Low Dark Current
Single Readout Register
User-selectable Outputs Allow either Low
Noise or High Dynamic Range Operation
Applications
• Scientific
• Medical
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
83 dB
97 dB
40%, 55%, 65%
Maximum Data Rate
High Sensitivity Output
High Dynamic Range
5 MHz
2 MHz
Transfer Efficiency (2 MHz, to −40°C)
> 0.99997
Package
CERDIP Package (Sidebrazed)
Cover Glass
Clear
NOTE: Parameters above are specified at T = 25°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 2
1
Publication Order Number:
KAF−1001/D
KAF−1001
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAF−1001 IMAGE SENSOR
Part Number
Description
Marking Code
KAF−1001−AAA−CP−B1
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Grade 1
KAF−1001−AAA−CP−B2
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Grade 2
KAF−1001−AAA−CP−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Sample
KAF−1001−AAA−CB−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Sample
KAF−1001−AAA−CB−B2
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Grade 2
KAF−1001−AAA
Serial Number
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KEK−4H0080−KAF−1001−12−5
Description
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAF−1001
DEVICE DESCRIPTION
Architecture
4 Dark Lines
fV1
KAF−1001
Usable Active Image Area
1024 (H) × 1024 (V)
24 × 24 mm Pixels
fV2
Guard
fH22
SUB
VDD2
VOUT2
VSS
VDD1
VOUT1
fR
VRD
VOG
fH21
FD1
FD2
É
1024 Active Pixels/Line
4 Dark
4 Inactive
8 Dark
2 Inactive
É
4 Dark Lines
fH1
fH2
NOTE: Shaded areas represent 4 non-imaging pixels at the beginning and 8 non-imaging pixels at the end of each line. There are also
4 non-imaging lines at the top and bottom of each frame.
Figure 2. Block Diagram
Refer to the block diagram in Figure 2. The KAF−1001
consists of one vertical (parallel) CCD shift register, one
horizontal (serial) CCD shift register and a selectable high
or low gain output amplifier. Both registers incorporate true
two-phase buried channel technology. The vertical register
consists of 24 mm × 24 mm photo-capacitor sensing elements
(pixels) which also serves as the transport mechanism.
The pixels are arranged in a 1024 (H) × 1024 (V) array;
an additional 12 columns (4 at the left and 8 at the right) and
8 rows (4 each at top and bottom) of non-imaging pixels are
added as dark reference. Because there is no storage array,
this device must be synchronized with strobe illumination or
shuttered during readout.
user to select either of the two output amplifiers. To use the
high dynamic range single-stage output (VOUT1), tie fH22
to a negative voltage to block charge transfer, and tie fH21
to fH2 to transfer charge. To use the high sensitivity
two-stage output (VOUT2), tie fH21 to a negative voltage
and fH22 to fH2. The charge packets are then dumped onto
the appropriate floating diffusion output node whose
potential varies linearly with the quantity of charge in each
packet. The amount of potential change is determined by the
simple expression DVfd = DQ/Cfd. The translation from
electrons to voltages is called the output sensitivity or
charge-to-voltage conversion. After the output has been
sensed off-chip, the reset clock (fR) removes the charge
from the floating diffusion via the reset drain (VRD). This,
in turn, returns the floating diffusion potential to the
reference level determined by the reset drain voltage.
Output Structure
The final gate of the horizontal register is split into two
sections, fH21 and fH22. The split gate structure allows the
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3
KAF−1001
H2
H1
H2
HCCD
Charge
Transfer
H1L
VDD
VOG
R
VRD
Floating
Diffusion
VOUT
VLG
Source
Follower
#1
Source
Follower
#2
Figure 3. Output Schematic
integration of charge is performed with fV1 and fV2 held
low. Transfer to horizontal CCD begins when fV1 is
brought high causing charge from the fV1 and fV2 gates
to combine under the fV1 gate.
fV1 and fV2 now reverse their polarity causing the
charge packets to ‘spill’ forward under the fV2 gate of the
next pixel. The rising edge of fV2 also transfers the first line
of charge into the horizontal CCD. A second phase transition
places the charge packets under the fV1 electrode of the
next pixel. The sequence completes when fV1 is brought
low. Clocking of the vertical register in this way is known as
accumulation mode clocking. Next, the horizontal CCD
reads out the first line of charge using traditional
complementary clocking (using fH1 and fH2 pins) as
shown. The falling edge of fH2 forces a charge packet over
the output gate (OG) onto one of the output nodes (floating
diffusion) which controls the output amplifier. The cycle
repeats until all lines are read.
Image Acquisition
An image is acquired when incident light, in the form of
photons, falls on the array of pixels in the vertical CCD
register and creates electron-hole pairs (or simply electrons)
within the silicon substrate. This charge is collected locally
by the formation of potential wells created at each pixel site
by induced voltages on the vertical register clock lines
(fV1, fV2). These same clock lines are used to implement
the transport mechanism as well. The amount of charge
collected at each pixel is linearly dependent on light level
and exposure time and non-linearly dependent on
wavelength until the potential well capacity is exceeded. At
this point charge will ‘bloom’ into vertically adjacent pixels.
Charge Transport
Integrated charge is transported to the output in a two-step
process. Rows of charge are first shifted line by line into the
horizontal CCD. ‘Lines’ of charge are then shifted to the
output pixel by pixel. Referring to the timing diagram,
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4
KAF−1001
Physical Description
Pin Description and Device Orientation
26 SUB
SUB 1
Pixel (1024, 1024)
fV2 2
25 fV2
fV1 3
24 fV1
SUB 4
23 GUARD
VOUT2 5
22 fV1
VDD2 6
21 fV2
VLG 7
20 N/C
VSS 8
19 N/C
fR
9
18 N/C
10
17 fH2
VDD1 11
16 fH1
VRD
15 fH22
VOUT1 12
VOG
13
Pixel (1, 1)
14 fH21
Figure 4. Pinout Diagram
Table 4. PIN DESCRIPTION
Pin
Name
Description
14
fH21
Last Horizontal (Serial) CCD Phase − Split
Gate
15
fH22
Last Horizontal (Serial) CCD Phase − Split
Gate
Substrate
16
fH1
Horizontal (Serial) CCD Clock − Phase 1
Video Output from High Sensitivity
Two-Stage Amplifier
17
fH2
Horizontal (Serial) CCD Clock − Phase 2
18
N/C
No Connection
19
N/C
No Connection
20
N/C
No Connection
21
fV2
Vertical (Parallel) CCD Clock − Phase 2
22
fV1
Vertical (Parallel) CCD Clock − Phase 1
23
GUARD
24
fV1
Vertical (Parallel) CCD Clock − Phase 1
25
fV2
Vertical (Parallel) CCD Clock − Phase 2
26
SUB
Substrate
Pin
Name
1
SUB
Substrate
2
fV2
Vertical (Parallel) CCD Clock − Phase 2
3
fV1
Vertical (Parallel) CCD Clock − Phase 1
4
SUB
5
VOUT2
6
VDD2
Description
High Sensitivity Two-Stage Amplifier
Supply
7
VLG
First Stage Load Transistor Gate for
Two-Stage Amplifier
8
VSS
Output Amplifier Return
9
fR
Reset Clock
10
VRD
Reset Drain
11
VDD1
High Dynamic Range Single-Stage
Amplifier Supply
12
VOUT1
13
VOG
Video Output from High Dynamic Range
Single-Stage Amplifier
Guard Ring
1. Pins 3, 22, and 24 must be connected together − only one
Phase 1 clock driver is required.
2. Pins 2, 21, and 25 must be connected together − only one
Phase 2 clock driver is required.
Output Gate
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5
KAF−1001
IMAGING PERFORMANCE
Typical Operational Conditions
sampling of the output is assumed and recommended. Many
units are expressed in electrons: to convert to voltage,
multiply by the amplifier sensitivity.
All values derived using nominal operating conditions
with the recommended timing. Correlated doubling
Specifications
Table 5. SPECIFICATIONS
Description
Symbol
Min.
Nom.
Max.
Units
FF
−
100
−
%
PRNU
−
−
5
% rms
QE
−
−
−
Notes
Verification
Plan
Full Array
Die10
ELECTRO-OPTICAL
Optical Fill Factor
Photoresponse
Non-uniformity
Quantum Efficiency
(450, 550, 650 nm)
Design11
CCD PARAMETERS COMMON TO BOTH OUTPUTS
Ne−SAT
450
500
−
ke−
2
Design11
JD
−
−
15.3
550
30
1,080
pA/cm2
e−/pix/sec
25°C
(Mean of All Pixels)
Die10
Dark Current Doubling Temp
DCDR
5
6
7
°C
Dark Signal Non-uniformity
DSNU
−
−
1,080
e−/pix/sec
Charge Transfer Efficiency
CTE
−
0.99997
−
V-H CCD Transfer Time
tVH
−
32
−
Blooming Suppression
BS
−
None
−
Sat. Signal − VCCD Register
Dark Current
ms
Design11
4
Die10
5
Die10
6, 7
Design11
CCD PARAMETERS SPECIFIC TO HIGH OUTPUT AMPLIFIER
VOUT/Ne−
9
11
−
mV/e−
Ne−SAT
180
200
240
ke−
1
Design11
ne−TOTAL
−
13
20
e− rms
8
Design11
Horizontal CCD Frequency
fH
−
2
5
MHz
6
Design11
Dynamic Range
DR
79
83
−
dB
9
Design11
Output Sensitivity
Sat. Signal
Total Sensor Noise
Design11
CCD PARAMETERS SPECIFIC TO LOW GAIN (HIGH DYNAMIC RANGE) OUTPUT AMPLIFIER
mV/e−
VOUT/Ne−
1.7
2
Ne−SAT
1,400
1,500
1,800
ke−
3
Design11
ne−TOTAL
−
22
30
e− rms
8
Die10
Horizontal CCD Frequency
fH
−
0.5
2
MHz
6
Design11
Dynamic Range
DR
93
97
−
dB
9
Design11
Output Sensitivity
Sat. Signal
Total Sensor Noise
Die10
1. Point where the output saturates when operated with nominal voltages.
2. Signal level at the onset of blooming in the vertical (parallel) CCD register.
3. Maximum signal level at the output of the high dynamic range output. This signal level will only be achieved when binning pixels containing
large signals.
4. None of 64 sub arrays (128 × 128) exceed the maximum dark current specification.
5. For 2 MHz data rate and T = 30°C to −40°C.
6. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
7. Time between the rising edge of fV1 and the first falling edge of fH1.
8. At TINTEGRATION = 0; data rate = 1 MHz; temperature = −30°C.
9. Uses 20LOG (Ne−SAT / ne−TOTAL) where Ne−SAT refers to the amplifier saturation signal.
10. A parameter that is measured on every sensor during production testing.
11. A parameter that is quantified during the design verification activity.
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6
KAF−1001
TYPICAL PERFORMANCE CURVES
Full Frame Image Sensor Spectral Response
1
0.9
KAF−1001: 24 mm Pixel
KAF−1401: 6.8 mm Pixel
Absolute Quantum Efficiency
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
400
500
600
700
800
900
1000
1100
1200
Wavelength (nm)
Figure 5. Typical Spectral Response
Most of the two phase CCD pixels are designed so that
each of the electrodes occupies half of the pixel area.
The KAF−1001 was not designed this way but instead is
designed with the transparent electrode occupying greater
than half the pixel area. This further improves the benefits
of the transparent gate.
Figure 5 shows a representative spectral response of front
side illuminated transparent gate full frame image sensors.
The KAF−1001 with 24 mm pixels has higher response than
the 6.8 mm pixel sensor at wavelengths greater than 750 nm
because it is constructed on a lower resistivity silicon
substrate. The resulting collection volume of each pixel
more efficiently collects signal generated deeper within the
silicon.
KAF−1001 Dark Current
Electrons/Pixel/Second
1000
100
10
1
−30
−20
−10
0
10
20
Temperature (5C)
Figure 6. Dark Current as a Function of Temperature
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30
KAF−1001
DEFECT DEFINITIONS
Table 6. SPECIFICATIONS
Grade
Point Defect
Cluster Defect
Column Defect
C1
20
2
0
C2
40
10
2
Point Defects
Dark: A pixel which deviates by more than 20% from
neighboring pixels when illuminated to 70% of saturation.
Bright: A pixel whose dark current exceeds 4,500 e−/pix/sec
at 25°C.
A column that loses > 500 electrons when the array is
illuminated to a signal level of 2,000 e−/pix (Trap like
defects).
Cluster Defect
A grouping of not more than 5 adjacent point defects.
Neighboring Pixels
The surrounding 128 × 128 pixels or ±64 columns/rows.
Column Defect
A grouping point defects along a single column (Dark
column).
Defect Separation
Defects are separated by no less than 3 pixels in any one
direction.
A column that does not exhibit the minimum charge
capacity specification (Low Charge capacity).
A column that contains a pixel whose dark current
exceeds 150,000 e−/pix/sec at 25°C (Bright column).
1, 1024
1024, 1024
All Pixels Subject to Detect Specification
1, 1
1024, 1
Figure 7. Active Pixel Region
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8
KAF−1001
OPERATION
Table 7. ABSOLUTE MAXIMUM RATINGS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−100
+80
°C
At Device
Operating Temperature
TOP
−50
+50
°C
At Device
Voltage
All Clocks
−16
+16
V
VSUB = 0 V
Voltage
OG
0
+8
V
VSUB = 0 V
Voltage
VRD, VSS, VDD, GUARD
0
+20
V
VSUB = 0 V
Current
Output Bias Current (IDD)
−
10
mA
Output Load Capacitance (CLOAD)
−
10
pF
Frequency/Time
fV1, fV2 Pulse Width
8
−
ms
Frequency/Time
fH1, fH2
−
5
MHz
Frequency/Time
fR Pulse Width
20
−
ns
Capacitance
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 8. DC BIAS OPERATING CONDITIONS
Description
Symbol
Minimum
Nominal
Maximum
Units
Pin Impedance
Substrate
VSUB
0.0
0.0
0.0
V
Common
Output Amplifier Supply
VDD
15.0
17.0
17.5
V
5 pF, 2 kW
Output Amplifier Return
VSS
1.4
2.0
2.1
V
5 pF, 2 kW
Reset Drain
VRD
11.5
12.0
12.5
V
5 pF, 1 MW
Output Gate
OG
3.0
4.0
4.5
V
5 pF, 10 MW
Guard Ring
GUARD
7.0
10.0
15.0
V
350 pF, 10 MW
Load Gate
VLG
VSS − 0.5
VSS
VSS + 1.0
V
Notes
1
1. VDD = 17 V for applications where the expected output voltage > 2.0 V. For applications where the expected useable output voltage is < 2 V,
VDD can be reduced to 15 V.
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9
KAF−1001
AC Operating Conditions
Table 9. CLOCK LEVELS
Description
Symbol
Level
Minimum
Nominal
Maximum
Units
Pin Impedance
Vertical CCD Clock − Phase 1
fV1
Low
−10.25
−10.0
−9.8
V
200 nF, 10 MW
Vertical CCD Clock − Phase 1
fV1
High
0.0
0.0
1.0
V
Vertical CCD Clock − Phase 2
fV2
Low
−10.25
−10.0
−9.8
V
200 nF, 10 MW
Vertical CCD Clock − Phase 2
fV2
High
0.0
0.0
1.0
V
CfV1−V2 = 100 nF
Horizontal CCD Clock − Phase 1
fH1
Low
−2.2
−2.0
−1.8
V
400 pF, 10 MW
Horizontal CCD Clock − Phase 1
fH1
High
7.8
8.0
8.2
V
Horizontal CCD Clock − Phase 2
fH2
Low
−2.2
−2.0
−1.8
V
250 pF, 10 MW
Horizontal CCD Clock − Phase 2
fH2
High
7.8
8.0
8.2
V
CfH1−H2 = 200 nF
Reset Clock
fR
Low
2.0
3.0
3.5
V
10 pF, 10 MW
Reset Clock
fR
High
9.5
10.0
11.0
V
Using the High Gain
Output (VOUT2)
Using the High Dynamic
Range Output (VOUT1)
Description
Symbol
Level
Min.
Nom.
Max.
Min.
Nom.
Max.
Units
Pin
Impedance
Horizontal Clock − Phase 1
fH21
Low
−4
fH2 Low
fH2 Low
−
fH2
−
V
10 pF, 10 MW
Horizontal Clock − Phase 1
fH21
High
−4
fH2 Low
fH2 Low
−
fH2
−
V
Horizontal Clock − Phase 2
fH22
Low
−
fH2
−
−
fH2 Low
fH2 Low
V
Horizontal Clock − Phase 2
fH22
High
−
fH2
−
−
fH2 Low
fH2 Low
V
10 pF, 10 MW
1. When using VOUT1, fH21 is clocked identically with fH2 while fH22 is held at a static level. When using VOUT2, fH21 and fH22 are
exchanged so that fH22 is identical to fH2 and fH21 is held at a static level. The static level should be the same voltage as fH2 low.
2. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may require adjustments of these
voltages. Pins shown with impedances greater than 1 MW are expected resistances. These pins are only verified to 1 MW.
3. fV1, 2 capacitances are accumulated gate oxide capacitance, and are an over-estimate of the capacitance.
4. This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult ON Semiconductor in
those situations in which operating conditions meet or exceed minimum or maximum levels.
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10
KAF−1001
TIMING
Table 10. REQUIREMENTS AND CHARACTERISTICS
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
fH1, fH2 Clock Frequency
fH
−
4
5
MHz
1, 2, 3
fV1, fV2 Clock Frequency
fV
−
100
125
kHz
1, 2, 3
Pixel Period (1 Count)
tPIX
200
250
−
ns
fH1, fH2 Setup Time
tfHS
500
1,000
−
ns
fV1, fV2 Clock Pulse Width
tfV
4
5
−
ms
2
Reset Clock Pulse Width
tfR
20
60
−
ns
4
tREADOUT
226
286
−
ms
5
Integration Time
tINT
−
−
−
Line Time
tLINE
219
277
−
Readout Time
6
ms
7
1. 50% duty cycle values.
2. CTE may degrade above the nominal frequency.
3. Rise and fall times (10/90% levels) should be limited to 5−10% of clock period. Crossover of register clocks should be between 40−60% of
amplitude.
4. fR should be clocked continuously.
5. tREADOUT = (1032 * tLINE)
6. Integration time (tINT) is user specified. Longer integration times will degrade noise performance due to dark signal fixed pattern and shot
noise.
7. tLINE = (3 * tfV) + tfHS + (1044* tPIX) + tPIX
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11
KAF−1001
Normal Readout
Frame Timing Detail
tINT
tREADOUT
1 Frame = 1032 Lines
fV1
fV2
Line
1
2
1031
1032
fH1
fH2
Line Timing Detail
Pixel Timing Detail
tfR
1 Line
tfV
fR
fV1
tfV
fH1
fV2
tPIX
1 Count
tPIX
tfHS
fH2
fH1
VPIX
fH2
VOUT
1044 Counts
VSAT
VDARK
fR
VODC
VSUB
Line Content
1−4 5−8
9−1032
VSAT
VDARK
1033−1042 1043−1044
VPIX
Photoactive
VODC
VSUB
Dummy Pixels
Dark Reference
Saturated pixel video output signal
Video output signal in no-light situation,
not zero due to JDARK
Pixel video output signal level,
more electrons = more negative
Video level offset with respect to VSUB*
Analog ground
* See Image Acquisition section.
Figure 8. Timing Diagram
NOTE: This device is suitable for a wide range of applications requiring a variety of different timing frequencies. Therefore, only maximum and
minimum values are shown above. Consult ON Semiconductor in those situations that require special consideration.
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12
KAF−1001
STORAGE AND HANDLING
Table 11. STORAGE CONDITIONS
Description
Symbol
Minimum
Maximum
Units
Notes
Storage Temperature
TST
−100
+80
°C
At Device
Operating Temperature
TOP
−50
90
°C
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
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13
KAF−1001
MECHANICAL INFORMATION
Completed Assembly
Figure 9. Completed Assembly (1 of 2)
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14
KAF−1001
Figure 10. Completed Assembly (2 of 2)
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15
KAF−1001
ON Semiconductor and the
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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