KAI 1003 D

KAI-1003
1024 (H) x 1024 (V) Interline
CCD Image Sensor
Description
The KAI−1003 Image Sensor is a high-performance megapixel
monochrome image sensor designed for a wide range of medical
imaging and machine vision applications.
The 12.8 mm square pixels with microlenses provide high sensitivity
and the large capacity results in large dynamic range. The two output,
split horizontal register and several binning modes allow a 15 to 60
frame per second (fps) video rate for the progressively scanned
images.
The vertical overflow drain structure provides anti-blooming
protection, and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag and
low smear.
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Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Figure 1. KAI−1003 Interline
CCD Image Sensor
Architecture
Interline CDD; Progressive Scan
Total Number of Pixels
1056 (H) × 1032 (V)
Number of Effective Pixels
1028 (H) × 1028 (V)
Features
Number of Active Pixels
1024 (H) × 1024 (V)
Pixel Size
12.8 mm(H) × 12.8 mm (V)
Active Image Size
13.1 mm (H) × 13.1 mm (V),
18.5 mm (Diagonal),
4/3″ Optical Format
Aspect Ratio
1:1
Number of Outputs
1 or 2
Charge Capacity
170,000 e−
Output Sensitivity
7.5 mV/e−
•
•
•
•
•
•
•
•
Quantum Efficiency (500 nm)
45%
Read Noise (f = 20 MHz)
40
Megapixel Progressive Scan Interline CCD
1024 (H) × 1024 (V) Imaging Pixels
12.8 mm Square Pixels
13.1 mm Square Imaging Area
Microlenses for Increased Sensitivity
Large Capacity (170 ke−)
Split Horizontal Register for 1 or 2 Outputs
Binning to 1 × 2 or 2 × 2
Applications
e−
• Machine Vision
• Medical
• Scientific
rms
nA/cm2
Dark Current
< 0.5
Dynamic Range
72 dB
Blooming Suppression
> 100 X
Smear
−80 dB
Maximum Pixel Clock Speed
20 MHz
Maximum Frame Rate
Single Output
Dual Output
Dual Output 2×2 Bin
15 fps
30 fps
60 fps
Package
28-Pin CERDIP
Cover Glass
AR Coated, 2 Sides
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 2
1
Publication Order Number:
KAI−1003/D
KAI−1003
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−1003 IMAGE SENSOR
Part Number
Description
KAI−1003−AAA−CR−AE
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1003−AAA−CR−B2
Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass with AR Coating (Both Sides), Grade 2
KAI−1003−ABA−CD−AE
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Engineering Sample
KAI−1003−ABA−CD−B2
Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass with AR Coating (Both Sides), Grade 2
Marking Code
KAI−1003
Serial Number
KAI−1003M
Serial Number
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number
KAI−1003−12−20−A−EVK
Description
Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
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2
KAI−1003
DEVICE DESCRIPTION
Architecture
2 Light Shielded Rows
14 Light Shielded Columns
2 Buffer Columns
2 Buffer Columns
2 Empty Pixels
Video A
KAI−1003
1024 (H) × 1024 (V)
Active Pixels
2 Empty Pixels
14 Light Shielded Columns
2 Buffer Rows
2 Buffer Rows
2 Light Shielded Rows
2
14
2
2
14
2
1024
2
14
2
14
Video B
Single Output
or
512
512
2
Dual Output
Figure 2. Sensor Architecture
and integration time and non-linearly dependent on
wavelength. When the photodiode’s charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming. The integration time can be decreased
below the frame time by using an electronic shutter, which
is a voltage pulse applied to the substrate to empty the
photodiodes.
The KAI−1003 is a high-performance, interline
charge-coupled device (CCD) designed for a wide range of
medical imaging and machine vision applications.
The device is built using an advanced two-phase,
double-polysilicon, NMOS CCD technology. The p+npn−
photodiodes eliminate image lag while providing
anti-blooming protection and electronic shutter capability.
The 12.8 mm square pixels with microlenses provide high
sensitivity and large dynamic range. The two output, split
horizontal register and several binning modes enable a 15 to
60 frame per second (fps) video rate with this megapixel
progressive scan imager.
Charge Transport
The integrated charge from each photodiode is
transported to the output by a three-step process. The charge
is first transferred from the photodiodes to the vertical shift
registers by applying a large positive voltage to one of the
vertical CCD phases. This transfer occurs simultaneously
for all photodiodes. The charge is then transported from the
vertical CCD registers to the horizontal CCD line by line in
parallel. Finally, the horizontal CCD register transports each
line of charge pixel by pixel serially to one or both of the
output structures.
The single horizontal CCD register is split into two halves
to allow a variety of line readout modes, as shown in
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photodiode. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent on light level
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3
KAI−1003
complementing the C phases, which reverses transport in the
B half of the horizontal CCD.
Binning can be used in a 1×2 and a 2×2 mode. Two
successive vertical transfers vertically bin the charge
directly onto the horizontal CCD, as shown in Figure 13 and
Figure 14. Horizontal binning is accomplished by two
successive horizontal transfers onto the H22 gate, which
then transfers the charge to the output structure, as shown in
Figure 15.
Combinations of output modes, binning and horizontal
clock frequency allow the range of frame rates listed in.
Figure 2 and Figure 3. The A output half of the register is a
true two-phase design, which results in unidirectional
transport using phases H1A and H2A. The B output half of
the register is a pseudo two-phase design, which allows
bi-directional transport using phases H1B, H2B, H1C and
H2C. Dual output is achieved with all of the first phases
identical and all the second phases identical. If the clocks of
H1A and H2A phases are shifted by one half cycle, the
output remains dual with the outputs alternating, so that only
one analog-to-digital converter is necessary. Finally, single
output of the entire image from the A output is obtained by
Table 4. KAI−1003 CALCULATED CLOCK PARAMETERS
Binning (H y V)
1y1
1y2
2y1
2y2
1y1
Output
Dual
Dual
Dual
Dual
Single
Unit
Parameter
HORIZONTAL CLOCK
20
20
20
40
20
MHz
Period
Actual
Effective
50
50
50
50
50
100
25
50
50
50
ns
Pixel Counts
Actual
Effective
532
532
532
532
532
266
532
266
1060
1060
Frequency
VERTICAL TO HORIZONTAL TRANSFER (HORIZONTAL RETRACE TIME)
Equivalent H-Clock
Counts (m)
80
80
80
160
80
Duration
4.0
4.0
4.0
4.0
4.0
Total H-Clock
Counts
612
612
612
692
1140
Line time
30.6
30.6
30.6
17.3
57.0
1032
1032
1032
516
1032
516
1032
516
1032
1032
4
4
4
7
2
122.4
122.4
122.4
121.1
114.0
Total Effective Line
Counts
1036
520
520
523
1034
Frame Time
31.7
15.9
15.9
9.0
58.9
ms
Frame Rate
31.5
62.8
62.8
110.5
17.0
frames/s
ms
HORIZONTAL LINE TIME
ms
VERTICAL CLOCK
Line Counts
Actual
Effective
PHOTODIODE READ (VERTICAL RETRACE TIME)
Equivalent Line
Counts (n)
Duration
ms
FRAME RATE
1. Time values have been rounded.
2. The number of counts (n and m) shown here are nominal integers, but in general they do not need be integers. They can be adjusted for
frame time, so long as the horizontal and vertical retrace times exceed the minimums specified in AC Timing Requirements.
3. Operation at 40 MHz will have increased readout noise.
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4
KAI−1003
Output Structure
fH1C
fH1B
fH2C
fH2B
fH1C
fH1B
fH2C
fH2B
fH1B
fH1C
fH1A
fH2A
fH1A
fH2A
In addition to the 1024 (H) by 1024 (V) imaging pixels,
there are active buffer, light shielded and empty pixels, as
fH2B
Non-Imaging Pixels
fH2C
shown in Figure 2. A two-pixel border of active buffer pixels
surrounds the imaging area. These buffer pixels respond to
illumination but are not tested for defects and
non-uniformities. Two light shielded rows lead and follow
each frame, and 14 light shielded columns lead and follow
each line. The light shielded columns are tested for column
defects and can be used for dark reference. Only the center
10 columns by 1028 rows of light shielded region on each
side can be used for dark reference due to light leakage into
the border of two pixels at the edges. Finally, two empty
pixels occur at the beginning of each line, which are empty
shift register cycles not associated with any vertical CCD
columns. Empty pixels may also occur at the end of the line,
depending on the timing.
Charge presented to the floating diffusion (FD) is
converted into a voltage and current amplified in order to
drive off-chip loads. The resulting voltage change seen at the
output is linearly related to the amount of charge placed on
the FD. Once the signal has been sampled by the system
electronics, the reset gate (fR) is clocked to remove the
signal and the FD is reset to the potential applied by the reset
drain (RD). More signal at the floating diffusion reduces the
voltage seen at the output pin. In order to activate the output
structure, an off-chip load must be added to the output pin
of the device.
fH1C
Single Output
H1A = H1B = H2C
H2A = H2B = H1C
Figure 3. Horizontal CCD Registers
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5
fH2B
H1A − 1/2 = H1B = H1C
H2A − 1/2 = H2B = H2C
fH2C
H1A = H1B = H1C
H2A = H2B = H2C
fH1B
Out-of-Phase
fH1A
fH2A
fH1A
fH2A
Dual Outputs
In-Phase
KAI−1003
Pin Description and Device Orientation
Pin 1 Designation
fV1
1
28
fV2
GND
2
27
GND
SUB
3
26
SUB
VDD
4
25
VMIN
VOUTA
5
24
VOUTB
VLG
6
23
VSS
RDA
7
22
RDB
fRA
8
Pixel
21
fRB
OGA
9
(1,1)
20
OGB
SUB
10
19
fH1B
fH1A
11
18
fH1C
fH2A
12
17
fH2C
fH22A 13
16
fH2B
15
fH22B
GND
14
Figure 4. Pin Description (Top View)
Table 5. PIN DESCRIPTION
Pin No.
Label
Pin No.
Label
1
fV1
15
fH22B
2
GND
16
fH2B
3
SUB
17
fH2C
4
VDD
18
fH1C
5
VOUTA
19
fH1B
6
VLG
20
OGB
7
RDA
21
fRB
8
fRA
22
RDB
9
OGA
23
VSS
10
SUB
24
VOUTB
11
fH1A
25
VMIN
12
fH2A
26
SUB
13
fH22A
27
GND
14
GND
28
fV2
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KAI−1003
PERFORMANCE SPECIFICATIONS
Table 6. PERFORMANCE SPECIFICATIONS
(All values measured at 40°C and 30 fps (integration time = 33 ms, fH = 20 MHz) for nominal operating parameters unless otherwise
noted. These parameters exclude defective pixels.)
Symbol
Min.
Nom.
Max.
Unit
QSAT
170
−
−
ke−
6.5
7.5
8.5
mV/e−
−
1.3
−
V
Quantum Efficiency at 500 nm
−
32
−
%
Quantum Efficiency at 540 nm
−
30
−
%
Quantum Efficiency at 600 nm
−
24
−
%
CCD Readout Noise with CDS
−
40
50
e− rms
IDARK
−
0.25
0.45
nA/cm2
XAB
100
−
−
Vertical Smear (Notes 2, 6)
−
0.005
0.01
%
Non-Uniformity of Sensitivity (Notes 3, 4)
−
0.3
0.5
% rms
Non-Uniformity of Dark Current (Note 4)
−
14
−
e− rms
Output Signal Non-Linearity (Note 5)
−
1
2
%
Gain Difference between the Two Video Outputs (Note 5)
−
−
10
%
Non-Uniformity of Gain between the Two Outputs (Note 5)
−
0.5
1.5
%
Description
Saturation Charge Capacity with Blooming Control
Output Gain
Output Voltage at the Saturation Level
VSAT
Dark Current
Anti-Blooming Factor (Notes 1, 2)
1. The illumination required to bloom the image sensor reported as a multiple of the saturation intensity. Blooming is defined as doubling the
vertical height of a spot that is 10% of the vertical CCD height at the saturation intensity.
2. Measured with continuous green light centered at 550 nm, F/4 optics and a spot size that is 10% of the vertical CCD height.
3. Measured at 90% of 150 ke− output.
4. Measured in the center 50 × 50 pixels.
5. Between 10% and 90% of 150 ke− output.
6. Measured without electronic shutter operation.
Typical Quantum Efficiency
0.50
Absolute Quantum Efficiency
0.45
With Cover Glass
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
400
500
600
700
800
900
Wavelength (nm)
Figure 5. Quantum Efficiency Spectrum
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7
1000
1100
KAI−1003
Angular Dependance of Quantum Efficiency
For the curve marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
Relative Quantum Efficiency (%)
100
90
80
Horizontal
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
Angle (Degrees)
Figure 6. Angular Dependance of Quantum Efficiency
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8
40
45
KAI−1003
DEFECT SPECIFICATIONS
Defect Test Conditions
Temperature:
Integration Time:
Light Source:
Operation:
40°C
33 ms (20 MHz HCCD Frequency, No Binning, 30 fps Frame Rate)
Continuous Green Light Centered at 550 nm
Nominal Voltages and Timing
Table 7. DEFECT DEFINITIONS
Name
Maximum
Number
Major Defective Pixel
20
A pixel whose signal deviates by more than 25 mV from the mean value of all active pixels
under dark field condition or by more than 8% from the mean value of all active pixels
under uniform illumination at 105 ke− output signal.
Minor Defective Pixel
100
A pixel whose signal deviates by more than 8 mV from the mean value of all active pixels
under dark field condition.
Cluster Defect
4
A group of 2 to 6 contiguous major defective pixels, but no more than 2 adjacent defects
horizontally.
Column Defect
0
A group of more than 6 contiguous major defective pixels along a single column.
Definition
Defect Proximity
Minimum Distance between Defective Clusters:
Minimum Distance between Defective Columns:
2 Pixels in All Directions without Major Pixel Defects
3 Columns without Column Defects or Cluster Defects
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KAI−1003
OPERATION
Table 8. ABSOLUTE MAXIMUM RATINGS
Item
Description
Temperature
Min.
Max
Unit
Operation to Specification
0
40
°C
Operation without Damage
−10
70
°C
Storage
−55
80
°C
0
95
%
Relative Humidity
Operation without Damage (Note 1)
Voltage (Between Pins)
SUB − GND (Notes 2, 5)
−0.6
50
V
VRD, VSS, VDD − GND
−0.6
25
V
VMIN − GND
−15
0.6
V
All Clocks − GND
−
17
V
fV1 − fV2 (Note 3)
−
17
V
fH1 − fH2
−
17
V
fH1, fH2 − fV2
−
17
V
fH2 − OG
−
17
V
VLG, OG – GND
−
17
V
fR, fH1, fH2 − VMIN
−
17
V
Capacitance
Output Load Capacitance (CLOAD) (Note 4)
−
10
pF
Current
Output Bias Current (IDD) (Note 4)
−
10
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Without condensation.
2. Under normal operating conditions, the substrate voltage should be maintained above 8.0 V. The substrate voltage should not remain above
25 V for longer than 100 ms.
3. Maximum of 20 V for fV1H − fV2L, with 20 ms maximum duration.
4. Each output.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Table 9. DC OPERATING CONDITIONS
Description
Symbol
Min.
Nom.
Max.
Unit
Output Gate
OG
1.8
2.0
2.2
V
Reset Drain
VRD
10.0
10.5
11.0
V
Output Amplifier Return (Note 1)
VSS
−
0.0
−
V
Output Amplifier Load Gate
VLG
1.4
1.5
1.6
V
Output Amplifier Supply
VDD
14.5
15.0
15.5
V
Disable ESD Protection (Note 2)
VMIN
−
−8.5
−
V
Substrate (Notes 3, 4, 5)
VSUB
8.0
TBS
18.0
V
Ground, P-Well (Note 4)
GND
−
0.0
−
V
1. Current sink.
2. Connect a 0.001 mF capacitor between VMIN and GND. VMIN must be more negative than the low voltage of any of the fH clocks and should
be established before the fH voltage is applied.
3. DC value when electronic shutter is not in use. See AC Clock Level Conditions for electronic shutter pulse voltage. The operating value of
the substrate voltage, VSUB, will be supplied with each shipment.
4. Ground and substrate biases should be established before other gate and diode potentials are applied.
5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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KAI−1003
Table 10. AC CLOCK LEVEL CONDITIONS
Description
Vertical CCD Clocks
(Note 1)
Horizontal CCD Clocks
(Note 1)
Reset Clock
Electronic Shutter Pulse (Notes 3, 4)
1.
2.
3.
4.
Level
Symbol
Min.
Nom.
Max.
Unit
High
fV2H
9.5
10.5
11.5
V
Mid
fV1M, fV2M
−0.8
−0.5
0.0
V
Low
fV1L, fV2L
−9.0
−8.5
−8.0
V
High
fH1H, fH2H
4.5
5.0
5.5
V
Low
fH1L, fH2L
−6.5
−6.0
−5.5
V
Amplitude
fRSWING
−
5.0
−
V
Low (Note 2)
VfRlow
0
TBS
5.0
V
Shutter
VSHUTTER
37
40
45
V
For best results, the CCD clock swings must be greater than or equal to the nominal values.
Reset clock low level voltage will be supplied with each shipment.
Electronic shutter pulse voltage referenced to GND. See DC Operating Conditions for DC level when electronic shutter is not in use.
Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
Electronic Shutter Operation
Electronic shuttering is accomplished by pulsing the
substrate voltage to empty the photodiodes. See Figure 16
for timing. The pulse must not occur while useful
information is being read from a line.
Table 11. CALCULATED CLOCK CAPACITANCE
Description
Vertical CCD Clocks
(Note 1)
Horizontal CCD Clocks
(Notes 1, 2)
Phase
Symbol
Typical
Unit
1 to GND
C fV1
55/37
nF
2 to GND
C fV2
50/32
nF
1 to 2
C fV1 − fV2
4
nF
1A
C fH1A
58/21
pF
1B
C fH1B
41/13
pF
1C
C fH1C
15/10
pF
2A
C fH2A
48/22
pF
2B
C fH2B
30/11
pF
2C
C fH2C
18/13
pF
C fH22A/B
3
pF
C fRA/B
5
pF
HCCD Summing Clock
Reset Clock − GND
1. Accumulation/depletion capacitances.
2. Capacitance of this gate to GND and all other gates.
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KAI−1003
Table 12. AC TIMING REQUIREMENTS
Description
Symbol
Min.
Nom.
Max.
Unit
tV2H
15
−
20
ms
tV
1.0
2.0/1.0
−
ms
tVPD1, tVPD3
40
−
−
ms
Vertical Pedestal Delay 2
tVPD2
15
−
−
ms
Horizontal Delay (Note 1)
tHD
1.5/0.5
−
−
ms
Reset Duration (Note 2)
tR
−
10
−
ns
Horizontal CCD Clock Frequency (Note 3)
fH
−
20
−
MHz
Pixel Time
tH
−
50
−
ns
Line Time (Note 4)
tL
−
−
−
Frame Time (Note 4)
tF
−
−
−
Clamp Delay (Note 5)
tCD
−
−
−
ns
Sample Delay (Note 5)
tSD
−
−
−
ns
tES
5
7.5
10
ms
tESHD
1.0
−
−
ms
Vertical High Level Duration
Vertical Transfer Time (Note 1)
Vertical Pedestal Delay 1 & 3
Electronic Shutter Pulse Duration
Electronic Shutter Horizontal Delay
1.
2.
3.
4.
5.
Non-binning/binning times.
The rising edge of fR should be coincident with the rising edge of fH22, within ±5 ns.
Horizontal CCD clock frequency can be increased to 40 MHz, with increased readout noise.
See Table 4 for nominal line and frame time in each mode.
The clamp delay and sample delay should be adjusted for optimum results.
Table 13. CCD CLOCK WAVEFORM CONDITIONS
Description
Phase
Symbol
tWH
tWL
tR
tF
Unit
1
2
fV1M/L
−
1.5
0.5
0.5
ms
fV2M/L
1.5
−
0.5
0.5
ms
2, High
fV2H
15
1.0
1.0
ms
1
fH1
20.5
21.5
4.0
4.0
ns
2
fH2
20.5
21.5
4.0
4.0
ns
2, Binning (Note 1)
fH22
20.5
21.5
4.0
4.0
ns
fR
5
39
3
3
ns
1 (Note 2)
fV1M/L
0.5
0.5
0.5
0.5
ms
2 (Note 2)
fV2M/L
0.5
0.5
0.5
0.5
ms
2, High
fV2H
15
−
1.0
1.0
ms
1
fH1
20.5
21.5
4.0
4.0
ns
2
fH2
20.5
21.5
4.0
4.0
ns
2, Binning
fH22
46.0
46.0
4.0
4.0
ns
fR
5
89
3
3
ns
NON-BINNING
Vertical CCD Clocks
Horizontal CCD Clocks
Reset clock
2y2 BINNING
Vertical CCD Clocks
Horizontal CCD Clocks
Reset clock
1.
2.
3.
Typical values measured with clocks connected to image sensor device. The actual values should be optimized for particular board layout.
fH22 may be connected to fH2 in 1×1 mode.
tWH and tWL for fV1M/L and fV2M/L are the time periods during the double pulses.
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KAI−1003
tR
tWH
tWL
tF
High 100%
90%
10%
Low 0%
Figure 7. CCD Clock Waveform
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13
KAI−1003
TIMING
Frame Timing − 1y1
tF = (1032 + n) ⋅ tL
fV1
fV2
Light Shielded Line
Buffer Line
tV2H
fV2
tPD1
tPD3
tPD2
n ⋅ tL
Line 1030
Line 0
Line 1031
fH1
fH2
Figure 8. Frame Timing − 1y1
www.onsemi.com
14
3
2
Image Line
fV1
tL
1
0
1031
1030
1029
1028
1027
4
3
2
1
0
1031
n ⋅ tL
KAI−1003
Line Timing − 1y1 − Single Output
tL = (1060 + m) ⋅ tH
fV1
tV
fV2
tHD
m ⋅ tH
fH1A,B &
fH2C
fH2A,B &
fH1C &
fH22A,B
Empty Pixels
Light Shielded Pixels
0
1
2
1056
1057
1058
1059
1040
1041
1042
1043
1044
1045
14
15
16
17
18
19
20
0
1
2
3
Pixel
Count
1057
1058
1059
fR
Buffer Pixels
Image Pixels
Figure 9. Line Timing − 1y1 − Single Output
Line Timing − 1y1 − Dual Output, In-Phase
tL = (532 + m) ⋅ tH
fV1
fV2
tV
tHD
m ⋅ tH
fH1
fH2 &
fH22
Empty Pixels
Light Shielded Pixels
Buffer Pixels
Figure 10. Line Timing − 1y1 − Dual Output, In-Phase
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15
0
1
2
528
530
531
14
15
16
17
18
19
529
530
531
Pixel
Count
0
1
2
3
fR
Image Pixels
KAI−1003
Line Timing − 1y1 − Dual Output, Out-of-Phase
tL = (532.5 + m) ⋅ tH
fV1
tV
fV2
m ⋅ tH
tHD
fH1A
fH1B,C
fH2A &
fH22A
fH2B,C &
fH22B
0
1
2
528
530
531
14
15
16
17
18
19
0
1
2
3
Pixel
Count
529
530
531
fRA
Empty Pixels
Light Shielded Pixels
Buffer Pixels
Figure 11. Line Timing − 1y1 − Dual Output, Out-of-Phase
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16
0
1
2
528
530
531
14
15
16
17
18
19
0
1
2
3
Pixel
Count
529
530
531
fRB
Image Pixels
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17
Figure 12. Pixel Timing − 1y1
Level
Reference
Video after Correlated
Double Sampling
(Inverted)
Sample
Clamp
VOUT
fR
fH2 &
fH22
fH1
Level
Reference
tR
tCD
tSD
tH
KAI−1003
Pixel Timing − 1y1
Signal
Signal
KAI−1003
Frame Timing − 2y2
tF = (516 + n) ⋅ tL
fV1
fV2
Light Shielded Line
Buffer Line
Image Line
fV1
tL
tV2H
fV2
tPD1
tPD3
tPD2
n ⋅ tL
Line 514
Line 0
Line 515
fH1
fH2
Figure 13. Frame Timing − 2y2
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18
3
2
1
0
515
514
513
512
511
4
3
2
1
0
1031
n ⋅ tL
KAI−1003
Line Timing − 2y2
tL = (532 + m) ⋅ tH
fV1
tV
fV2
tHD
m ⋅ tH
fH1
fH2
fH22
Empty Pixels
Light Shielded Pixels
Buffer Pixels
1
0
265
264
12
11
10
9
8
7
1
265
Pixel
Count
0
fR
Image Pixels
Figure 14. Line Timing − 2y2
Pixel Timing − 2y2
2 ⋅ tH
fH1
fH2
fH22
tR
fR
Reference
Signal
VOUT
Level
Clamp
tCD
tSD
Sample
Video after
Correlated Double
Sampling (Inverted)
Signal
Reference
Level
Figure 15. Pixel Timing − 2y2
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19
KAI−1003
Electronic Shutter Line Timing
fV1
fV2
tV
tHD
VSHUTTER
tES
VSUB
tESHD
fH1
fH2 & fH22
fR
Figure 16. Electronic Shutter Line Timing
Integration Time Definition
fV2
Integration Time
VSHUTTER
VSUB
Figure 17. Integration Time Definition
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20
KAI−1003
REFERENCES
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference
Manual
(SOLDERRM/D)
from
www.onsemi.com.
www.onsemi.com
21
KAI−1003
MECHANICAL DRAWINGS
Completed Assembly
Figure 18. Completed Assembly
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22
KAI−1003
Cover Glass Specification
Table 14. COVER GLASS SPECIFICATION
Item
Specification
Substrate
Schott D263T eco or equivalent
Thickness
0.030″ ± 0.002″
Coating
Double-sided anti-reflecting coating on a 0.660″ × 0.660″ square for a transmission minimum of 98% in the 400 to
700 nm wavelength
Scratch
No scratch greater than 10 microns
Cover Glass Care and Cleanliness:
1. The cover glass is highly susceptible to particles
and other contamination. Perform all assembly
operations in a clean environment.
2. Touching the cover glass must be avoided
3. Improper cleaning of the cover glass may damage
these devices. Improper cleaning of the cover glass
may damage these devices. Refer to Application
Note Image senosr Handling and Best Practices.
ON Semiconductor and the
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SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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23
ON Semiconductor Website: www.onsemi.com
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KAI−1003/D