KLI-2113 Linear CCD Image Sensor Description The KLI−2113 Image Sensor is a high dynamic range, multispectral, linear CCD image sensor ideally suited for demanding color scanner applications. The imager consists of three parallel 2098-element photodiode arrays − one for each primary color. The KLI−2113 sensor offers high sensitivity, a high data rate, low noise, and negligible lag. Independent exposure control for each channel allows color balancing at the front end. CMOS-compatible 5 V clocks, and single 12 V DC supply are all that are required to drive the KLI−2113 sensor, simplifying the design of interface electronics. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture 3 Channel, RGB Tri-linear CCD Pixels Count 2098 × 3 Pixel Size 14 mm (H) × 14 mm (V) Pixel Pitch 14 mm Inter-Array Spacing 112 mm (8 Lines Effective) Features Active Image Size 29.37 mm (H) × 0.24 mm (V) 29.4 mm (Diagonal) Saturation Signal 170,000 e− Dynamic Range 76 dB Responsivity (Wavelength) R, G, B (−RAA) R, G, B (−DAA)* Mono (−AAA, −AAB) 62, 42, 37 V/mJ/cm2 60, 40, 36 V/mJ/cm2 66 V/mJ/cm2 Output Sensitivity 11.5 mV/e− Dark Current 0.02 pA/Pixel Dark Current Doubling Rate 9°C Charge Transfer Efficiency 0.99999/Transfer Photoresponse Non-Uniformity 5% Peak-Peak • • • • • • • • • • • • Lag (First Field) 0.6% Maximum Data Rate 20 MHz/Channel Package CERDIP (Sidebrazed, CuW) Cover Glass AR Coated, 2 Sides Figure 1. KLI−2113 Linear CCD Image Sensor High Resolution Wide Dynamic Range High Sensitivity High Operating Speed High Charge Transfer Efficiency No Image Lag Electronic Exposure Control Pixel Summing Capability Up to 2.0 V Peak-Peak Output 5.0 V Clock Inputs Two-Phase Register Clocking On-Chip Dark Reference Applications * Configuration KLI-2113-DAA uses Gen1 color filter set and is not recommended for new designs. NOTE: Parameters above are specified at T = 25°C and 2 MHz clock rates unless otherwise noted. • • • • Digitization Machine Vision Mapping/Aerial Photography ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2015 November, 2015 − Rev. 5 1 Publication Order Number: KLI−2113/D KLI−2113 ORDERING INFORMATION Table 2. ORDERING INFORMATION − KLI−2113 IMAGE SENSOR Part Number Description Marking Code KLI−2113−AAA−ER−AA Monochrome, No Microlens, CERDIP Package (Leadframe), Taped Clear Cover Glass with AR Coating (2 Sides), Standard Grade KLI−2113−AAA−ER−AE Monochrome, No Microlens, CERDIP Package (Leadframe), Taped Clear Cover Glass with AR Coating (2 Sides), Engineering Sample KLI−2113−AAB−ED−AA Monochrome, No Microlens, CERDIP Package (Leadframe), Clear Cover Glass with AR Coating (Both Sides), Standard Grade KLI−2113−AAB−ED−AE Monochrome, No Microlens, CERDIP Package (Leadframe), Clear Cover Glass with AR Coating (Both Sides), Engineering Sample KLI−2113−RAA−ED−AA Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe), Clear Cover Glass with AR Coating (Both Sides), Standard Grade KLI−2113−RAA−ED−AE Gen2 Color (RGB), No Microlens, CERDIP Package (Leadframe), Clear Cover Glass with AR Coating (Both Sides), Engineering Sample KLI−2113−DAA−ED−AA* Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe), Clear Cover Glass with AR Coating (Both Sides), Standard Grade KLI−2113−DAA−ED−AE* Gen1 Color (RGB), No Microlens, CERDIP Package (Leadframe), Clear Cover Glass with AR Coating (Both Sides), Engineering Sample KLI−2113 Lot Number Serial Number KLI−2113 Lot Number Serial Number KLI−2113 Lot Number Serial Number KLI−2113 Lot Number Serial Number *Not recommended for new designs. Table 3. ORDERING INFORMATION − EVALUATION SUPPORT Part Number KLI−2113−12−5−A−EVK Description Evaluation Board (Complete Kit) See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KLI−2113 DEVICE DESCRIPTION LS LOGn Photodiode Array IG ID 12 Test 2098 Active Pixels 12 Dark RD fR VDD TG1 TG2 2 Blank 4 Blank CCD Cells CCD Cells FD f2 VIDn f1 f2s SUB SUB Figure 2. Single Channel Schematic Pixel Summing The effective resolution of this sensor can be varied by enabling the pixel summing feature. A separate pin is provided for the last shift register gate labeled f2s. This gate, when clocked appropriately, stores the summation of signal from adjacent pixels. This combined charge packet is then transferred onto the sense node. As an example, the sensor can be operated in 2-pixel summing mode (1,049 pixels), by supplying a f2s clock which is a 75% duty cycle signal at 1/2 the frequency of the f2 signal, and modifying the fR clock as depicted in Figure 10. Applications that require full resolution mode (2,098 pixels), must tie the f2s pin to the f2 pin. Refer to Figure 9 and Figure 10 for additional details. Exposure Control Exposure control is implemented by selectively clocking the LOG gates during portions of the scanning line time. By applying a large enough positive bias to the LOG gate, the channel potential is increased to a level beyond the ‘pinning level’ of the photodiode. (The ‘pinning’ level is the maximum channel potential that the photodiode can achieve and is fixed by the doping levels of the structure.) With TG1 in an ‘off’ state and LOG strongly biased, all of the photocurrent will be drawn off to the LS drain. Referring to Figure 9, one notes that the exposure can be controlled by pulsing the LOG gate to a ‘high’ level while TG1 is turning ‘off’ and then returning the LOG gate to a ‘low’ bias level sometime during the line scan. The effective exposure (tEXP) is the net time between the falling edge of the LOG gate and the falling edge of the TG1 gate (end of the line). Separate LOG connections for each channel are provided, enabling on-chip light source and image spectral color balancing. As a cautionary note, the switching transients of the LOG gates during line readout may inject an artifact at the sensor output. Rising edge artifacts can be avoided by switching LOG during the photodiode-to-CCD transfer period, preferably, during the TG1 falling edge. Depending on clocking speeds, the falling edge of the LOG should be synchronous with the f1/f2 shift register readout clocks. For very fast applications, the falling edge of the LOG gate may be limited by on-chip RC delays across the array. In this case, artifacts may extend across one or more pixels. Correlated double sampling (CDS) processing of the output waveform can remove the first order magnitude of such artifacts. In high dynamic range applications, it may be advisable to limit the LOG fall times to minimize the current transients in the device substrate and limit the magnitude of the artifact to an acceptable level. Image Acquisition During the integration period, an image is obtained by gathering electrons generated by photons incident upon the photodiodes. The charge collected in the photodiode array is a linear function of the local exposure. The charge is stored in the photodiode itself and is isolated from the CCD shift registers during the integration period by the transfer gates TG1 and TG2, which are held at barrier potentials. At the end of the integration period, the CCD register clocking is stopped with the f1 and f2 gates being held in a ‘high’ and ‘low’ state respectively. Next, the TG gates are turned ‘on’ causing the charge to drain from the photo-diode into the TG1 storage region. As TG1 is turned back ‘off’, charge is transferred through TG2 and into the f1 storage region. The TG2 gate is then turned ‘off’, isolating the shift registers from the accumulation region once again. Complementary clocking of the f1 and f2 phases now resumes for readout of the current line of data while the next line of data is integrated. www.onsemi.com 3 KLI−2113 Charge Transport a parallel format at the falling edge of the f2s clock. Resettable floating diffusions are used for the charge to voltage conversion while source followers provide buffering to external connections. The potential change on the floating diffusion is dependent on the amount of signal charge and is given by DVFD = DQ / CFD, where DVFD is the change in potential on the floating diffusion, DQ is the amount of charge, and CFD is the capacitance of the floating diffusion node. Prior to each pixel output, the floating diffusion is returned to the RD level by the reset clock, fR. Readout of the signal charge is accomplished by two-phase, complementary clocking of the Phase 1 and Phase 2 gates (f1 and f2) in the horizontal (output) shift register. The register architecture has been designed for high speed clocking with minimal transport and output signal degradation, while still maintaining low (4.75 VP−P min) clock swings for reduced power dissipation, lower clock noise and simpler driver design. The data in all registers is clocked simultaneously toward the output structures. The signal is then transferred to the output structures in www.onsemi.com 4 KLI−2113 Physical Description Pin Description and Device Orientation VIDR 1 28 VIDG SUB 2 27 SUB RD 3 26 VDD fR 4 25 VIDB LOGR 5 24 SUB LOGG 6 23 N/C SUB 7 22 LOGB N/C 8 21 N/C LS 9 20 N/C IG 10 19 ID TG2 11 18 TG1 N/C 12 17 N/C f2s 13 16 N/C f2 14 15 f1 Figure 3. KLI−2113 Pinout Table 4. PACKAGE PIN DESCRIPTION Pin Name 1 VIDR Red Output Video Description 15 f1 Phase1 Shift Register Clock 2 SUB Substrate 16 N/C No Connection 3 RD Reset Drain 17 N/C No Connection 4 fR Reset Clock 18 TG1 Inner Transfer Gate Input Diode Test Pin Pin Name Description 5 LOGR Red Overflow Gate 19 ID 6 LOGG Green Overflow Gate 20 N/C No Connection 7 SUB Substrate 21 N/C No Connection 8 N/C No Connection 22 LOGB 9 LS Light Shield/Exposure Drain 23 N/C No Connection 10 IG Input Gate/LOG Test Pin 24 SUB Substrate 11 TG2 Outer Transfer Gate 25 VIDB Blue Output Video 12 N/C No Connection 26 VDD Amplifier Supply 13 f2s Phase2 Shift Register Summing Gate Clock 27 SUB Substrate 14 f2 Phase2 Shift Register Clock 28 VIDG Green Output Video www.onsemi.com 5 Blue Overflow Gate KLI−2113 IMAGING PERFORMANCE Typical Operational Conditions Specifications given under nominal operating conditions @25°C ambient, fCLK =2 MHz and nominal external VIDn load resistors unless otherwise specified. Table 5. SPECIFICATIONS Description Saturation Output Voltage Output Sensitivity Symbol Min. Nom. Max. Units Notes Verification Plan VSAT − 2.0 − VP−P 1, 7 Die8 DVO/DNe − 11.5 − mV/e− 7 Design9 Saturation Signal Charge Ne,SAT − 170k − e− Output Buffer Bandwidth f−3dB − 75 − MHz @ CLOAD = 10 pF Design9 DR − 76 − dB 3 Design9 Dark Current IDARK − 0.02 − pA/Pixel 4 Die8 Charge Transfer Efficiency CTE − 0.99999 − − 5 Design9 L − 0.6 1 % 1st Field Design9 VODC 6 7 9 V 7 Design9 Register Clock Capacitance Cf − 500 − pF per Phase Design9 Transfer Gate Capacitance CTG − 400 − pF Design9 V/mJ/cm2 Design9 − − − 62 42 37 − − − nm Design9 − − − 650 540 460 − − − − 7 14 %p−p Die8 V/mJ/cm2 Design9 − − − 60 40 36 − − − nm Design9 − − − 650 540 460 − − − − 5 10 %p−p Die8 V/mJ/cm2 Design9 nm Design9 %p−p Die8 Dynamic Range Lag DC Output Offset Design9 KLI−2113−RAA CONFIGURATION GEN2 COLOR Responsivity Red Channel Green Channel Blue Channel Peak Responsivity Wavelength Red Channel Green Channel Blue Channel Photoresponse Uniformity RMAX lR PRNU KLI−2113−DAA CONFIGURATION GEN1 COLOR (Note 10) Responsivity Red Channel Green Channel Blue Channel Peak Responsivity Wavelength Red Channel Green Channel Blue Channel Photoresponse Uniformity RMAX lR PRNU KLI−2113−AAA AND KLI−2113–AAB CONFIGURATION MONOCHROME Responsivity Monochrome, All Channels Peak Responsivity Wavelength Monochrome, All Channels Photoresponse Uniformity RMAX − 66 − − 675 − − 5 10 lR PRNU 1. Defined as the maximum output level achievable before linearity or PRNU performance is degraded. 2. With color filter. Values specified at filter peaks. 50% bandwidth = ±30 nm. 3. This device utilizes 2-phase clocking for cancellation of driver displacement currents. Symmetry between f1 and f2 phases must be maintained to minimize clock noise. 4. Dark current doubles approximately every 9°C. 5. Measured per transfer. For total line h < (0.99999)4256 = 0.96 6. Low frequency response across array with color filter array. 7. Decreasing external VIDn load resistors to improve signal bandwidth will decrease these parameters. 8. A parameter that is measured on every sensor during production testing. 9. A parameter that is quantified during the design verification activity. 10. Configuration KLI−2113−DAA uses Gen1 color filter set and is not recommended for new designs. www.onsemi.com 6 KLI−2113 TYPICAL PERFORMANCE CURVES (2 MHz Operation, Emitter Follower Buffered, 3/4 VSAT, Dark to Bright Transition) VIDR Output (1 V/DIV) f2 Clock (2 V/DIV) Time (200 ns/DIV) Figure 4. Output Waveforms 70 50 40 30 20 10 Wavelength (nm) Figure 5. Typical Responsivity www.onsemi.com 7 1100 1050 1000 950 900 850 800 750 700 650 600 550 500 450 400 350 0 300 Responsivity (V/mJ/cm2) 60 KLI−2113 DEFECT DEFINITIONS Table 6. OPERATING CONDITION SPECIFICATIONS (Test Conditions: T = 25°C, fCLK = 2 MHz, tINT = 1.066 ms) Field Defect Type Threshold Units Notes Number Dark Bright 8.0 mV 1, 2 0 Bright Bright/Dark 10 % 1, 3 0 Bright Exposure Control 4.0 mV 1, 4, 5 ≤ 16 1. 2. 3. 4. Defective pixels will be separated by at least one non-defective pixel within and across channels. Pixels whose response is greater than the average response by the specified threshold. See Figure 6 below. Pixels whose response is greater or less than the average response by the specified threshold. See Figure 6 below. Pixels whose response deviates from the average pixel response by the specified threshold when operating in exposure control mode. See Figure 6 below. 5. Defect coordinates are available upon request. Note 3: Bright Field Bright Pixel Note 4: Bright Field Exposure Control Bright Defect Average Pixel Average Pixel Signal Out Signal Out Note 2: Dark Field Bright Pixel Note 5: Bright Field Field Exposure Control Dark Defect Note 3: Bright Field Dark Pixel Exposure Exposure Figure 6. Illustration of Defect Classifications www.onsemi.com 8 KLI−2113 OPERATION Table 7. ABSOLUTE MAXIMUM RATINGS Description Symbol Minimum Maximum Unit Notes Gate Pin Voltage VGATE −0.5 16 V 1, 2 Pin-to-Pin Voltage VPIN−PIN − 16 V 1, 3 Diode Pin Voltage VDIODE −0.5 16 V 1, 4 IDD − −10 mA 5 Output Load Capacitance CVID,LOAD − 15 pF CCD Clocking Frequency fC − 20 MHz Output Bias Current 6 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Referenced to substrate voltage. 2. Includes pins: f1, f2, f2s, TG1, TG2, fR, IG, and LOGn. 3. Voltage difference (either polarity) between any two pins. 4. Includes pins: VIDn, RD, VDD, LS and ID. 5. Care must be taken not to short output pins to ground during operation as this may cause serious damage to the output structures. 6. Charge transfer efficiency will degrade at frequencies higher than the nominal (2 MHz) clocking frequency. VIDn load resistor values may need to be decreased as well to achieve required output bandwidths. Device Input ESD Protection Circuit (Schematic) To Device Function I/O Pin Vt − 20 V SUB CAUTION: To allow for maximum performance, this device contains limited I/O protection and may be sensitive to electrostatic induced damage. Devices should be installed in accordance with strict ESD handling procedures! Figure 7. ESD Protection Circuit www.onsemi.com 9 KLI−2113 DC Bias Operating Conditions Table 8. DC BIAS OPERATING CONDITIONS Symbol Minimum Nominal Maximum Units Substrate Description VSUB − 0 − V Reset Drain Bias VRD 11.5 12.0 12.5 V Output Buffer Supply VDD 11.5 12.0 12.5 V Light Shield/Drain Bias VLS 11.5 12.0 12.5 V Output Bias Current/Channel IDDn −4.0 −6.0 −8.0 mA Test Pin − Input Gate/LOG VIG − 12.0 − V Test Pin − Input Diode VID − 12.0 − V Notes 1 1. A current sink must be supplied for each output. Load capacitance should be minimized so as not to limit bandwidth. See Figure 8.Choose values optimized for specific operating frequency, but R2 should not be less than 75 W. Typical Output Bias/Buffer Circuit VDD 0.1 mF 2N2369 or Similar* To Device Output Pin: VIDn (Minimize Path Length) Buffered Output R2 = 120 W* R1 = 600 W* Figure 8. Typical Output Bias/Buffer Circuit www.onsemi.com 10 KLI−2113 AC Operating Conditions Table 9. CLOCK LEVELS Symbol Minimum Nominal Maximum Units CCD Readout Clocks High Description Vf1H, Vf2H, Vf2sH 4.75 5.0 5.25 V Notes CCD Readout Clocks Low Vf1L, Vf2L, Vf2sL −0.1 0.0 0.1 V Transfer Clocks High VTG1H, VTG2H 4.75 5.0 5.25 V Transfer Clocks Low VTG1L, VTG2L −0.1 0.0 0.1 V Reset Clock High VfRH 4.75 5.0 5.25 V Reset Clock Low VfRL −0.1 0.0 0.1 V Exposure Clocks High VLOG1H, VLOG2H 4.75 5.0 5.25 V 1 Exposure Clocks Low VLOG1L, VLOG2L −0.1 0.0 0.1 V 1 Minimum Nominal Maximum Units Notes 50 50 − ns 1. Tie pin to 0 V for applications where exposure control is not used. Table 10. AC TIMING LEVELS Description CCD Element Duration Line/Integration Period Symbol 1e- (= 1/fCLK) 1L (= tINT) 0.108 1.066 − ms PD−CCD Transfer Period tPD 1.0 − − ms Transfer Gate 1 Clear tTG1 500 − − ns Transfer Gate 2 Clear tTG2 500 − − ns LOGGate Duration tLOG1 1 − − ms LOGGate Clear tLOG2 1 − − ms Reset Pulse Duration tRST 9 − − ns Clamp to f2 Delay tCD 5 − − ns 1 Sample to Reset Edge Delay tSD 5 − − ns 1 CCD Clock Rise Time tR − 30 − ns Typical 1. Recommended delays for Correlated Double Sampling of output. www.onsemi.com 11 KLI−2113 TIMING Line Timing f1 4e 12e 2098e 12e 2e 4e 12e 2098e 12e 2e f2 4e 12e 2098e 12e 2e 4e 12e 2098e 12e 2e TG1 tINT TG2 tLOG1 tLOG2 LOGn tEXP Photodiode-to-CCD Transfer Timing First Dark Reference Pixel Data Valid 1e f1 f2 tPD TG1 tTG1 tTG2 TG2 See Timing Notes LOGn Output Timing (Full Resolution Mode) 1e f2s = f2 VFEEDTHRU VDARK VIDn VSAT tRST tCD tSD fR Clamp* Sample* tCLP tSPL * Required for Correlated Double Sampling. Figure 9. Normal Mode Timing www.onsemi.com 12 KLI−2113 Output Timing (2-Pixel Summing Mode) 1e f2 f2s fR VIDn VPixel N + Pixel (N+1) Clamp* Sample* * Required for Correlated Double Sampling. Figure 10. Binning Mode Timing www.onsemi.com 13 KLI−2113 MECHANICAL INFORMATION Completed Assembly Figure 11. Completed Assembly Drawing (1 of 4) www.onsemi.com 14 KLI−2113 Figure 12. Completed Assembly Drawing (2 of 4) www.onsemi.com 15 KLI−2113 Figure 13. Completed Assembly Drawing (3 of 4) www.onsemi.com 16 KLI−2113 Figure 14. Completed Assembly Drawing (4 of 4) www.onsemi.com 17 KLI−2113 REFERENCES For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 www.onsemi.com 18 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KLI−2113/D