Ordering number : ENA2310A LC450210PCH CMOS LSI 1/8 to 1/16 Duty Dot Matrix LCD Controller Driver http://onsemi.com Overview The LC450210PCH is the 1/8 to 1/16 duty dot matrix LCD controller driver. By controlling this driver with a microcontroller, it is used in applications such as character display and simple graphic display etc. This driver can drive a LCD panel of up to 3,200 dots (16 16 dot font: 1-line display of up to 12 digits and 128 segments, 5 7 dot font: 2-line display of up to 40 digits). The operating temperature range is from -40 to +105 [C]. Features 1. Selectable duty ratio by serial data: 1/8 duty to 1/16 duty 1/8 duty: 8 200 = 1,600 dots 1/11 duty: 11 200 = 2,200 dots 1/14 duty: 14 200 = 2,800 dots 1/9 duty: 9 200 = 1,800 dots 1/12 duty: 12 200 = 2,400 dots 1/15 duty: 15 200 = 3,000 dots 1/10 duty: 10 200 = 2,000 dots 1/13 duty: 13 200 = 2,600 dots 1/16 duty: 16 200 = 3,200 dots 2. Selectable LCD bias voltage ratio by serial data: 1/4 bias or 1/5 bias 3. Selectable inversion drive of LCD drive waveform by serial data: line inversion or frame inversion 4. Adjustable frame frequency of common and segment output waveforms and clock frequency of voltage booster by serial data, for preventing interference with the frequency of the backlight. 5. Selectable operation modes by serial data: power-saving mode (maintains display data), the state of display (ON, all ON, all OFF, all forced OFF) 6. Built-in oscillator circuit (built-in resistor and capacitor for oscillation) 7. Selectable fundamental clock operating modes by serial data: internal oscillator operating mode or external clock operating mode 8. Input of serial data supports CCB* format (for 5V and 3V) 9. Selectable voltage range of power supply for logic block by setting REGE pad (VDD): +4.5V to +5.5V (5V power supply (REGE=VDD)) +2.7V to +3.6V (3V power supply (REGE=VSS)) 10. Built-in quadruple and quintuple voltage booster with discharge function Base voltage of boosting (VBTI2): +3.2V (Typ.) (5V power supply (REGE=VDD)) (VBTI1=VBTI2): +2.7V to VDD[V] (3V power supply (REGE=VSS)) 11. Power supply for LCD driver block (VLCD): +16.0V (Typ.) (VDD=5V, Quintuple voltage booster is used.) +16.5V (VDD=3.3V, Quintuple voltage booster is used.) +4.5V to +16.5V (range with external power supply) Continued on next page. CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. CCB is a registered trademark of Semiconductor Components Industries, LLC. ORDERING INFORMATION See detailed ordering and shipping information on page 53 of this data sheet. Semiconductor Components Industries, LLC, 2014 May, 2014 51214HK 20140430-S00001/42114HKPC No.A2310-1/53 LC450210PCH Continued from preceding page. 12. Built-in contrast adjuster LCD drive bias voltage (VLCD0): +4.65V to +13.5V (Typ.) (VDD=5V, Quintuple voltage booster is used.) +4.65V to +14.1V (VDD=3.3V, Quintuple voltage booster is used.) +4.65V to +14.1V (VLCD=16.5V with external power supply) ____ 13. The initialization of this driver and the prevention of an unintended display are controllable by setting RES pad. 14. Wide range of operating temperature: -40 to +105 [C] 15. CMOS process and chip with Au bumps Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0V Parameter Symbol Conditions VDD, Supply voltage VDD max REGE = VDD VDD, REGE = VSS VLCD max VIN1 VLCD (Note.1) ____ CE, CL, DI, RES, TSIN1 to TSIN4, OSCI ____ CE, CL, DI, RES, TSIN1 to TSIN4, OSCI, Supply more than 2.7V to VDD before VIN1 is input. Input voltage Output voltage Unit -0.3 to +6.0 -0.3 to +4.2 -0.3 to +4.2 -0.3 to +6.0 VBTI1 -0.3 to VDD+0.3 VIN3 REGE -0.3 to +6.0 VIN4 VLCD5 (Note.1) -0.3 to VLCD+0.3 VOUT1 VLCD -0.3 to VLCD+0.3 VOUT2 S1 to S200, COM1 to COM16 -0.3 to VLCD+0.3 VOUT3 CP12N, CP34N, VLOGIC, TSOUT1 to TSOUT3, TSO, CP12N, CP34N, VLOGIC, TSOUT1 to TSOUT3, TSO, VDD > 3.9V (REGE=VDD) -0.3 to VDD+0.3 CP1P, CP2P, CP3P, CP4P -0.3 to VLCD+0.3 VINOUT2 VLCD0, VLCD1, VLCD2, VLCD3, VLCD4 (Note.1) -0.3 to VLCD+0.3 VINOUT3 VBTI2, VBTI2, VBTI1 > 3.9V (REGE=VDD) V V -0.3 to +4.2 VINOUT1 VBTI1 ≤ 3.9V (REGE=VSS) V -0.3 to +17.0 VIN2 VDD ≤ 3.9V (REGE=VSS) Input / Output voltage Ratings -0.3 to VBTI1+0.3 V -0.3 to +4.2 IOUT1 VLCD Output current IOUT2 S1 to S200 8 IOUT3 COM1 to COM16 Operating temperature Topr -40 to +105 °C Storage temperature Tstg -55 to +125 °C 0.3 mA 1 (Note.1) Follow a condition of VLCD VLCD0 > VLCD1 > VLCD2 > VLCD3 > VLCD4 > VLCD5. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. No.A2310-2/53 LC450210PCH Allowable Operating Ranges at Ta = -40 to +105C, VSS = 0V Parameter Symbol Ratings Conditions Min. VDD, VDD Supply voltage REGE = VDD VDD, REGE = VSS VLCD VLCD, When VLCD is supplied from the outside. Typ. Unit Max. 4.5 5.5 2.7 3.6 4.5 16.5 4.5 VDD 2.7 VDD (≤ 3.6) 2.7 VDD (≤ 3.3) V VBTI1, VBTI1 VDD = 4.5V to 5.5V (REGE = VDD), Quadruple/Quintuple voltage booster is used. VBTI1, VBTI2 (VBTI1 = VBTI2), Input base voltage for voltage booster VBTI2 VDD = 2.7V to 3.6V (REGE = VSS), Quadruple voltage booster is used. V VBTI1, VBTI2 (VBTI1 = VBTI2), VDD = 2.7V to 3.3V (REGE = VSS), Quintuple voltage booster is used. VLCD0 Input voltage for LCD drive bias voltage generator VLCD1 VLCD2 VLCD0, 4.5 Contrast adjuster is not used. (Note. 1) VLCD1, VLCD2, VLCD3, VLCD4, VLCD3 VLCD4 LCD drive bias voltage generator is not used. VLCD5 VLCD5 Input High-level voltage Input Low-level voltage VIL1 VDD = 4.5V to 5.5V (REGE = VDD) ____ CE, CL, DI, RES, OSCI REGE ____ CE, CL, DI, RES, TSIN1 to TSIN4, OSCI VDD = 4.5V to 5.5V (REGE = VDD) ____ CE, CL, DI, RES, TSIN1 to TSIN4, OSCI VDD = 2.7V to 3.6V (REGE = VSS) VIL2 External clock input frequency fCK External clock duty DCK Data setup time Data hold time REGE OSCI, External clock operating mode VLCD (Note. 1) (Note.1) [Fig.1] OSCI, V V 0 VDD = 2.7V to 3.6V (REGE = VSS) VIH2 (Note. 1) V (Note.1) ____ CE, CL, DI, RES, OSCI VIH1 V 0.5VDD 5.5 0.8VDD 3.6 0.8VDD 5.5 0 0.2VDD 0 0.2VDD 0 0.2VDD V V 100 300 600 kHz 30 50 70 % External clock operating mode [Fig.1] tds CL, DI [Fig.2], [Fig.3] 160 ns tdh CL, DI [Fig.2], [Fig.3] 160 ns CE wait time tcp CE, CL [Fig.2], [Fig.3] 160 ns CE setup time tcs CE, CL [Fig.2], [Fig.3] 160 ns CE hold time tch CE, CL [Fig.2], [Fig.3] 160 ns tH CL [Fig.2], [Fig.3] 160 ns tL CL [Fig.2], [Fig.3] 160 ns Rise time tr CE, CL, DI [Fig.2], [Fig.3] 160 ns Fall time tf CE, CL, DI ____ RES [Fig.2], [Fig.3] 160 ns High-level clock pulse width Low-level clock pulse width Reset pulse minimum width twres [Fig.5] to [Fig.8] 1.0 ms (Note.1) Follow a condition of VLCD VLCD0 > VLCD1 > VLCD2 > VLCD3 > VLCD4 > VLCD5. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. No.A2310-3/53 LC450210PCH Electrical Characteristics in the Allowable Operating Ranges Parameter Hysteresis Input High-level Symbol VH CE, CL, DI, ____ RES, OSCI IIH1 CE, ____CL, DI, RES, OSCI IIH2 REGE current Input Low-level current PAD IIL1 CE, CL, DI, ____ RES, TSIN1 to TSIN4, Conditions Ratings Min. Typ. VDD = 4.5V to 5.5V (REGE = VDD) 0.03VDD VDD = 2.7V to 3.6V (REGE = VSS) 0.05VDD Max. V VI = 3.6V 5.0 VI = 5.5V, Supply more than 2.7V to VDD before VI is input. 5.0 VI = 5.5V 5.0 VI = 0V Unit A A -5.0 REGE, OSCI VDD = 5.5V, VBTI1 = 5.5V, REGE = VDD, Quadruple voltage booster is used. Contrast adjuster is used. LCD drive bias voltage generator is used. 2,050 4,100 2,550 5,100 Common and segment outputs are open. IBTI1 VBTI1 display on (normal display) VDD = 5.5V, VBTI1 = 5.5V, REGE = VDD, Quintuple voltage booster is used. Contrast adjuster is used. LCD drive bias voltage generator is used. Common and segment outputs are open. display on (normal display) Input current for VDD = 3.6V, VBTI1 = VBTI2 = 3.6V, REGE = VSS, voltage booster A Quadruple voltage booster is used. Contrast adjuster is used. 2,000 4,000 2,500 5,000 LCD drive bias voltage generator is used. Common and segment outputs are open. IBTI2 VBTI2 display on (normal display) VDD = 3.3V, VBTI1 = VBTI2 = 3.3V, REGE = VSS, Quintuple voltage booster is used. Contrast adjuster is used. LCD drive bias voltage generator is used. Common and segment outputs are open. display on (normal display) ON-resistance of segment driver RONS S1 to S200 output 20 k 20 k VLCD1 to VLCD5 = 1/5 bias (with external input) ON-resistance of common driver VLCD = 4.5V (with external supply), VLCD0 = 4.5V (with external input), RONC COM1 to COM16 output VLCD = 4.5V (with external supply), VLCD0 = 4.5V (with external input), VLCD1 to VLCD5 = 1/5 bias (with external input) VBTI1 = 4.5V to 5.5V (REGE = VDD) Voltage booster is used. VBTI2 VBTI2 Contrast adjuster is not used. 3.09 3.2 3.3 (VBTI24) - 0.4 VBTI24 (VBTI24) + 0.4 (VBTI25) - 0.4 VBTI25 16.5 210 300 390 LCD drive bias voltage generator is not used. No-load. Quadruple voltage booster is used. Contrast adjuster is not used. Output voltage LCD drive bias voltage generator is not used. VLCD VLCD V No-load. Quintuple voltage booster is used. Contrast adjuster is not used. LCD drive bias voltage generator is not used. No-load. Oscillator frequency fosc Internal clock generator Internal oscillator operating mode kHz Continued on next page. No.A2310-4/53 LC450210PCH Continued from preceding page. Parameter Symbol PAD Conditions Ratings Min. Typ. Max. Unit <Power-saving mode> VDD = 3.6V (REGE = VSS), communication inactive, 15 Input level is VSS or VDD. IDD1 VDD < Power-saving mode > VDD = 5.5V (REGE = VDD), communication inactive, 50 120 100 500 Input level is VSS or VDD. <Normal mode> VDD = 3.6V (REGE = VSS), display on (normal display), internal oscillator operating mode, Power current A communication inactive, IDD2 VDD Input level is VSS or VDD. < Normal mode > VDD = 5.5V (REGE = VDD), display on (normal display), internal oscillator operating mode, 150 600 500 1,000 communication inactive, Input level is VSS or VDD. < Normal mode > VLCD = 16.5V (with external supply), display on (normal display), ILCD VLCD Voltage booster is not used. Contrast adjuster is used. LCD drive bias voltage generator is used. Common and segment outputs are open. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. No.A2310-5/53 LC450210PCH (1) Clock timing of OSCI pad in the external clock operating mode tCKH tCKL fCK= VIH1 50% VIL1 OSCI 1 tCKH + tCKL [kHz] tCKH x 100[%] DCK= tCKH + tCKL [Fig.1] (2) When CL is stopped at the low level VIH1 CE VIL1 tL tH CL tf VIH1 50% VIL1 tr tcp tcs tch VIH1 DI VIL1 tds tdh [Fig.2] (3) When CL is stopped at the high level VIH1 CE VIL1 tL tH CL tf VIH1 50% VIL1 tr tcp tcs tch VIH1 DI VIL1 tds tdh [Fig.3] No.A2310-6/53 LC450210PCH S1 S200 COM1 COM16 Block Diagram REGE VBTI1 VBTI2 CP1P CP12N CP2P CP3P CP34N CP4P VOLTAGE BOOSTER COMMON DRIVER SEGMENT DRIVER LACTH VLCD CONTRAST ADJUSTER DISPLAY DATA ADDRESS VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD5 RAM COUNTER LCD DRIVE (16 200 bits) BIAS VOLTAGE GENERATOR INSTRUCTION REGISTER & DECODER SHIFT REGISTER ____ RES VDD TIMING GENERATOR REGULATOR CLOCK GENERATOR VSS CCB INTERFACE TSIN1 to 4 TSOUT1 to 3 CE CL DI OSCI VLOGIC TSO No.A2310-7/53 LC450210PCH Pad Functions Handling Pad Name Pad No. Function Active I/O when unused This is a power supply for logic block. VDD 231 to 234 REGE = VDD: Supply a voltage from 4.5V to 5.5V to VDD. - - - - - - - O OPEN - I - These are segment driver outputs. - O OPEN These are common driver outputs. - O OPEN - I OPEN - I/O OPEN - I/O OPEN REGE = VSS: Supply a voltage from 2.7V to 3.6V to VDD. In addition, make sure to connect a capacitor between VDD and VSS. VSS VLOGIC 226 to 229, 235 to 243 216 Make sure to connect VSS to ground. This is a monitor of a regulator output for logic power supply. Do not use VLOGIC with an external circuit. This is an input for controlling the regulator of logic power supply and the regulator of voltage booster. Depending on specification of power supply, make sure to connect REGE to VDD or VSS. REGE 230 REGE = VDD: 5V Power supply is used. The regulator of logic power supply runs. The regulator of voltage booster runs. REGE = VSS: 3V Power supply is used. The regulator of logic power supply stops. The regulator of voltage booster stops. S1 to 200 2 to 201 COM1 to 8, 313 to 320, COM9 to16 210 to 203 This is an input for a base voltage for voltage booster. < When voltage booster is used > Make sure to connect a capacitor between VBTI1 and VSS. REGE = VDD: Input the voltage from 4.5V to VDD[V] to VBTI1. VBTI1 244 to 248 REGE = VSS: Connect VBTI1 to VBTI2, and Input the voltage from 2.7V to VDD[V] to VBTI1. (When quadruple booster is used : VBTI1 ≤ 3.6V, When quintuple booster is used : VBTI1 ≤ 3.3V) < When voltage booster is not used > Make sure to open VBTI1. This is an input-output for a base voltage for voltage booster. < When voltage booster is used > Make sure to connect a capacitor between VBTI2 and VSS. REGE = VDD: VBTI2 outputs a base voltage for voltage booster. VBTI2 249 to 253 REGE = VSS: Connect VBTI1 to VBTI2, and Input the voltage from 2.7V to VDD[V] to VBTI1. (When quadruple booster is used : VBTI1 ≤ 3.6V, When quintuple booster is used : VBTI1 ≤ 3.3V) < When voltage booster is not used > Make sure to open VBTI2. These are Input-outputs for voltage booster. < When quadruple voltage booster is used > Make sure to connect a capacitor between CP1P(+) and CP12N(-). Make sure to connect a capacitor between CP2P(+) and CP12N(-). CP1P, 254 to 257, Make sure to connect a capacitor between CP3P(+) and CP34N(-). CP12N, 258 to 264, Make sure to connect CP4P and VLCD. CP2P, 265 to 268, CP3P, 269 to 272, CP34N, 273 to 279, Make sure to connect a capacitor between CP1P(+) and CP12N(-). CP4P 280 to 283 Make sure to connect a capacitor between CP2P(+) and CP12N(-). < When quintuple voltage booster is used > Make sure to connect a capacitor between CP3P(+) and CP34N(-). Make sure to connect a capacitor between CP4P(+) and CP34N(-). < When voltage booster is not used > Make sure to open CP1P, CP12N, CP2P, CP3P, CP34N and CP4P. Continued on next page. No.A2310-8/53 LC450210PCH Continued from preceding page. Handling Pad Name Pad No. Function Active I/O when unused This is a power supply for LCD driver block. Make sure to connect a capacitor between VLCD and VSS. < When voltage booster is used > VLCD 284 to 289 (i) When quadruple booster is used: VLCD outputs the booster voltage (VBTI2 4). (ii) When quintuple booster is used: VLCD outputs the booster voltage (VBTI2 5). - I/O - - I/O OPEN - I/O OPEN - I/O OPEN - I/O OPEN < When voltage booster is not used > Supply a voltage from 4.5V to 16.5V to VLCD. When contrast adjuster is used, follow a condition of VLCD ≥ VLCD0 + 2.4V. This is an input-output for the LCD drive bias voltage (High level). Make sure to connect a capacitor between VLCD0 and VLCD5. < When contrast adjuster is used > VLCD0 outputs the LCD drive bias voltage (High level) set by “Set of display contrast” VLCD0 290 to 294 instruction (CT0 to CT5). Follow a condition of VLCD0 ≤ VLCD - 2.4V. < When contrast adjuster is not used > Input the LCD drive bias voltage (High level) to VLCD0 from the outside, and follow a condition of VLCD1 < VLCD0 ≤ VLCD. This is an input-output for the LCD drive bias voltage (3/4 level, 4/5 level). Make sure to connect a capacitor between VLCD1 and VLCD5. < When LCD drive bias voltage generator is used > (i) When 1/4 bias is used: VLCD1 outputs the LCD drive bias voltage (3/4 VLCD0). (ii) When 1/5 bias is used: VLCD1 outputs the LCD drive bias voltage (4/5 VLCD0). VLCD1 306 to 308 < When LCD drive bias voltage generator is not used > (i) When 1/4 bias is used: Input the LCD drive bias voltage (3/4 VLCD0) to VLCD1 from the outside, and follow a condition of VLCD2 < VLCD1 < VLCD0. (ii) When 1/5 bias is used: Input the LCD drive bias voltage (4/5 VLCD0) to VLCD1 from the outside, and follow a condition of VLCD2 < VLCD1 < VLCD0. This is an input-output for the LCD drive bias voltage (2/4 level, 3/5 level). Make sure to connect a capacitor between VLCD2 and VLCD5. < When LCD drive bias voltage generator is used > (i) When 1/4 bias is used: VLCD2 outputs the LCD drive bias voltage (2/4 VLCD0). (ii) When 1/5 bias is used: VLCD2 outputs the LCD drive bias voltage (3/5 VLCD0). VLCD2 300 to 302 < When LCD drive bias voltage generator is not used > (i) When 1/4 bias is used: Input the LCD drive bias voltage (2/4 VLCD0) to VLCD2 from the outside, and follow a condition of VLCD4 < VLCD2 < VLCD1. (ii) When 1/5 bias is used: Input the LCD drive bias voltage (3/5 VLCD0) to VLCD2 from the outside, and follow a condition of VLCD3 < VLCD2 < VLCD1. This is an input-output for the LCD drive bias voltage (2/5 level). < When LCD drive bias voltage generator is used > (i) When 1/4 bias is used: Make sure to open VLCD3. (ii) When 1/5 bias is used: VLCD3 outputs the LCD drive bias voltage (2/5 VLCD0). Make sure to connect a capacitor between VLCD3 and VLCD3 303 to 305 VLCD5. < When LCD drive bias voltage generator is not used > (i) When 1/4 bias is used: Make sure to open VLCD3. (ii) When 1/5 bias is used: Make sure to connect a capacitor between VLCD3 and VLCD5. Input the LCD drive bias voltage (2/5 VLCD0) to VLCD3 from the outside, and follow a condition of VLCD4 < VLCD3 < VLCD2. Continued on next page. No.A2310-9/53 LC450210PCH Continued from preceding page. Handling Pad Name Pad No. Function Active I/O when unused This is an input-output for the LCD drive bias voltage (1/4 level, 1/5 level). Make sure to connect a capacitor between VLCD4 and VLCD5. < When LCD drive bias voltage generator is used > (i) When 1/4 bias is used: VLCD4 outputs the LCD drive bias voltage (1/4 VLCD0). (ii) When 1/5 bias is used: VLCD4 outputs the LCD drive bias voltage (1/5 VLCD0). VLCD4 309 to 311 < When LCD drive bias voltage generator is not used > - I/O OPEN - I VSS - I VSS H I (i) When 1/4 bias is used: Input the LCD drive bias voltage (1/4 VLCD0) to VLCD4 from the outside, and follow a condition of VLCD5 < VLCD4 < VLCD2. (ii) When 1/5 bias is used: Input the LCD drive bias voltage (1/5 VLCD0) to VLCD4 from the outside, and follow a condition of VLCD5 < VLCD4 < VLCD3. VLCD5 295 to 299 This is an input-output for the LCD drive bias voltage (Low level). Make sure to connect VLCD5 to VSS even if the LCD drive bias generator is not used. This is an input for the external clock, when external clock operating mode is selected. OSCI 221 By “Set of display method” instruction, OC = 0 (internal oscillator operating mode): Make sure to connect OSCI to VSS. OC = 1 (external clock operating mode): OSCI is used to input the external clock. CE 218 CL 220 DI 219 ____ RES 217 These are Inputs for transferring serial data. These pads are connected to a controller. CE: Chip enables. I CL: Synchronous clock. DI: Transfer data. This is an input for reset of this LSI. ____ RES = VSS: The state of this LSI is reset. VSS - I L I VSS - I VSS - O OPEN - O OPEN - - OPEN Refer to about the “System Reset”. ____ RES = VDD: Normal state. TSIN1 to TSIN4 TSOUT1 to TSOUT3 TSO 222 to 225 212 to 214 215 These are inputs for a test. Make sure to connect these pads to VSS. These are outputs for a test. Make sure to open these pads. These are output for a test. Make sure to open this pad. These are dummy pads. DUMMY 1, 202, 211, 312 These pads are not available. Don’t connect between dummy pads. Moreover, don’t use them with an external circuit. No.A2310-10/53 (SDIR = “1”) address direction PGA address Page (SDIR = “0”) Reversed direction 1 0 Normal direction Set of column D2_1 D2_2 D2_3 D2_4 D2_5 D2_6 D1_1 D1_2 D1_3 D1_4 D1_5 D1_6 D2_8 D2_9 D2_10 D2_11 D2_12 D2_13 D2_14 D2_15 D2_16 01H D1_8 D1_9 D1_10 D1_11 D1_12 D1_13 D1_14 D1_15 D1_16 00H D2_7 S199 S200 D1_7 S2 S1 02H D3_16 D3_15 D3_14 D3_13 D3_12 D3_11 D3_10 D3_9 D3_8 D3_7 D3_6 D3_5 D3_4 D3_3 D3_2 D3_1 S198 S3 03H D4_16 D4_15 D4_14 D4_13 D4_12 D4_11 D4_10 D4_9 D4_8 D4_7 D4_6 D4_5 D4_4 D4_3 D4_2 D4_1 S197 S4 04H D5_16 D5_15 D5_14 D5_13 D5_12 D5_11 D5_10 D5_9 D5_8 D5_7 D5_6 D5_5 D5_4 D5_3 D5_2 D5_1 S196 S5 05H D6_16 D6_15 D6_14 D6_13 D6_12 D6_11 D6_10 D6_9 D6_8 D6_7 D6_6 D6_5 D6_4 D6_3 D6_2 D6_1 S195 S6 Correspondence of RAM and Segment Output Pad 06H D7_16 D7_15 D7_14 D7_13 D7_12 D7_11 D7_10 D7_9 D7_8 D7_7 D7_6 D7_5 D7_4 D7_3 D7_2 D7_1 S194 S7 5H D193_6 D194_6 D195_6 D196_6 D197_6 D198_6 D199_6 D200_6 9H D9_10 D10_10 D193_10 D194_10 D195_10 D196_10 D197_10 D198_10 D199_10 D200_10 08H 09H C0H C1H C2H C3H C4H C5H C6H C7H D9_16 D10_16 D193_16 D194_16 D195_16 D196_16 D197_16 D198_16 D199_16 D200_16 FH D9_15 D10_15 D193_15 D194_15 D195_15 D196_15 D197_15 D198_15 D199_15 D200_15 EH D9_14 D10_14 D193_14 D194_14 D195_14 D196_14 D197_14 D198_14 D199_14 D200_14 DH D9_13 D10_13 D193_13 D194_13 D195_13 D196_13 D197_13 D198_13 D199_13 D200_13 CH D9_12 D10_12 D193_12 D194_12 D195_12 D196_12 D197_12 D198_12 D199_12 D200_12 BH D9_11 D10_11 D193_11 D194_11 D195_11 D196_11 D197_11 D198_11 D199_11 D200_11 AH D10_9 8H D9_9 7H 6H 4H D193_7 D194_7 D195_7 D196_7 D197_7 D198_7 D199_7 D200_7 3H S1 D193_5 D194_5 D195_5 D196_5 D197_5 D198_5 D199_5 D200_5 S2 S200 D193_4 D194_4 D195_4 D196_4 D197_4 D198_4 D199_4 D200_4 S3 S199 2H S4 S198 1H S5 S197 D193_3 D194_3 D195_3 D196_3 D197_3 D198_3 D199_3 D200_3 S6 S196 0H S7 S195 D193_2 D194_2 D195_2 D196_2 D197_2 D198_2 D199_2 D200_2 S8 S194 D193_1 D194_1 D195_1 D196_1 D197_1 D198_1 D199_1 D200_1 S193 D193_9 D194_9 D195_9 D196_9 D197_9 D198_9 D199_9 D200_9 D10_8 D10_7 D10_6 D10_5 D10_4 D10_3 D10_2 D10_1 S191 S10 D193_8 D194_8 D195_8 D196_8 D197_8 D198_8 D199_8 D200_8 D9_8 D9_7 D9_6 D9_5 D9_4 D9_3 D9_2 D9_1 S192 S9 Column address CRA0 to CRA7 07H D8_16 D8_15 D8_14 D8_13 D8_12 D8_11 D8_10 D8_9 D8_8 D8_7 D8_6 D8_5 D8_4 D8_3 D8_2 D8_1 S193 S8 Segment output pad Line LNA3 to LNA0 address LC450210PCH No.A2310-11/53 LC450210PCH Transfer Format of Serial Data This LSI has several internal registers. These internal registers are written by CCB interface. Structure of transfer bits consists of CCB address and instruction data. First 8 bits are CCB address. The subsequent bits are instruction data. The bit number of instruction data is different depending on an instruction, and these bits are from 16 bits to 272 bits. The serial data is taken by the positive edge of the CL signal, which is latched by the negative edge of the CE signal. When the number of data in CE=“High level” period is different from the defined number, LSI does not execute the instruction and holds the old state. For more information about the number of instruction data, refer to “Instruction Table”. (1) When CL is stopped at the low level CE CL DI 0 1 0 0 1 1 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D0 CCB address 8 bits (fixed) D1 D2 D3 D4 D270 D271 Instruction data 272 bits (Max.) (2) When CL is stopped at the high level CE CL DI 0 1 0 B0 B1 B2 0 1 1 0 B3 A0 A1 A2 CCB address 8 bits (fixed) 1 D0 D1 D2 D3 D4 D270 D271 A3 Instruction data 272 bits (Max.) • B0 to B3, A0 to A3 ········· CCB address is “B2H” • D0 to D271 ········· Instruction data (from 16 bits to 272 bits) No.A2310-12/53 D D D n+7 n+7 n+8 _m+14 _m+15 _m D D D n+8 n+8 n+8 _m+1 _m+2 _m+3 ··· ··· 0 1 0 DBC CTC CTC 0 1 0 0 0 0 0 DT0 DT1 DT2 DT3 0 0 DR WVC 0 1 0 0 1 1 0 0 0 0 SC0 SC1 0 0 DBF DBF DBF 0 1 2 0 BU 0 0 0 1 0 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 0 (Note.3) When the number of instruction data which want to execute is different from the number of transferred instruction data, the transferred instruction data is ignored. (Note.4) n=1 to 186, n+14=15 to 200, m=1, 9 (Note.5) n=1 to 185, n+15=16 to 200, m=1 (1) When voltage booster, contrast adjuster and LCD drive bias voltage generator are used (DBC=“1”, CTC0,CTC1=“1,1”), the stabilization time of these circuits is 200[msec]. (2) When contrast adjuster and LCD drive bias voltage generator are used (DBC=“0”, CTC0,CTC1=“1,1”), the stabilization time of these circuits is 20[msec]. (3) When LCD drive bias voltage generator is used (DBC=“0”, CTC0,CTC1=“0,1”), the stabilization time of this circuit is 20[msec]. * Refer from [Fig.5] to [Fig.9]. 0 0 0 0 1 FC0 FC1 FC2 FC3 CRA CRA CRA CRA CRA CRA CRA CRA PGA 0 4 5 6 7 0 1 2 3 LNA LNA LNA LNA 0 1 2 3 PNC 0 CDIR SDIR D D D D D D D D D D D D D D D D D D D D CRA CRA CRA CRA CRA CRA CRA CRA PGA 0 n+14 n+14 n+14 n+14 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 n+15 4 5 6 7 0 1 2 3 _m+12 _m+13 _m+14 _m+15 _m _m+1 _m+2 _m+3 _m+4 _m+5 _m+6 _m+7 _m+8 _m+9 _m+10 _m+11 _m+12 _m+13 _m+14 _m+15 D D D D D D D D D D D D n+13 n+13 n+13 n+13 n+14 n+14 n+14 n+14 n+14 n+14 n+14 n+14 _m+4 _m+5 _m+6 _m+7 _m _m+1 _m+2 _m+3 _m+4 _m+5 _m+6 _m+7 OC 0 1 0 1 0 1 D236 D237 D238 D239 D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 (Note.1) “Set of display method” instruction must be executed first. If voltage booster, contrast adjuster and LCD____ drive bias voltage generator are used, wait time shown from (1) to (3) is needed for stabilization of each circuit after having reset a system by RES =“Low level”. (Note.2) When power-saving mode is changed to normal mode (BU=“1” to “0”), wait time shown from (1) to (3) is needed for stabilization of each circuit. When normal mode is changed to power-saving mode (BU=“0” to “1”), secure a stop transition time (discharge time) more than 200[msec]. Set of display contrast Dn Dn Dn _m+1 _m+2 _m+3 Dn _m ··· Write display data to RAM (1616 bits in a lump) (Note.5) Dn Dn Dn _m+1 _m+2 _m+3 Write display data to RAM (815 bits in a lump) (Note.4) Dn _m ··· ··· ··· D126 D127 D128 D129 D130 D131 Set of line address ··· D3 D2 Control of display ON / OFF (Note.2) D1 D0 Set of display method (Note.1) Instruction Instruction Table 16 272 144 16 16 32 Total bits (Note.3) LC450210PCH No.A2310-13/53 LC450210PCH Explanation of Instruction Data 1. “Set of display method” instruction The display method is set by “Set of display method” instruction. ____ After having reset a system by RES=“Low level”, make sure to execute “Set of display method” first. Instruction data (32 bits) D240 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 OC 0 1 0 DBC CTC0 CTC1 0 DT0 DT1 DT2 DT3 DR WVC (LSB) 1 0 CDIR SDIR 1 0 (MSB) DBF0 DBF1 DBF2 (LSB) 0 (MSB) FC0 FC1 FC2 FC3 (LSB) 0 0 0 (MSB) (1-1) OC ··· This is control data to set a fundamental clock operating mode. Internal oscillator operating mode and external clock operating mode are set by this control data. When the internal oscillator operating mode is set, clock generator begins to run after power-saving mode is canceled (BU=“0”). OC Fundamental clock operating mode The state of OSCI 0 Internal oscillator operating mode Make sure to connect OSCI to VSS. 1 External clock operating mode Input the clock fCK from 100 to 600 [kHz]. (1-2) DBC ··· This is control data to set a state of voltage booster. Run or Stop of voltage booster is set by this control data. About the combination of DBC, CTC0 and CTC1, refer to the following table. (1-3) CTC0, CTC1 ··· These are control data to set a state of contrast adjuster and LCD drive bias voltage generator. Run or Stop of contrast adjuster and LCD drive bias voltage generator is set by these control data. About the combination of DBC, CTC0 and CTC1, refer to the following table. DBC CTC0 CTC1 Voltage booster Contrast adjuster LCD drive bias voltage generator 0 0 0 Stop Stop Stop 0 0 1 Stop Stop Run 0 1 0 Stop Run Stop 0 1 1 Stop Run Run Stop 1 0 0 Run Stop 1 0 1 Run Stop Run 1 1 0 Run Run Stop 1 1 1 Run Run Run No.A2310-14/53 1 LC450210PCH About the state of Voltage booster, VBTI1, VBTI2 and VLCD, refer to the following table. The state of The state of VBTI1 voltage booster The state of VBTI2 The state of VLCD Supply a voltage from Unused Make sure to open VBTI1. Make sure to open VBTI2. < REGE=VDD > < REGE=VDD > 4.5V to 16.5V to VLCD from the outside. Input the voltage from 4.5V to VDD[V] to VBTI2 outputs a base voltage for voltage VBTI1. booster. VLCD outputs the Quadruple voltage booster is used. < REGE=VSS > Connect VBTI1 to VBTI2. < REGE=VSS > (VBTI2 4) voltage Connect VBTI1 to VBTI2, and Input the voltage from 2.7V to VDD[V] (≤3.6V) to VBTI1. < REGE=VDD > < REGE=VDD > Input the voltage from 4.5V to VDD[V] to VBTI2 outputs a base voltage for voltage VBTI1. booster. VLCD outputs the Quintuple voltage booster is used. < REGE=VSS > Connect VBTI1 to VBTI2. < REGE=VSS > (VBTI2 5) voltage Connect VBTI1 to VBTI2, and Input the voltage from 2.7V to VDD[V] (≤3.3V) to VBTI1. (Note.1) During (1) or (2) time, voltage booster stops forcibly and is the discharge state. In the discharge state, the electric potential of VLCD is same as VBTI1. ____ (1) The period of RES=“Low level” (Regardless of the setting of voltage booster) (2) DBC=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by “Control of display ON / OFF” instruction. No.A2310-15/53 LC450210PCH (Note.2) The peripheral circuit of VBTI1, VBTI2, CP1P, CP12N, CP2P, CP3P, CP34N, CP4P and VLCD is as follows. Only changing the connection of CP4P, a multiple of the voltage booster is selectable. < 5V Power supply (REGE=VDD), Quadruple voltage booster is used (DBC=“1”) > +4.5V to VDD[V] (≤5.5V) Cbt VBTI1 VBTI2 +2.7V to VDD[V] (≤3.6V) Cbt D C1 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] C2 C3 + CP12N + + CP2P CP3P CP34N 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] VBTI1 VBTI2 C3 C4 Cvl + + + CP2P CP3P CP34N + CP4P D C1 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ C4 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] C2 C3 C4 Cvl CP12N CP2P CP3P Cvl + CP12N CP2P CP3P + + CP34N CP4P + VLCD + +2.7V to +3.6V VDD Cbt VBTI1 VBTI2 +4.5V to +16.5V CP1P + < 3V Power supply (REGE=VSS), Voltage booster is not used (DBC=“0”) > VDD open VLCD + VBTI1 VBTI2 CP1P 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] CP34N VBTI1 VBTI2 VLCD < 5V Power supply (REGE=VDD), Voltage booster is not used (DBC=“0”) > Cbt CP2P CP3P + + +2.7V to VDD[V] (≤3.3V) CP1P CP12N CP12N CP4P Cbt + +4.5V to +5.5V C3 CP1P + < 3V Power supply (REGE=VSS), Quintuple voltage boost is used (DBC=“1”) > Cbt C2 C2 Cvl +4.5V to VDD[V] (≤5.5V) 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ C4 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] C1 VLCD + C1 D CP1P < 5V Power supply (REGE=VDD), Quintuple voltage boost is used (DBC=“1”) > D VBTI1 VBTI2 Cbt CP4P Cvl Cbt < 3V Power supply (REGE=VSS), Quadruple voltage booster is used (DBC=“1”) > CP1P 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] open CP12N CP2P CP3P CP34N CP34N CP4P CP4P VLCD +4.5V to +16.5V Cvl + VLCD No.A2310-16/53 LC450210PCH About the state of contrast adjuster, LCD drive bias voltage generator and the state from VLCD1 to VLCD4, refer to the following table. The state of The state of LCD drive contrast adjuster bias voltage generator Unused Unused The state of VLCD0 The state from VLCD1 to VLCD4 Input LCD drive bias voltage (High level) to VLCD0 from the outside. Input LCD drive bias voltage (Middle level) to pads from VLCD1 to VLCD4 from the outside. (When 1/4 bias is used, make sure to open VLCD3.) VLCD0 outputs the LCD drive bias Use Unused voltage (High level) set by “Set of display Input LCD drive bias voltage (Middle level) to pads contrast” instruction (CT0 to CT5). Make from VLCD1 to VLCD4 from the outside. sure to connect a capacitor between (When 1/4 bias is used, make sure to open VLCD3.) VLCD0 and VLCD5. Pads from VLCD1 to VLCD4 outputs LCD drive bias Unused Input LCD drive bias voltage (High level) Use to VLCD0 from the outside. voltage (Middle level). Make sure to connect a capacitor between pads from VLCD1 to VLCD4 and VLCD5. (When 1/4 bias is used, make sure to open VLCD3.) Use Use VLCD0 outputs the LCD drive bias Pads from VLCD1 to VLCD4 outputs LCD drive bias voltage (High level) set by “Set of display voltage (Middle level). contrast” instruction (CT0 to CT5). Make Make sure to connect a capacitor between pads sure to connect a capacitor between from VLCD1 to VLCD4 and VLCD5. VLCD0 and VLCD5. (When 1/4 bias is used, make sure to open VLCD3.) (Note.1) During (1) or (2) or (3) time, contrast adjuster and LCD drive bias voltage generator stop forcibly, and are the discharge state. In the discharge state, the electric potential of VLCD0, VLCD1, VLCD2, VLCD3 and VLCD4 are same as VLCD5. ____ (1) The period of RES=“Low level” (Regardless of the setting of contrast adjuster and LCD drive bias voltage generator) (2) CTC0=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by “Control of display ON / OFF” instruction. (3) CTC1=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by “Control of display ON / OFF” instruction. (Note.2) When 1/4 bias is set (DR=“0”), set a peripheral circuit from VLCD0 to VLCD5 as follows. < Contrast adjuster and LCD drive bias voltage generator are used. (CTC0,CTC1=“1,1”) > VLCD0 Cvm open VLCD4 VLCD2 open VLCD3 VLCD4 VLCD5 0.1[F] ≤ Cvm ≤ 0.47[F] VLCD0 Cvm Cvm 0.1[F] ≤ Cvm ≤ 0.47[F] VLCD0 ≤ VLCD-2.4[V] VLCD1 Cvm VLCD5 < Contrast adjuster is used, and LCD drive bias voltage generator is not used. (CTC0,CTC1=“1,0”) > 1/4VLCD0[V] Cvm VLCD3 0.1[F] ≤ Cvm ≤ 0.47[F] VLCD0 ≤ VLCD-2.4[V] 2/4VLCD0[V] VLCD0 Cvm Cvm VLCD2 Cvm 3/4VLCD0[V] +4.5V to VLCD[V] VLCD1 Cvm Cvm < Contrast adjuster is not used, and LCD drive bias voltage generator is used. (CTC0,CTC1=“0,1”) > Cvm open Cvm < Contrast adjuster and LCD drive bias voltage generator are not used. (CTC0,CTC1=“0,0”) > +4.5V to VLCD[V] VLCD1 3/4VLCD0[V] VLCD2 2/4VLCD0[V] VLCD1 Cvm VLCD3 VLCD4 VLCD0 Cvm 1/4VLCD0[V] VLCD5 Cvm VLCD2 open Cvm VLCD3 VLCD4 VLCD5 0.1[F] ≤ Cvm ≤ 0.47[F] No.A2310-17/53 LC450210PCH (Note.3) When 1/5 bias is set (DR=“1”), set a peripheral circuit from VLCD0 to VLCD5 as follows. < Contrast adjuster is not used, and LCD drive bias voltage generator is used. (CTC0,CTC1=“0,1”) > < Contrast adjuster and LCD drive bias voltage generator are used. (CTC0,CTC1=“1,1”) > +4.5V to VLCD[V] VLCD0 Cvm VLCD1 Cvm Cvm VLCD5 VLCD0 Cvm Cvm Cvm 1/5VLCD0[V] VLCD5 0.1[F] ≤ Cvm ≤ 0.47[F] Cvm 2/5VLCD0[V] VLCD4 Cvm < Contrast adjuster is used, and LCD drive bias voltage generator is not used. (CTC0,CTC1=“1,0”) > 3/5VLCD0[V] VLCD3 Cvm VLCD4 0.1[F] ≤ Cvm ≤ 0.47[F] VLCD0 ≤ VLCD-2.4[V] 4/5VLCD0[V] VLCD2 Cvm VLCD3 Cvm VLCD1 Cvm VLCD2 Cvm VLCD0 Cvm Cvm < Contrast adjuster and LCD drive bias voltage generator are not used. (CTC0,CTC1=“0,0”) > +4.5V to VLCD[V] VLCD1 4/5VLCD0[V] VLCD2 3/5VLCD0[V] VLCD3 2/5VLCD0[V] VLCD4 1/5VLCD0[V] VLCD0 Cvm VLCD1 Cvm VLCD2 Cvm VLCD3 Cvm VLCD4 Cvm VLCD5 VLCD5 0.1[F] ≤ Cvm ≤ 0.47[F] 0.1[F] ≤ Cvm ≤ 0.47[F] VLCD0 ≤ VLCD-2.4[V] (1-4) DT0 to DT3 ··· These are control data to set duty from 1/8 to 1/16. Duty from 1/8 to 1/16 is set by these control data. The state from COM1 to COM16 DT0 DT1 DT2 DT3 Duty Pads which output scan pulse Pads which output pulse of display off Normal scan Reversed scan Normal scan Reversed scan CDIR = “0” CDIR = “1” CDIR = “0” CDIR = “1” 0 0 0 0 1/8 duty COM1 to COM8 COM16 to COM9 COM9 to COM16 COM8 to COM1 1 0 0 0 1/9 duty COM1 to COM9 COM16 to COM8 COM10 to COM16 COM7 to COM1 0 1 0 0 1/10 duty COM1 to COM10 COM16 to COM7 COM11 to COM16 COM6 to COM1 1 1 0 0 1/11 duty COM1 to COM11 COM16 to COM6 COM12 to COM16 COM5 to COM1 0 0 1 0 1/12 duty COM1 to COM12 COM16 to COM5 COM13 to COM16 COM4 to COM1 1 0 1 0 1/13 duty COM1 to COM13 COM16 to COM4 COM14 to COM16 COM3 to COM1 0 1 1 0 1/14 duty COM1 to COM14 COM16 to COM3 COM15, COM16 COM2, COM1 1 1 1 0 1/15 duty COM1 to COM15 COM16 to COM2 COM16 COM1 X X X 1 1/16 duty COM1 to COM16 COM16 to COM1 - - X: don’t care No.A2310-18/53 LC450210PCH (1-5) DR ··· This is control data to set 1/4 bias or 1/5 bias. 1/4 bias or 1/5 bias is set by this control data. DR Bias VLCD1 voltage VLCD2 voltage VLCD3 voltage VLCD4 voltage 0 1/4 bias 3/4 VLCD0 2/4 VLCD0 Make sure to open VLCD3 1/4 VLCD0 1 1/5 bias 4/5 VLCD0 3/5 VLCD0 2/5 VLCD0 1/5 VLCD0 (1-6) WVC ··· This is control data to set inversion drive of LCD drive waveform. Line inversion or frame inversion is set by this control data. WVC LCD drive waveform 0 Line inversion 1 Frame inversion (1-7) CDIR ··· This is control data to set scan direction of common outputs. Scan direction of common outputs is set by this control data. CDIR Scan direction of common outputs (COM1 COM2 COM3 ······ COM15 COM16) 0 Normal scan 1 Reversed scan (COM16 COM15 COM14 ······ COM2 COM1) (1-8) SDIR ··· This is control data to set a correspondence of a segment output and a column address of RAM. A correspondence of a segment output and a column address of RAM are set by this control data. Only just changing the setting of SDIR data does not change the display of LCD. When display data is written to RAM, column address of RAM is converted. Then display data is saved to there. SDIR Correspondence of a segment output and a column address of RAM Normal direction 0 (Column address “CRA0 to CRA7=00H, 01H, 02H, C5H, C6H, C7H” of RAM corresponds to segment output “S1, S2, S3, , S198, S199, S200”.) Reversed direction 1 (Column address “CRA0 to CRA7=00H, 01H, 02H, C5H, C6H, C7H” of RAM corresponds to segment output “S200, S199, S198, , S3, S2, S1”.) (1-9) DBF0 to DBF2 ··· These are control data to set clock frequency of voltage booster. A clock frequency of voltage booster is set by these control data. DBF0 DBF1 DBF2 Clock frequency of voltage booster (fcp) 0 0 0 fosc/12 or fCK/12 1 0 0 fosc/14 or fCK/14 0 1 0 fosc/18 or fCK/18 1 1 0 fosc/22 or fCK/22 0 0 1 fosc/26 or fCK/26 1 0 1 fosc/28 or fCK/28 0 1 1 fosc/30 or fCK/30 1 1 1 fosc/34 or fCK/34 No.A2310-19/53 LC450210PCH (1-10) FC0 to FC3 ··· These are control data to set frame frequency of common and segment output waveforms. A frame frequency of common and segment output waveforms are set by these control data. FC0 FC1 FC2 FC3 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 FC0 FC1 FC2 FC3 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 Frame frequency fo[Hz] 1/8 duty 1/9 duty 1/10 duty 1/11 duty 1/12 duty fosc(fCK)/4352 < 68.9[Hz] > fosc(fCK)/3712 < 80.8[Hz] > fosc(fCK)/2944 < 101.9[Hz] > fosc(fCK)/2368 < 126.7[Hz] > fosc(fCK)/1984 < 151.2[Hz] > fosc(fCK)/1696 < 176.9[Hz] > fosc(fCK)/1472 < 203.8[Hz] > fosc(fCK)/1312 < 228.7[Hz] > fosc(fCK)/1184 < 253.4[Hz] > fosc(fCK)/1088 < 275.7[Hz] > fosc(fCK)/1056 < 284.1[Hz] > fosc(fCK)/992 < 302.4[Hz] > fosc(fCK)/960 < 312.5[Hz] > fosc(fCK)/928 < 323.3[Hz] > fosc(fCK)/896 < 334.8[Hz] > fosc(fCK)/864 < 347.2[Hz] > fosc(fCK)/4320 < 69.4[Hz] > fosc(fCK)/3744 < 80.1[Hz] > fosc(fCK)/2952 < 101.6[Hz] > fosc(fCK)/2376 < 126.3[Hz] > fosc(fCK)/1944 < 154.3[Hz] > fosc(fCK)/1692 < 177.3[Hz] > fosc(fCK)/1476 < 203.3[Hz] > fosc(fCK)/1332 < 225.2[Hz] > fosc(fCK)/1188 < 252.5[Hz] > fosc(fCK)/1080 < 277.8[Hz] > fosc(fCK)/1044 < 287.4[Hz] > fosc(fCK)/1008 < 297.6[Hz] > fosc(fCK)/972 < 308.6[Hz] > fosc(fCK)/936 < 320.5[Hz] > fosc(fCK)/900 < 333.3[Hz] > fosc(fCK)/864 < 347.2[Hz] > fosc(fCK)/4320 < 69.4[Hz] > fosc(fCK)/3760 < 79.8[Hz] > fosc(fCK)/2960 < 101.4[Hz] > fosc(fCK)/2400 < 125.0[Hz] > fosc(fCK)/2000 < 150.0[Hz] > fosc(fCK)/1720 < 174.4[Hz] > fosc(fCK)/1480 < 202.7[Hz] > fosc(fCK)/1320 < 227.3[Hz] > fosc(fCK)/1200 < 250.0[Hz] > fosc(fCK)/1080 < 277.8[Hz] > fosc(fCK)/1040 < 288.5[Hz] > fosc(fCK)/1000 < 300.0[Hz] > fosc(fCK)/960 < 312.5[Hz] > fosc(fCK)/920 < 326.1[Hz] > fosc(fCK)/900 < 333.3[Hz] > fosc(fCK)/860 < 348.8[Hz] > fosc(fCK)/4400 < 68.2[Hz] > fosc(fCK)/3784 < 79.3[Hz] > fosc(fCK)/2992 < 100.3[Hz] > fosc(fCK)/2376 < 126.3[Hz] > fosc(fCK)/1936 < 155.0[Hz] > fosc(fCK)/1672 < 179.4[Hz] > fosc(fCK)/1496 < 200.5[Hz] > fosc(fCK)/1320 < 227.3[Hz] > fosc(fCK)/1188 < 252.5[Hz] > fosc(fCK)/1100 < 272.7[Hz] > fosc(fCK)/1056 < 284.1[Hz] > fosc(fCK)/990 < 303.0[Hz] > fosc(fCK)/946 < 317.1[Hz] > fosc(fCK)/924 < 324.7[Hz] > fosc(fCK)/902 < 332.6[Hz] > fosc(fCK)/858 < 349.7[Hz] > fosc(fCK)/4320 < 69.4[Hz] > fosc(fCK)/3744 < 80.1[Hz] > fosc(fCK)/2976 < 100.8[Hz] > fosc(fCK)/2400 < 125.0[Hz] > fosc(fCK)/1968 < 152.4[Hz] > fosc(fCK)/1728 < 173.6[Hz] > fosc(fCK)/1488 < 201.6[Hz] > fosc(fCK)/1320 < 227.3[Hz] > fosc(fCK)/1200 < 250.0[Hz] > fosc(fCK)/1104 < 271.7[Hz] > fosc(fCK)/1056 < 284.1[Hz] > fosc(fCK)/984 < 304.9[Hz] > fosc(fCK)/960 < 312.5[Hz] > fosc(fCK)/936 < 320.5[Hz] > fosc(fCK)/888 < 337.8[Hz] > fosc(fCK)/864 < 347.2[Hz] > 1/13 duty 1/14 duty 1/15 duty 1/16 duty fosc(fCK)/4264 < 70.4[Hz] > fosc(fCK)/3744 < 80.1[Hz] > fosc(fCK)/2964 < 101.2[Hz] > fosc(fCK)/2392 < 125.4[Hz] > fosc(fCK)/1976 < 151.8[Hz] > fosc(fCK)/1716 < 174.8[Hz] > fosc(fCK)/1482 < 202.4[Hz] > fosc(fCK)/1326 < 226.2[Hz] > fosc(fCK)/1196 < 250.8[Hz] > fosc(fCK)/1118 < 268.3[Hz] > fosc(fCK)/1040 < 288.5[Hz] > fosc(fCK)/988 < 303.6[Hz] > fosc(fCK)/962 < 311.9[Hz] > fosc(fCK)/936 < 320.5[Hz] > fosc(fCK)/884 < 339.4[Hz] > fosc(fCK)/858 < 349.7[Hz] > fosc(fCK)/4256 < 70.5[Hz] > fosc(fCK)/3808 < 78.8[Hz] > fosc(fCK)/2968 < 101.1[Hz] > fosc(fCK)/2408 < 124.6[Hz] > fosc(fCK)/1960 < 153.1[Hz] > fosc(fCK)/1708 < 175.6[Hz] > fosc(fCK)/1456 < 206.0[Hz] > fosc(fCK)/1316 < 228.0[Hz] > fosc(fCK)/1204 < 249.2[Hz] > fosc(fCK)/1092 < 274.7[Hz] > fosc(fCK)/1036 < 289.6[Hz] > fosc(fCK)/980 < 306.1[Hz] > fosc(fCK)/952 < 315.1[Hz] > fosc(fCK)/924 < 324.7[Hz] > fosc(fCK)/896 < 334.8[Hz] > fosc(fCK)/868 < 345.6[Hz] > fosc(fCK)/4320 < 69.4[Hz] > fosc(fCK)/3720 < 80.7[Hz] > fosc(fCK)/3000 < 100.0[Hz] > fosc(fCK)/2400 < 125.0[Hz] > fosc(fCK)/1980 < 151.5[Hz] > fosc(fCK)/1710 < 175.4[Hz] > fosc(fCK)/1500 < 200.0[Hz] > fosc(fCK)/1350 < 222.2[Hz] > fosc(fCK)/1200 < 250.0[Hz] > fosc(fCK)/1080 < 277.8[Hz] > fosc(fCK)/1050 < 285.7[Hz] > fosc(fCK)/990 < 303.0[Hz] > fosc(fCK)/960 < 312.5[Hz] > fosc(fCK)/930 < 322.6[Hz] > fosc(fCK)/900 < 333.3[Hz] > fosc(fCK)/870 < 344.8[Hz] > fosc(fCK)/4352 < 68.9[Hz] > fosc(fCK)/3712 < 80.8[Hz] > fosc(fCK)/2944 < 101.9[Hz] > fosc(fCK)/2368 < 126.7[Hz] > fosc(fCK)/1984 < 151.2[Hz] > fosc(fCK)/1696 < 176.9[Hz] > fosc(fCK)/1472 < 203.8[Hz] > fosc(fCK)/1312 < 228.7[Hz] > fosc(fCK)/1184 < 253.4[Hz] > fosc(fCK)/1088 < 275.7[Hz] > fosc(fCK)/1056 < 284.1[Hz] > fosc(fCK)/992 < 302.4[Hz] > fosc(fCK)/960 < 312.5[Hz] > fosc(fCK)/928 < 323.3[Hz] > fosc(fCK)/896 < 334.8[Hz] > fosc(fCK)/864 < 347.2[Hz] > Frame frequency fo[Hz] (Note.1) The value of “< >” is a frame frequency when fosc(fCK) is 300[kHz]. No.A2310-20/53 LC450210PCH 2. “Control of display ON / OFF” instruction A state of display is set by “Control of display ON / OFF” instruction. Instruction data (16 bits) D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 PNC 0 1 0 SC0 SC1 0 BU 0 0 1 0 0 0 1 0 (2-1) PNC ··· This is control data to set normal display or reversed display. Normal display or reversed display is set by this control data. When a state of display is ON (SC0, SC1=“0, 0”), the setting of PNC becomes effective. PNC Normal display or Reversed display Display data Dn_m=“0” Display data Dn_m=“1” 0 Normal display OFF ON 1 Reversed display ON OFF (Note.1) Display data “Dn_m” is from D1_1 to D200_16. (2-2) SC0, SC1 ··· These are control data to set a state of display. A state of display is set by these control data. SC0 SC1 The state of segment outputs The state of common outputs 0 0 The state of display ON Waveform corresponding to display data Scan pulse 1 0 All OFF OFF waveform Scan pulse 0 1 All ON ON waveform Scan pulse 1 1 All forced OFF VLCD5 level VLCD5 level (2-3) BU ··· This is control data to set normal mode or power-saving mode. Normal mode or power-saving mode (low current) is set by this control data. The state of BU Mode common and Voltage booster Contrast adjuster segment outputs 0 1 LCD drive bias voltage generator Normal display These circuits can run mode operation (depend on the setting of DBC,CTC0 and CTC1). mode VLCD5 level clock) Run Normal Power-saving Internal oscillator (Reception state of the external (The external clock reception is possible) Stop and Stop and Stop and Stop discharge discharge discharge (The external clock is not (Note.1) (Note.1) (Note.1) received.) (Note.1) During (1) or (2) or (3) or (4) time, voltage booster, contrast adjuster and LCD drive bias voltage generator stop forcibly. And____ each circuit is the discharge state. (1) The period of RES=“Low level” (Regardless of the setting of voltage booster, contrast adjuster or LCD drive bias voltage generator) In the discharge state, the electric potential of VLCD is same as VBTI1. And the electric potential of VLCD0, VLCD1, VLCD2, VLCD3 and VLCD4 are same as VLCD5. (2) DBC=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by “Control of display ON / OFF” instruction. In the discharge state, the electric potential of VLCD is same as VBTI1. (3) CTC0=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by “Control of display ON / OFF” instruction. In the discharge state, the electric potential of VLCD0 is same as VLCD5. (4) CTC1=“1” is set by “Set of display method” instruction, and power-saving mode (BU=“1”) is set by “Control of display ON / OFF” instruction. In the discharge state, the electric potential of VLCD1, VLCD2, VLCD3 and VLCD4 are same as VLCD5. (Note.2) When the setting is changed from normal mode to power-saving mode (BU=“0”“1”), secure a stop transition time more than 200 [msec]. When the setting is changed from power-saving mode to normal mode (BU=“1”“0”), a time shown from (1) to (3) is needed for stabilization of each circuit. (Refer to [Fig.9]) (1) When voltage booster, contrast adjuster and LCD drive bias voltage generator are used (DBC=“1”, CTC0,CTC1=“1,1”), the stabilization time of these circuits is 200 [msec]. (2) When contrast adjuster and LCD drive bias voltage generator are used (DBC=“0”, CTC0,CTC1=“1,1”), the stabilization time of these circuits is 20 [msec]. (3) When LCD drive bias voltage generator is used (DBC=“0”, CTC0,CTC1=“0,1”), the stabilization time of this circuit is 20 [msec]. No.A2310-21/53 LC450210PCH 3. “Set of line address” instruction A line address of RAM to specify a start display position is set by “Set of line address” instruction. Instruction data (16 bits) D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 LNA0 LNA1 LNA2 LNA3 0 0 0 0 0 1 0 0 0 0 1 1 (LSB) (MSB) (3-1) LNA0 to LNA3 ··· These are control data to set a line address of RAM. A line address of RAM to specify a start display position is set by these control data. (ex.1) When a line address is “8H”, the relation between the common output and RAM at the normal scan (CDIR=“0”) is as follows. Line address of RAM LSB A start display position MSB LNA0 LNA1 LNA2 LNA3 1/8 duty 1/9 duty 1/10 duty 1/11 duty 1/12 duty 1/13 duty 1/14 duty 1/15 duty 1/16 duty 0 0 0 1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 1 0 0 1 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 0 1 0 1 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 1 1 0 1 COM4 COM4 COM4 COM4 COM4 COM4 COM4 COM4 COM4 0 0 1 1 COM5 COM5 COM5 COM5 COM5 COM5 COM5 COM5 COM5 1 0 1 1 COM6 COM6 COM6 COM6 COM6 COM6 COM6 COM6 COM6 0 1 1 1 COM7 COM7 COM7 COM7 COM7 COM7 COM7 COM7 COM7 1 1 1 1 COM8 COM8 COM8 COM8 COM8 COM8 COM8 COM8 COM8 0 0 0 0 - COM9 COM9 COM9 COM9 COM9 COM9 COM9 COM9 1 0 0 0 - - COM10 COM10 COM10 COM10 COM10 COM10 COM10 0 1 0 0 - - - COM11 COM11 COM11 COM11 COM11 COM11 1 1 0 0 - - - - COM12 COM12 COM12 COM12 COM12 0 0 1 0 - - - - - COM13 COM13 COM13 COM13 1 0 1 0 - - - - - - COM14 COM14 COM14 0 1 1 0 - - - - - - - COM15 COM15 1 1 1 0 - - - - - - - - COM16 (ex.2) When a line address is “8H”, the relation between the common output and RAM at the reversed scan (CDIR=“1”) is as follows. Line address of RAM LSB A start display position MSB LNA0 LNA1 LNA2 LNA3 1/8 duty 1/9 duty 1/10 duty 1/11 duty 1/12 duty 1/13 duty 1/14 duty 1/15 duty 1/16 duty 0 0 0 1 COM16 COM16 COM16 COM16 COM16 COM16 COM16 COM16 COM16 1 0 0 1 COM15 COM15 COM15 COM15 COM15 COM15 COM15 COM15 COM15 0 1 0 1 COM14 COM14 COM14 COM14 COM14 COM14 COM14 COM14 COM14 1 1 0 1 COM13 COM13 COM13 COM13 COM13 COM13 COM13 COM13 COM13 0 0 1 1 COM12 COM12 COM12 COM12 COM12 COM12 COM12 COM12 COM12 1 0 1 1 COM11 COM11 COM11 COM11 COM11 COM11 COM11 COM11 COM11 0 1 1 1 COM10 COM10 COM10 COM10 COM10 COM10 COM10 COM10 COM10 1 1 1 1 COM9 COM9 COM9 COM9 COM9 COM9 COM9 COM9 COM9 0 0 0 0 - COM8 COM8 COM8 COM8 COM8 COM8 COM8 COM8 1 0 0 0 - - COM7 COM7 COM7 COM7 COM7 COM7 COM7 0 1 0 0 - - - COM6 COM6 COM6 COM6 COM6 COM6 1 1 0 0 - - - - COM5 COM5 COM5 COM5 COM5 0 0 1 0 - - - - - COM4 COM4 COM4 COM4 1 0 1 0 - - - - - - COM3 COM3 COM3 0 1 1 0 - - - - - - - COM2 COM2 1 1 1 0 - - - - - - - - COM1 No.A2310-22/53 LC450210PCH 4. “Write display data to RAM (8 15 bits in a lump)” instruction The page address and column address of RAM are set by the “Write display data to RAM (8 15 bits in a lump)” instruction. And the display data of “8 15 bits (8 common outputs 15 segment outputs)” are written to the specified page address and column address of RAM in a lump by this instruction. Instruction data (144 bits) D128 D129 D130 D131 D132 ······ Dn_m Dn_m+1 Dn_m+2 Dn_m+3 Dn_m+4 ······ D243 D244 D245 D246 D247 Dn+14_m+3 Dn+14_m+4 Dn+14_m+5 Dn+14_m+6 Dn+14_m+7 (Note.1) n=1 to 186, n+14=15 to 200, m=1, 9 Instruction data (continuance) D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 0 0 0 0 0 0 0 0 CRA0 CRA1 CRA2 CRA3 CRA4 CRA5 CRA6 CRA7 PGA (LSB) 0 0 0 0 1 0 0 (MSB) (4-1) CRA0 to CRA7 ··· These are control data to set a column address of RAM. The settable range of a column address from CRA0 to CRA7 is from 00H to C7H. When a column address is set more than BAH, display data is written from start position and the overflowed data from RAM is canceled. (4-2) PGA ··· This is control data to set a page address of RAM. (4-3) Dn_m, Dn_m+1 to Dn+14_m+7 ··· These are display data which are written to RAM. A start position of writing to RAM is set by PGA and the data from CRA0 to CRA7. (ex.1) When a page address PGA is set to 0 and a column address from CRA0 to CRA7 is set to 00H, the relation between instruction data and a direction of writing to RAM is as follows. Column address 0 Page address Start position of writing 00H 01H Dn_m Dn+1_m C7H 0EH Dn+14_m Dn_m+1 Dn+1_m+1 Dn+14_m+1 Dn_m+7 Dn+1_m+7 Dn+14_m+7 End position of writing display data RAM 1 (ex.2) When a page address PGA is set to 1 and a column address from CRA0 to CRA7 is set to BAH, the relation between instruction data and a direction of writing to RAM is as follows. Column address 00H 01H BAH BBH C7H Page address 0 Canceled display data Start position of writing 1 display data RAM Dn+13_m Dn+14_m Dn_m+1 Dn+1_m+1 Dn_m Dn+1_m Dn+13_m+1 Dn+14_m+1 Dn_m+7 Dn+1_m+7 Dn+13_m+7 Dn+14_m+7 End position of writing No.A2310-23/53 LC450210PCH 5. “Write display data to RAM (16 16 bits in a lump)” instruction The page address and column address of RAM are set by the “Write display data to RAM (16 16 bits in a lump)” instruction. And the display data of “16 16 bits (16 common outputs 16 segment outputs)” are written to the specified page address and column address of RAM in a lump by this instruction. Instruction data (272 bits) D0 D1 D2 D3 D4 ······ Dn_m Dn_m+1 Dn_m+2 Dn_m+3 Dn_m+4 ······ D251 D252 D253 D254 D255 Dn+15_m+11 Dn+15_m+12 Dn+15_m+13 Dn+15_m+14 Dn+15_m+15 (Note.1) n=1 to 185, n+15=16 to 200, m=1 Instruction data (continuance) D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 CRA0 CRA1 CRA2 CRA3 CRA4 CRA5 CRA6 CRA7 PGA (LSB) 0 0 0 0 1 0 1 (MSB) (5-1) CRA0 to CRA7 ··· These are control data to set a column address of RAM. The settable range of a column address from CRA0 to CRA7 is from 00H to C7H. When a column address is set more than B9H, display data is written from start position and the overflowed data from RAM is canceled. (5-2) PGA ··· This is control data to set a page address of RAM. When PGA is set to 1, display data is written from start position and the overflowed data from RAM is canceled. (5-3) Dn_m, Dn_m+1 to Dn+15_m+15 ··· These are display data which are written to RAM. The start position of writing to RAM is set by PGA and the data from CRA0 to CRA7. (ex.1) When a page address PGA is set to 0 and a column address from CRA0 to CRA7 is set to 04H, the relation between instruction data and a direction of writing to RAM is as follows. Column address 00H 01H 02H 03H Page address 0 Start position of writing 04H 05H 13H C7H Dn_m Dn+1_m Dn+15_m Dn_m+1 Dn+1_m+1 Dn+15_m+1 display data RAM 1 Dn_m+15 Dn+1_m+15 Dn+15_m+15 End position of writing (ex.2) When a page address PGA is set to 1 and a column address from CRA0 to CRA7 is set to B9H, the relation between instruction data and a direction of writing to RAM is as follows. Column address 00H 01H 02H 03H B9H BAH C7H Page address 0 1 Canceled display data display data RAM Start position of writing Dn_m Dn+1_m Dn+14_m Dn+15_m Dn_m+1 Dn+1_m+1 Dn+14_m+1 Dn+15_m+1 Dn_m+7 Dn+1_m+7 Dn+14_m+7 Dn_m+8 Dn+1_m+8 Dn+14_m+8 Dn_m+15 Dn+1_m+15 Dn+14_m+15 End position of writing Canceled display data Dn+15_m+7 No.A2310-24/53 LC450210PCH 6. “Set of display contrast” instruction When contrast adjuster is used, LCD drive bias voltage VLCD0 (High level) is set by “Set of display contrast” instruction. Instruction data (16 bits) D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 0 1 0 1 1 0 (LSB) (MSB) (6-1) CT0 to CT5 ··· These are control data to set a display contrast. LCD drive bias voltage VLCD0 (High level) is set by these control data. Follow a condition of VLCD0 ≤ VLCD - 2.4[V]. (Reference example: from (ex.1) to (ex.4)) (ex.1) VBTI1=VBTI2=3.3V, REGE=VSS, Quintuple voltage booster and contrast adjuster are used. VLCD0 [V] (ex.2) VBTI1=5.0V, REGE=VDD, VBTI2=3.2V (Output, Typ.), Quintuple voltage booster and contrast adjuster are used. VLCD0 [V] VBTI2 5=16.50 VLCD VBTI2 x 5=16.00 14.10 13.60 13.50 4.65 4.65 63 0 0 4 Value from CT0 to CT5 63 Value from CT0 to CT5 (ex.3) VBTI1=VBTI2=3.0V, REGE=VSS, Quintuple voltage booster and contrast adjuster are used. VLCD0 [V] VBTI2 5=15.00 (ex.4) VBTI1=5.0V, REGE=VDD, VBTI2=3.2V (Output, Typ.), Quadruple voltage booster and contrast adjuster are used. VLCD0 [V] 2.4V VLCD 12.60 VBTI2 4=12.80 2.4V 10.40 10.35 4.65 4.65 0 VLCD 2.4V 10 Value from CT0 to CT5 63 0 25 VLCD 63 Value from CT0 to CT5 No.A2310-25/53 LC450210PCH Step voltage of LCD drive bias VLCD0 (High level) (Step voltage width: 0.15V (fixed)) Step CT0 CT1 CT2 CT3 CT4 CT5 VLCD0 level (High level) Step CT0 CT1 CT2 CT3 CT4 CT5 VLCD0 level (High level) 0 0 0 0 0 0 0 14.10 V 32 0 0 0 0 0 1 9.30 V 1 1 0 0 0 0 0 13.95 V 33 1 0 0 0 0 1 9.15 V 2 0 1 0 0 0 0 13.80 V 34 0 1 0 0 0 1 9.00 V 3 1 1 0 0 0 0 13.65 V 35 1 1 0 0 0 1 8.85 V 4 0 0 1 0 0 0 13.50 V 36 0 0 1 0 0 1 8.70 V 5 1 0 1 0 0 0 13.35 V 37 1 0 1 0 0 1 8.55 V 6 0 1 1 0 0 0 13.20 V 38 0 1 1 0 0 1 8.40 V 7 1 1 1 0 0 0 13.05 V 39 1 1 1 0 0 1 8.25 V 8 0 0 0 1 0 0 12.90 V 40 0 0 0 1 0 1 8.10 V 9 1 0 0 1 0 0 12.75 V 41 1 0 0 1 0 1 7.95 V 10 0 1 0 1 0 0 12.60 V 42 0 1 0 1 0 1 7.80 V 11 1 1 0 1 0 0 12.45 V 43 1 1 0 1 0 1 7.65 V 12 0 0 1 1 0 0 12.30 V 44 0 0 1 1 0 1 7.50 V 13 1 0 1 1 0 0 12.15 V 45 1 0 1 1 0 1 7.35 V 14 0 1 1 1 0 0 12.00 V 46 0 1 1 1 0 1 7.20 V 15 1 1 1 1 0 0 11.85 V 47 1 1 1 1 0 1 7.05 V 16 0 0 0 0 1 0 11.70 V 48 0 0 0 0 1 1 6.90 V 17 1 0 0 0 1 0 11.55 V 49 1 0 0 0 1 1 6.75 V 18 0 1 0 0 1 0 11.40 V 50 0 1 0 0 1 1 6.60 V 19 1 1 0 0 1 0 11.25 V 51 1 1 0 0 1 1 6.45 V 20 0 0 1 0 1 0 11.10 V 52 0 0 1 0 1 1 6.30 V 21 1 0 1 0 1 0 10.95 V 53 1 0 1 0 1 1 6.15 V 22 0 1 1 0 1 0 10.80 V 54 0 1 1 0 1 1 6.00 V 23 1 1 1 0 1 0 10.65 V 55 1 1 1 0 1 1 5.85 V 24 0 0 0 1 1 0 10.50 V 56 0 0 0 1 1 1 5.70 V 25 1 0 0 1 1 0 10.35 V 57 1 0 0 1 1 1 5.55 V 26 0 1 0 1 1 0 10.20 V 58 0 1 0 1 1 1 5.40 V 27 1 1 0 1 1 0 10.05 V 59 1 1 0 1 1 1 5.25 V 28 0 0 1 1 1 0 9.90 V 60 0 0 1 1 1 1 5.10 V 29 1 0 1 1 1 0 9.75 V 61 1 0 1 1 1 1 4.95 V 30 0 1 1 1 1 0 9.60 V 62 0 1 1 1 1 1 4.80 V 31 1 1 1 1 1 0 9.45 V 63 1 1 1 1 1 1 4.65 V No.A2310-26/53 LC450210PCH 4 3 2 1 n n-1 n-2 n-3 4 2 3 n 1 n-1 n-2 n-3 4 2 3 1 1/8 to 1/16 Duty, 1/4 bias, Line inversion (DR=“0”, WVC=“0”, CDIR=“0”) VLCD0 VLCD1 COM1 VLCD4 VLCD5 VLCD0 VLCD1 COM2 VLCD4 VLCD5 VLCD0 VLCD1 COM3 VLCD4 VLCD5 VLCD0 VLCD1 COM(n-1) VLCD4 VLCD5 VLCD0 VLCD1 COM(n) VLCD4 VLCD5 VLCD0 Segment driver output when all LCD segments are off VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM1 is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM2 is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM1 and COM3 is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM(n-1) is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM(n) is on VLCD2 VLCD5 VLCD0 Segment driver output when all LCD segments are on VLCD2 VLCD5 To/n To Frame frequency: fo=1/To 1/n duty (n is integer from 8 to 16) (Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display method” instruction. No.A2310-27/53 LC450210PCH 4 3 2 1 n n-1 n-2 n-3 4 2 3 n 1 n-1 n-2 n-3 4 2 3 1 1/8 to 1/16 Duty, 1/5 bias, Line inversion (DR=“1”, WVC=“0”, CDIR=“0”) VLCD0 VLCD1 COM1 VLCD4 VLCD5 VLCD0 VLCD1 COM2 VLCD4 VLCD5 VLCD0 VLCD1 COM3 VLCD4 VLCD5 VLCD0 VLCD1 COM(n-1) VLCD4 VLCD5 VLCD0 VLCD1 COM(n) VLCD4 VLCD5 VLCD0 Segment driver output when all LCD segments are off VLCD2 VLCD3 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM1 is on VLCD2 VLCD3 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM2 is on VLCD2 VLCD3 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM1 and COM3 is on VLCD2 VLCD3 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM(n-1) is on VLCD2 VLCD3 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM(n) is on VLCD2 VLCD3 VLCD5 VLCD0 Segment driver output when all LCD segments are on VLCD2 VLCD3 VLCD5 To/n To Frame frequency: fo=1/To 1/n duty (n is integer from 8 to 16) (Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display method” instruction. No.A2310-28/53 LC450210PCH n-3 n-2 n-1 n 1 2 3 n-3 n-2 n-1 n 1 2 3 4 5 1 2 3 4 5 n-3 n-2 n-1 n 1 2 3 4 5 1/8 to 1/16 Duty, 1/4 bias, Frame inversion (DR=“0”, WVC=“1”, CDIR=“0”) VLCD0 VLCD1 COM1 VLCD4 VLCD5 VLCD0 VLCD1 COM2 VLCD4 VLCD5 VLCD0 VLCD1 COM3 VLCD4 VLCD5 VLCD0 VLCD1 COM(n-1) VLCD4 VLCD5 VLCD0 VLCD1 COM(n) VLCD4 VLCD5 VLCD0 Segment driver output when all LCD segments are off VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM1 is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM2 is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM1 and COM3 is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM(n-1) is on VLCD2 VLCD5 VLCD0 Segment driver output when LCD segment corresponding to COM(n) is on VLCD2 VLCD5 VLCD0 Segment driver output when all LCD segments are on VLCD2 VLCD5 To/n To/n To To Frame frequency: fo=1/To 1/n duty (n is integer from 8 to 16) (Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display method” instruction. No.A2310-29/53 LC450210PCH n-3 n-2 n-1 n 1 2 3 n-3 n-2 n-1 n 1 2 3 4 5 1 2 3 4 5 n-3 n-2 n-1 n 1 2 3 4 5 1/8 to 1/16 Duty, 1/5 bias, Frame inversion (DR=“1”, WVC=“1”, CDIR=“0”) VLCD0 VLCD1 COM1 VLCD4 VLCD5 VLCD0 VLCD1 COM2 VLCD4 VLCD5 VLCD0 VLCD1 COM3 VLCD4 VLCD5 VLCD0 VLCD1 COM(n-1) VLCD4 VLCD5 VLCD0 VLCD1 COM(n) VLCD4 VLCD5 VLCD0 Segment driver output when all LCD segments are off VLCD2 VLCD3 Segment driver output when LCD segment corresponding to COM1 is on VLCD2 VLCD3 Segment driver output when LCD segment corresponding to COM2 is on VLCD2 VLCD3 Segment driver output when LCD segment corresponding to COM1 and COM3 is on VLCD2 VLCD3 Segment driver output when LCD segment corresponding to COM(n-1) is on VLCD2 VLCD3 Segment driver output when LCD segment corresponding to COM(n) is on VLCD2 VLCD3 Segment driver output when all LCD segments are on VLCD2 VLCD3 VLCD5 VLCD0 VLCD5 VLCD0 VLCD5 VLCD0 VLCD5 VLCD0 VLCD5 VLCD0 VLCD5 VLCD0 VLCD5 To/n To/n To To Frame frequency: fo=1/To 1/n duty (n is integer from 8 to 16) (Note.1) The duty and frame frequency “fo” are set by DT0, DT1, DT2, DT3, FC0, FC1, FC2 and FC3 in “Set of display method” instruction. No.A2310-30/53 LC450210PCH ____ Caution About Using CE, CL, DI, RES and OSCI with 5V signal ____ When CE, CL, DI, RES and OSCI are input the 5V signal, these input pads must be observed following points to prevent destruction. ____ (1) Supply VDD (power supply for logic block) before inputting 5V signal to CE, CL, DI, RES and OSCI. ____ (2) Input 0V to CE, CL, DI, RES and OSCI before shutting down VDD (power supply for logic block). Peripheral Circuit of OSCI (1) Internal oscillator operating mode (OC=“0”) When internal oscillator operating mode is set, make sure to connect OSCI to VSS. OSCI (2) External clock operating mode (OC=“1”) When external clock operating mode is set, make sure to input the clock (fCK: 100 to 600 [kHz]) to OSCI from the outside. External clock output pad OSCI External oscillator No.A2310-31/53 LC450210PCH Power Supply Sequence The following sequence must be observed when power supply is supplied and shut down. (Refer from [Fig.5] to [Fig.8]) When voltage booster is used < 5V power supply REGE=VDD > (1) When power supply is supplied: Supply VDD (power supply for logic block). Input a base voltage for voltage booster to VBTI1 after wait time for inputting voltage ( 0). Reset ____ cancellation with RES=“High level” (Reset pulse width ( 1[msec])). Wait time for inputting serial data ( 1[msec]). Set DBC to 1 by “Set of display method” instruction. (2) When power supply is shut down: Set BU to 1 by “Control of display ON / OFF” instruction. ____ Wait for stop transition time of each circuit ( 200[msec]). Reset with RES=“Low level”. Stop inputting a base voltage for voltage booster to VBTI1. Wait time for shutting down the power supply ( 0). Shut down VDD (power supply for logic block). < 3V power supply REGE=VSS > (1) When power supply is supplied: Supply VDD (power supply for logic block). Input a base voltage for ____ voltage booster to VBTI1 and VBTI2 after wait time for inputting voltage ( 0). Reset cancellation with RES=“High level” (Reset pulse width ( 1[msec])). Wait time for inputting serial data ( 1[msec]). Set DBC to 1 by “Set of display method” instruction. (2) When power supply is shut down: Set BU to 1 by “Control of display ON / OFF” instruction. ____ Wait for stop transition time of each circuit ( 200[msec]). Reset with RES=“Low level”. Stop inputting a base voltage for voltage booster to VBTI1 and VBTI2. Wait time for shutting down the power supply ( 0). Shut down VDD (power supply for logic block). When voltage booster is not used (1) When power supply is supplied: Supply VDD (power supply ____for logic block). Reset cancellation with RES=“High level” (Reset pulse width ( 1[msec])). Wait time for supplying voltage and wait time for inputting serial data ( 1[msec]). Supply VLCD (power supply for LCD driver block). Set DBC to 0 by “Set of display method” instruction. (2) When power supply is shut down: Set BU to 1 by “Control of display ON / OFF” instruction. Wait for stop transition time of each circuit ( 200[msec]). Shut down VLCD (power supply for LCD driver block). Wait time for a reset ( 0). ____ Reset with RES=“Low level”. Wait time for shutting down the power supply ( 0). Shut down VDD (power supply for logic block). (Note.1) Make sure to open VBTI1, VBTI2, CP1P, CP12N, CP2P, CP3P, CP34N and CP4P. After the following page, examples of power supply sequence and set or cancel the power-saving mode during supplying power. No.A2310-32/53 LC450210PCH (ex.1) Voltage booster, contrast adjuster and LCD drive bias voltage generator are used. twres t4 VDD (Power) t5 t6 t11 t9 ____ RES (Input) VIH1 VIL1 t2 VBTI1 (Input) VLCD (Output) VLCD0 (Output) VBTI2 5, VBTI2 4 VBTI1 VBTI1 Voltage booster is running. VLCD5 VLCD5 Contrast adjuster is running. VLCD1 to VLCD4 (Output) VLCD5 VLCD5 LCD drive bias voltage generator is running. Internal oscillator (Internal oscillator operating mode) Stop Stop Run OSCI (Input) (External clock operating mode) External clock receiver (External clock operating mode) State of display (common and segment output pads) Instruction Disable Enable Disable ON All forced OFF : Fixed low level(VLCD5) (1) (2)(3) (4) (5) All forced OFF : Fixed low level(VLCD5) (6) Instruction (1) “Set of display method” is executed. (DBC=“1”, CTC0, CTC1=“1, 1”) Make sure to execute “Set of display method” first. When external clock operating mode is set, make sure to set OC to 1. (2) “Set of display contrast” is executed. (3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a lump)” is executed. (4) “Set of line address” is executed. (5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”) (6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”) Constraint on the timing Reset pulse width Wait time for inputting voltage Wait time for inputting serial data Stabilization time of voltage booster, contrast adjuster and LCD drive bias voltage generator Wait time for display on Stop transition time of voltage booster, contrast adjuster and LCD drive bias voltage generator Wait time for shutting down the power supply : twres 1[msec] : t2 0 : t9 1 [msec] : t4 200 [msec] : t5 > 0 : t6 200 [msec] : t11 0 [Fig.5] No.A2310-33/53 LC450210PCH (ex.2) VLCD (power supply for LCD driver block) is supplied from the outside. Contrast adjuster and LCD drive bias voltage generator are used. twres t12 VDD (Power) ____ RES (Input) t5 t13 t11 t9 VIH1 VIL1 VIL1 t18 VLCD (Power) Supplied from the outside. t10 VLCD0 (Output) VLCD5 VLCD5 Contrast adjuster is running. VLCD1 to VLCD4 (Output) VLCD5 VLCD5 LCD drive bias voltage generator is running. Internal oscillator (Internal oscillator operating mode) Stop Run Stop Enable Disable OSCI (Input) (External clock operating mode) External clock receiver (External clock operating mode) State of display (common and segment output pads) Instruction Disable ON All forced OFF : Fixed low level(VLCD5) (1) (2) (3) (4) (5) All forced OFF : Fixed low level(VLCD5) (6) Instruction (1) “Set of display method” is executed. (DBC=“0”, CTC0, CTC1=“1, 1”) Make sure to execute “Set of display method” first. When external clock operating mode is set, make sure to set OC to 1. (2) “Set of display contrast” is executed. (3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a lump)” is executed. (4) “Set of line address” is executed. (5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”) (6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”) Constraint on the timing Reset pulse width Wait time for supplying voltage Wait time for inputting serial data Stabilization time of contrast adjuster and LCD drive bias voltage generator Wait time for display on Stop transition time of contrast adjuster and LCD drive bias voltage generator Wait time for shutting down the power supply Wait time for a reset : twres 1 [msec] : t10 1 [msec] : t9 1 [msec] : t12 20 [msec] : t5 > 0 : t13 200 [msec] : t11 0 : t18 > 0 Follow a condition of VLCD VLCD0 > VLCD1 > VLCD2 > VLCD3 > VLCD4 > VLCD5. [Fig.6] No.A2310-34/53 LC450210PCH (ex.3) VLCD (power supply for LCD driver block) is supplied from the outside. Contrast adjuster is not used, and VLCD0 is input from the outside. LCD drive bias voltage generator is used. twres t12 t5 t13 t11 VDD (Power) t9 ____ RES (Input) VIH1 VIL1 VIL1 t18 VLCD (Power) Supplied from the outside. t10 VLCD0 (Input) Input from the outside. VLCD1 to VLCD4 (Output) VLCD5 VLCD5 LCD drive bias voltage generator is running. Internal oscillator (Internal oscillator operating mode) Stop Run Stop Enable Disable OSCI (Input) (External clock operating mode) External clock receiver (External clock operating mode) State of display (common and segment output pads) Instruction Disable All forced OFF : Fixed low level(VLCD5) (1) (2) (3) (4) All Forced OFF : Fixed low level(VLCD5) ON (5) (6) Instruction (1) “Set of display method” is executed. (DBC=”0”, CTC0, CTC1=”0, 1”) Make sure to execute “Set of display method” first. When external clock operating mode is set, make sure to set OC to 1. (2) “Set of display contrast” is executed. (3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a lump)” is executed. (4) “Set of line address” is executed. (5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”) (6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”) Constraint on the timing Reset pulse width Wait time for supplying voltage Wait time for inputting serial data Stabilization time of LCD drive bias voltage generator Wait time for display on Stop transition time of LCD drive bias voltage generator Wait time for shutting down the power supply Wait time for a reset : twres 1 [msec] : t10 1 [msec] : t9 1 [msec] : t12 20 [msec] : t5 > 0 : t13 200 [msec] : t11 0 : t18 > 0 Follow a condition of VLCD VLCD0 > VLCD1 > VLCD2 > VLCD3 > VLCD4 > VLCD5. [Fig.7] No.A2310-35/53 LC450210PCH (ex.4) VLCD (power supply for LCD driver block) is supplied from the outside. Contrast adjuster and LCD drive bias voltage generator are not used. From VLCD0 to VLCD4 is input from the outside. twres t14 t5 t15 t11 VDD (Power) t9 ____ RES (Input) VIH1 VIL1 VIL1 t18 VLCD (Power) Supplied from the outside. t10 VLCD0 (Input) Input from the outside. VLCD1 to VLCD4 (Input) VLCD1 to VLCD4 is input from the outside. Internal oscillator (Internal oscillator operating mode) Stop Run Stop Enable Disable OSCI (Input) (External clock operating mode) External clock receiver (External clock operating mode) State of display (common and segment output pads) Instruction Disable ON All forced OFF : Fixed low level(VLCD5) (1) (2) (3) (4) (5) All Forced OFF : Fixed low level(VLCD5) (6) Instruction (1) “Set of display method” is executed. (DBC=“0”, CTC0, CTC1=“0, 0”) Make sure to execute “Set of display method” first. When external clock operating mode is set, make sure to set OC to 1. (2) “Set of display contrast” is executed. (3) “Write display data to RAM (815 bits in a lump)” or “Write display data to RAM (1616 bits in a lump)” is executed. (4) “Set of line address” is executed. (5) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”) (6) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”) Constraint on the timing Reset pulse width Wait time for supplying voltage Wait time for inputting serial data Stabilization time of external power supply Wait time for display on Stop transition time of external power supply Wait time for shutting down the power supply Wait time for a reset : twres 1 [msec] : t10 1 [msec] : t9 1 [msec] : t14 Stabilization time of external power supply : t5 > 0 : t15 Stop time of external power supply : t11 0 : t18 > 0 Follow a condition of VLCD VLCD0 > VLCD1 > VLCD2 > VLCD3 > VLCD4 > VLCD5. [Fig.8] No.A2310-36/53 LC450210PCH (ex.5) Power-saving mode is set and canceled. (Voltage booster, contrast adjuster and LCD drive bias voltage generator are used.) Power-saving mode t4 t16 t5 5.0V VDD (Power) High level ____ RES (Input) 5.0V VBTI1 (Input) VBTI2 5, VBTI2 4 VBTI2 5, VBTI2 4 VLCD (Output) VBTI1 Voltage booster is running. Voltage booster is running. VLCD0 VLCD0 VLCD0 (Output) VLCD5 Contrast adjuster is running. VLCD1 to VLCD4 (Output) Contrast adjuster is running. VLCD5 LCD drive bias voltage generator is running. LCD drive bias voltage generator is running. Internal oscillator (Internal oscillator operating mode) Run Stop Run Disable Enable OSCI (Input) (External clock operating mode) External clock receiver (External clock operating mode) Enable State of display (common and segment output pads) ON ON All forced OFF : Fixed low level(VLCD5) (1) Instruction (2) (3) Instruction (1) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“1”) (2) “Control of display ON / OFF” is executed. (SC0, SC1=“1, 1”, BU=“0”) (3) “Control of display ON / OFF” is executed. (SC0, SC1=“0, 0”, BU=“0”) Constraint on the timing Stabilization time of voltage booster, contrast adjuster and LCD drive bias voltage generator : t4 200 [msec] Stop transition time of voltage booster, contrast adjuster and LCD drive bias voltage generator : t16 200 [msec] Wait time for display on : t5 > 0 [Fig.9] No.A2310-37/53 LC450210PCH System Reset 1. Reset function ____ This LSI can reset the system by RES pad. 2. State of each block during reset (1) CLOCK GENERATOR, TIMING GENERATOR ____ These circuits are initialized forcibly during reset ( RES=“Low level”). (2) INSTRUCTION REGISTER & DECODER, CCB INTERFACE, SHIFT REGISTER ____ Contents of these circuits are initialized forcibly, and these circuits don't accept serial data during reset ( RES =“Low level”). (3) ADDRESS COUNTOR ____ Contents of this circuit are initialized forcibly during reset ( RES=“Low level”). (4) DISPLAY DATA RAM Contents of RAM are not affected by reset. (5) LATCH Contents of LATCH are not affected by reset. (6) COMMON DRIVER, SEGMENT DRIVER Common drivers and segment drivers output VLCD5 level, the display of LCD is forced OFF during reset ____ ( RES=“Low level”). (7) VOLTAGE BOOSTER ____ Voltage booster stops, and the electric potential of VLCD is same as VBTI1 during reset ( RES=“Low level”). (8) CONTRAST ADJUSTER ____ Contrast adjuster stops, and the electric potential of VLCD0 is same as VLCD5 during reset ( RES=“Low level”). (9) LCD DRIVE BIAS VOLTAGE GENERATOR LCD drive bias voltage generator stops, and the electric potential of VLCD1, VLCD2, VLCD3 and VLCD4 are ____ same as VLCD5 during reset ( RES=“Low level”). No.A2310-38/53 LC450210PCH 3. The state of PAD during reset The state during reset PAD The state during reset VLCD1 VLCD5 VLCD2 VLCD5 VLCD5 VLCD VBTI1 VLCD3 VLCD5 VLCD0 VLCD5 VLCD4 VLCD5 COM1 S200 VLCD5 COM1 to COM16 COM16 S1 to S200 S1 PAD REGE VBTI1 VBTI2 CP1P CP12N CP2P CP3P CP34N CP4P VOLTAGE BOOSTER COMMON DRIVER SEGMENT DRIVER LACTH VLCD CONTRAST ADJUSTER DISPLAY DATA ADDRESS VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD5 RAM COUNTER LCD DRIVE BIAS VOLTAGE GENERATOR ( 16 200 bits ) INSTRUCTION REGISTER & DECODER SHIFT REGISTER ____ RES VDD TIMING GENERATOR REGULATOR CLOCK GENERATOR VSS CCB INTERFACE TSIN1 to 4 TSOUT1 to 3 CE CL DI OSCI VLOGIC TSO The reset block No.A2310-39/53 LC450210PCH Sample Circuits Sample circuits are as follows. LCD drive bias Duty Bias VDD VLCD Voltage booster Contrast adjuster voltage generator Sample circuit (1) 1/8 to 1/16 1/5 5.0V Sample circuit (2) 1/8 to 1/16 1/5 5.0V Sample circuit (3) 1/8 to 1/16 1/5 3.0V Sample circuit (4) 1/8 to 1/16 1/5 5.0V VLCD is not supplied Quintuple from the outside. voltage boost Used Used Used Used Used Used Unused Used Used Unused Unused Used Unused Unused Unused VLCD is not supplied Quadruple from the outside. voltage boost VLCD is not supplied Quintuple from the outside. voltage boost VLCD is supplied from the outside. (16.5V) VLCD is supplied from Sample circuit (5) 1/8 to 1/16 1/5 5.0V the outside. (16.5V) VLCD is supplied from Sample circuit (6) 1/8 to 1/16 1/5 5.0V the outside. (16.5V) No.A2310-40/53 LC450210PCH Sample circuit (1) 1/8 to 1/16 Duty, 1/5 bias, VDD=5.0V, VBTI1=5.0V, Quintuple voltage booster, Contrast adjuster and LCD drive bias voltage generator are used. (REGE=VDD, “Set of display method” instruction (DBC=“1”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.) +5.0V Cvd VDD REGE + TSIN1 to TSIN4 VSS VBTI1 +5.0V VBTI2 Cbt D Cbt (*4) C1 C2 C3 C4 (*3) + CP1P + CP2P CP3P CP12N + CP4P VLCD VLCD1 Cvm + VLCD2 Cvm Cvm Cvm Input the external clock From the controller 1/8 duty (8com 200seg) to 1/16 duty (16com 200seg) VLCD0 Cvm Cvl LCD panel S6 S5 S4 S3 S2 S1 CP34N + COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 S200 S199 S198 S197 S196 VLCD3 (*1) VLCD4 VLCD5 OSCI (*2) ____ RES CE CL DI 1[F] ≤ Cvd ≤ 10[F] 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ C4 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] 0.1[F] ≤ Cvm ≤ 0.47[F] 4.5V ≤ VBTI1 ≤ VDD ≤ 5.5V VLCD=16.0V[Typ.] (=VBTI2 5) VLOGIC TSOUT1 to TSOUT3 TSO OPEN (*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3. (*2) When the internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. (*3) Make sure to open unused common and segment drivers. (*4) When “VBTI1 > 5.5V” is assumed during discharge of capacitors for voltage booster, make sure to connect a zener diode “D” between VBTI1 and VSS. No.A2310-41/53 LC450210PCH Sample circuit (2) 1/8 to 1/16 Duty, 1/5 bias, VDD=5.0V, VBTI1=5.0V, Quadruple voltage booster, Contrast adjuster and LCD drive bias voltage generator are used. (REGE=VDD, “Set of display method” instruction (DBC=“1”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.) +5.0V Cvd VDD REGE + TSIN1 to TSIN4 VSS VBTI1 +5.0V VBTI2 Cbt D Cbt (*4) C1 C2 C3 (*3) + CP1P + CP2P CP3P CP12N + VLCD VLCD1 Cvm VLCD2 Cvm Cvm Cvm Input the external clock From the controller 1/8 duty (8com 200seg) to 1/16 duty (16com 200seg) VLCD0 Cvm + LCD panel S6 S5 S4 S3 S2 S1 CP34N CP4P Cvl COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 S200 S199 S198 S197 S196 VLCD3 (*1) VLCD4 VLCD5 OSCI (*2) ____ RES CE CL DI 1[F] ≤ Cvd ≤ 10[F] 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] 0.1[F] ≤ Cvm ≤ 0.47[F] 4.5V ≤ VBTI1 ≤ VDD ≤ 5.5V VLCD=12.8V[Typ.] (=VBTI2 4) VLOGIC TSOUT1 to TSOUT3 TSO OPEN (*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3. (*2) When the internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. (*3) Make sure to open unused common and segment drivers. (*4) When “VBTI1 > 5.5V” is assumed during discharge of capacitors for voltage booster, make sure to connect a zener diode “D” between VBTI1 and VSS. No.A2310-42/53 LC450210PCH Sample circuit (3) 1/8 to 1/16 Duty, 1/5 bias, VDD=3.0V, VBTI1=VBTI2=3.0V, Quintuple voltage booster, Contrast adjuster and LCD drive bias voltage generator are used. (REGE=VSS, “Set of display method” instruction (DBC=“1”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.) +3.0V Cvd VDD REGE + TSIN1 to TSIN4 VSS VBTI1 +3.0V VBTI2 Cbt D (*3) (*4) C1 C2 C3 C4 + CP1P + CP2P CP3P CP12N + CP4P VLCD + VLCD1 Cvm VLCD2 Cvm Cvm Cvm Input the external clock From the controller 1/8 duty (8com 200seg) to 1/16 duty (16com 200seg) VLCD0 Cvm Cvl LCD panel S6 S5 S4 S3 S2 S1 CP34N + COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 S200 S199 S198 S197 S196 VLCD3 (*1) VLCD4 VLCD5 OSCI (*2) ____ RES CE CL DI 1[F] ≤ Cvd ≤ 10[F] 1[F] ≤ Cbt ≤ 10[F] 1[F] ≤ C1 ≤ 10[F] 1[F] ≤ C2 ≤ 10[F] 1[F] ≤ C3 ≤ 10[F] 1[F] ≤ C4 ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] 0.1[F] ≤ Cvm ≤ 0.47[F] 2.7V ≤ VBTI1=VBTI2 ≤ VDD ≤ 3.3V VLCD=15.0V[Typ.] (=VBTI2 5) VLOGIC TSOUT1 to TSOUT3 TSO OPEN (*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3. (*2) When the internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. (*3) Make sure to open unused common and segment drivers. (*4) When “VBTI1 > 3.6V” is assumed during discharge of capacitors for voltage booster, make sure to connect a zener diode “D” between VBTI1 and VSS. No.A2310-43/53 LC450210PCH Sample circuit (4) 1/8 to 1/16 Duty, 1/5 bias, VDD=5.0V, VLCD=16.5V (Voltage booster is not used, and supply VLCD from the outside), Contrast adjuster and LCD drive bias voltage generator are used. (REGE=VDD, “Set of display method” instruction (DBC=“0”, CTC0, CTC1=“1, 1”, DR=“1”) is executed.) +5.0V Cvd VDD REGE + TSIN1 to TSIN4 VSS VBTI1 VBTI2 (*3) CP1P OPEN CP12N CP2P CP3P CP4P VLCD VLCD1 Cvm + 1/8 duty (8com 200seg) to 1/16 duty (16com 200seg) VLCD0 Cvm Cvl LCD panel S6 S5 S4 S3 S2 S1 CP34N +16.5V COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 S200 S199 S198 S197 S196 VLCD2 Cvm Cvm Cvm Input the external clock From the controller 1[F] ≤ Cvd ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] 0.1[F] ≤ Cvm ≤ 0.47[F] 4.5V ≤ VLCD ≤ 16.5V VLCD3 (*1) VLCD4 VLCD5 OSCI (*2) ____ RES CE CL DI VLOGIC TSOUT1 to TSOUT3 TSO OPEN (*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3. (*2) When the internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. (*3) Make sure to open unused common and segment drivers. No.A2310-44/53 LC450210PCH Sample circuit (5) 1/8 to 1/16 Duty, 1/5 bias, VDD=5.0V, VLCD=16.5V (Voltage booster is not used, and supply VLCD from the outside), Contrast adjuster is not used (Input the VLCD voltage to VLCD0 pad), LCD drive bias voltage generator is used. (REGE=VDD, “Set of display method” instruction (DBC=“0”, CTC0, CTC1=“0, 1”, DR=“1”) is executed.) +5.0V Cvd VDD REGE + TSIN1 to TSIN4 VSS VBTI1 VBTI2 (*3) CP1P OPEN CP12N CP2P CP3P LCD panel 1/8 duty (8com 200seg) to 1/16 duty (16com 200seg) S6 S5 S4 S3 S2 S1 CP34N CP4P VLCD +16.5V COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 S200 S199 S198 S197 S196 VLCD0 Cvl VLCD1 Cvm + VLCD2 Cvm Cvm Cvm Input the external clock From the controller 1[F] ≤ Cvd ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] 0.1[F] ≤ Cvm ≤ 0.47[F] 4.5V ≤ VLCD ≤ 16.5V VLCD0=VLCD VLCD3 (*1) VLCD4 VLCD5 OSCI (*2) ____ RES CE CL DI VLOGIC TSOUT1 to TSOUT3 TSO OPEN (*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3. (*2) When the internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. (*3) Make sure to open unused common and segment drivers. No.A2310-45/53 LC450210PCH Sample circuit (6) 1/8 to 1/16 Duty, 1/5 bias, VDD=5.0V, VLCD=16.5V (Voltage booster is not used, and supply VLCD from the outside), Contrast adjuster and LCD drive bias voltage generator are not used (Input the voltage to VLCD0, VLCD1, VLCD2, VLCD3 and VLCD4 from the outside.). (REGE=VDD, “Set of display method” instruction (DBC=“0”, CTC0, CTC1=“0, 0”, DR=“1”) is executed.) +5.0V Cvd VDD REGE + TSIN1 to TSIN4 VSS VBTI1 VBTI2 (*3) CP1P OPEN CP12N CP2P CP3P COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 S200 S199 S198 S197 S196 LCD panel 1/8 duty (8com 200seg) to 1/16 duty (16com 200seg) CP34N S6 S5 S4 S3 S2 S1 CP4P +16.5V Cvl VLCD + 5/5 VLCD0 (when 1/5 bias is used) VLCD0 Cvm 4/5 VLCD0 (when 1/5 bias is used) VLCD1 Cvm 3/5 VLCD0 (when 1/5 bias is used) VLCD2 Cvm 2/5 VLCD0 (when 1/5 bias is used) VLCD3 (*1) Cvm 1/5 VLCD0 (when 1/5 bias is used) VLCD4 Cvm VLCD5 Input the external clock From the controller OSCI (*2) ____ RES CE CL DI 1[F] ≤ Cvd ≤ 10[F] 1[F] ≤ Cvl ≤ 10[F] 0.1[F] ≤ Cvm ≤ 0.47[F] 4.5V ≤ VLCD ≤ 16.5V VLCD1 < VLCD0 ≤ VLCD VLCD2 < VLCD1 < VLCD0 VLCD3 < VLCD2 < VLCD1 VLCD4 < VLCD3 < VLCD2 VLCD5 < VLCD4 < VLCD3 VLOGIC TSOUT1 to TSOUT3 TSO OPEN (*1) When 1/4 bias is set (DR=“0”), make sure to open VLCD3. (*2) When the internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. (*3) Make sure to open unused common and segment drivers. No.A2310-46/53 LC450210PCH Caution Caution is provided as follows for the stable operation of this LSI. However, caution does not provide any guarantee for operation and characteristics of this LSI. Moreover, examples of application circuit described are used only to explain internal operation and usage of this LSI. Therefore, it is necessary to design an application or set, in consideration of an LCD specification and condition. (1) Power supply pads All power supply pads must be connected to the power supply, and don’t open. (2) ITO (Indium Tin Oxide) line Wire the ITO line for power supply and voltage booster as short and wide as possible, because it is necessary to minimize the parasitic resistance of ITO line. (3) Signal wiring and connection DUMMY pads should be opened. (4) Unused input pads Unfixed input pads cause the unstable operation or the leak current of power supply, because this LSI adopts a CMOS process. Make sure to connect the open pad of logic input to VDD or VSS. (5) Protection from light An exposure to the light may cause the malfunction of this LSI. Make sure to shut out the surface, side and back of this LSI from the light when this LSI is mounted to the product. No.A2310-47/53 LC450210PCH Unit: [m] PAD No.312 DUMMY PAD No.320 COM8 PAD No.319 COM7 PAD No.318 COM6 PAD No.317 COM5 PAD No.316 COM4 PAD No.315 COM3 PAD No.314 COM2 PAD No.313 COM1 PAD Assignment (Bump Side View) DUMMY PAD No.1 S1 S2 S3 S4 S5 S6 PAD No.2 PAD No.3 PAD No.4 PAD No.5 PAD No.6 PAD No.7 Alignment mark 2 PAD No.311 VLCD4 PAD No.310 VLCD4 PAD No.309 VLCD4 PAD No.308 VLCD1 PAD No.307 VLCD1 PAD No.306 VLCD1 PAD No.305 VLCD3 Bump shape C (Power supply, I/O) Bump shape A (Segment driver) +Y 68 170 27 23 50 +X (0,0) 65 100 35 2 S = 4,590 [m ] (Typ.) 2 S = 4,420 [m ] (Typ.) Chip name PAD No.218 CE PAD No.217 RES PAD No.216 VLOGIC S195 S196 S197 S198 S199 S200 PAD No.196 PAD No.197 PAD No.198 PAD No.199 PAD No.200 PAD No.201 PAD No.215 TSO PAD No.214 TSOUT3 Alignment mark 3 PAD No.213 TSOUT2 Alignment mark 1 PAD No.212 TSOUT1 Bump shape B (Common driver) DUMMY PAD No.211 COM16 PAD No.203 COM15 PAD No.204 COM14 PAD No.205 COM13 PAD No.206 COM12 PAD No.207 COM11 PAD No.208 COM10 PAD No.209 COM9 PAD No.210 DUMMY PAD No.202 30 45 99 75 2 S = 4,455 [m ] (Typ.) No.A2310-48/53 LC450210PCH Chip size (X, Y and S are based on the dicing center.) X = 1.49 mm Y = 10.63 mm S = 15.8387 mm2 Chip thickness = 400 m Au bump (Typ.) Size Item PAD No. Bump shape 1 to 202 X [m] Y [m] S [m2] A 170 27 4,590 B 45 99 4,455 211 to 312 C 68 65 4,420 1 to 202 A 50 - B 75 - 211 to 312 C 100 - 1 to 202 A 23 - B 30 - C 35 - 17 - 203 to 210, Bump size 313 to 320 203 to 210, Min. bump pitch 313 to 320 203 to 210, Min. bump clearance 313 to 320 211 to 312 Bump height All bumps Alignment mark 80 50 80 50 20 60 Alignment mark 3 30 Alignment mark 2 10 Alignment mark 1 10 30 50 80 20 50 60 Unit: m 80 Center coordinates of alignment marks Alignment mark X coordinate [m] Y coordinate [m] Alignment mark 1 -628 -5110 Alignment mark 2 -628 5110 Alignment mark 3 638 -5070 No.A2310-49/53 LC450210PCH Center coordinates of PADs X Y coordinate coordinate PAD PAD No. Name [m] [m] 1 DUMMY -574.5 2 S1 3 4 X Y coordinate coordinate Bump PAD PAD shape No. Name Bump [m] [m] 5216 A 61 S60 -574.5 2025 A -574.5 4975 A 62 S61 -574.5 1975 A S2 -574.5 4925 A 63 S62 -574.5 1925 A S3 -574.5 4875 A 64 S63 -574.5 1875 A 5 S4 -574.5 4825 A 65 S64 -574.5 1825 A 6 S5 -574.5 4775 A 66 S65 -574.5 1775 A 7 S6 -574.5 4725 A 67 S66 -574.5 1725 A 8 S7 -574.5 4675 A 68 S67 -574.5 1675 A 9 S8 -574.5 4625 A 69 S68 -574.5 1625 A 10 S9 -574.5 4575 A 70 S69 -574.5 1575 A 11 S10 -574.5 4525 A 71 S70 -574.5 1525 A 12 S11 -574.5 4475 A 72 S71 -574.5 1475 A 13 S12 -574.5 4425 A 73 S72 -574.5 1425 A 14 S13 -574.5 4375 A 74 S73 -574.5 1375 A 15 S14 -574.5 4325 A 75 S74 -574.5 1325 A 16 S15 -574.5 4275 A 76 S75 -574.5 1275 A 17 S16 -574.5 4225 A 77 S76 -574.5 1225 A 18 S17 -574.5 4175 A 78 S77 -574.5 1175 A 19 S18 -574.5 4125 A 79 S78 -574.5 1125 A 20 S19 -574.5 4075 A 80 S79 -574.5 1075 A 21 S20 -574.5 4025 A 81 S80 -574.5 1025 A 22 S21 -574.5 3975 A 82 S81 -574.5 975 A 23 S22 -574.5 3925 A 83 S82 -574.5 925 A 24 S23 -574.5 3875 A 84 S83 -574.5 875 A 25 S24 -574.5 3825 A 85 S84 -574.5 825 A 26 S25 -574.5 3775 A 86 S85 -574.5 775 A 27 S26 -574.5 3725 A 87 S86 -574.5 725 A 28 S27 -574.5 3675 A 88 S87 -574.5 675 A 29 S28 -574.5 3625 A 89 S88 -574.5 625 A 30 S29 -574.5 3575 A 90 S89 -574.5 575 A 31 S30 -574.5 3525 A 91 S90 -574.5 525 A 32 S31 -574.5 3475 A 92 S91 -574.5 475 A 33 S32 -574.5 3425 A 93 S92 -574.5 425 A 34 S33 -574.5 3375 A 94 S93 -574.5 375 A 35 S34 -574.5 3325 A 95 S94 -574.5 325 A 36 S35 -574.5 3275 A 96 S95 -574.5 275 A 37 S36 -574.5 3225 A 97 S96 -574.5 225 A 38 S37 -574.5 3175 A 98 S97 -574.5 175 A 39 S38 -574.5 3125 A 99 S98 -574.5 125 A 40 S39 -574.5 3075 A 100 S99 -574.5 75 A 41 S40 -574.5 3025 A 101 S100 -574.5 25 A 42 S41 -574.5 2975 A 102 S101 -574.5 -25 A 43 S42 -574.5 2925 A 103 S102 -574.5 -75 A 44 S43 -574.5 2875 A 104 S103 -574.5 -125 A 45 S44 -574.5 2825 A 105 S104 -574.5 -175 A 46 S45 -574.5 2775 A 106 S105 -574.5 -225 A 47 S46 -574.5 2725 A 107 S106 -574.5 -275 A 48 S47 -574.5 2675 A 108 S107 -574.5 -325 A 49 S48 -574.5 2625 A 109 S108 -574.5 -375 A 50 S49 -574.5 2575 A 110 S109 -574.5 -425 A 51 S50 -574.5 2525 A 111 S110 -574.5 -475 A 52 S51 -574.5 2475 A 112 S111 -574.5 -525 A 53 S52 -574.5 2425 A 113 S112 -574.5 -575 A 54 S53 -574.5 2375 A 114 S113 -574.5 -625 A 55 S54 -574.5 2325 A 115 S114 -574.5 -675 A 56 S55 -574.5 2275 A 116 S115 -574.5 -725 A 57 S56 -574.5 2225 A 117 S116 -574.5 -775 A 58 S57 -574.5 2175 A 118 S117 -574.5 -825 A 59 S58 -574.5 2125 A 119 S118 -574.5 -875 A 60 S59 -574.5 2075 A 120 S119 -574.5 -925 A shape No.A2310-50/53 LC450210PCH X Y coordinate coordinate PAD PAD No. Name [m] [m] 121 S120 -574.5 122 S121 123 X Y coordinate coordinate Bump PAD PAD shape No. Name [m] [m] -975 A 181 S180 -574.5 -3975 A -574.5 -1025 A 182 S181 -574.5 -4025 A S122 -574.5 -1075 A 183 S182 -574.5 -4075 A 124 S123 -574.5 -1125 A 184 S183 -574.5 -4125 A 125 S124 -574.5 -1175 A 185 S184 -574.5 -4175 A 126 S125 -574.5 -1225 A 186 S185 -574.5 -4225 A 127 S126 -574.5 -1275 A 187 S186 -574.5 -4275 A 128 S127 -574.5 -1325 A 188 S187 -574.5 -4325 A 129 S128 -574.5 -1375 A 189 S188 -574.5 -4375 A 130 S129 -574.5 -1425 A 190 S189 -574.5 -4425 A 131 S130 -574.5 -1475 A 191 S190 -574.5 -4475 A 132 S131 -574.5 -1525 A 192 S191 -574.5 -4525 A 133 S132 -574.5 -1575 A 193 S192 -574.5 -4575 A 134 S133 -574.5 -1625 A 194 S193 -574.5 -4625 A 135 S134 -574.5 -1675 A 195 S194 -574.5 -4675 A 136 S135 -574.5 -1725 A 196 S195 -574.5 -4725 A 137 S136 -574.5 -1775 A 197 S196 -574.5 -4775 A 138 S137 -574.5 -1825 A 198 S197 -574.5 -4825 A 139 S138 -574.5 -1875 A 199 S198 -574.5 -4875 A 140 S139 -574.5 -1925 A 200 S199 -574.5 -4925 A 141 S140 -574.5 -1975 A 201 S200 -574.5 -4975 A 142 S141 -574.5 -2025 A 202 DUMMY -574.5 -5216 A 143 S142 -574.5 -2075 A 203 COM16 -135 -5182 B 144 S143 -574.5 -2125 A 204 COM15 -60 -5182 B 145 S144 -574.5 -2175 A 205 COM14 15 -5182 B 146 S145 -574.5 -2225 A 206 COM13 90 -5182 B 147 S146 -574.5 -2275 A 207 COM12 165 -5182 B 148 S147 -574.5 -2325 A 208 COM11 240 -5182 B 149 S148 -574.5 -2375 A 209 COM10 315 -5182 B 150 S149 -574.5 -2425 A 210 COM9 390 -5182 B 151 S150 -574.5 -2475 A 211 DUMMY 623.5 -5197 C 152 S151 -574.5 -2525 A 212 TSOUT1 623.5 -4900 C 153 S152 -574.5 -2575 A 213 TSOUT2 623.5 -4800 C 154 S153 -574.5 -2625 A 214 TSOUT3 623.5 -4700 C 155 S154 -574.5 -2675 A 215 TSO 623.5 -4600 C 156 S155 -574.5 -2725 A 216 VLOGIC 623.5 -4500 C 157 S156 -574.5 -2775 A 217 RES 623.5 -4400 C 158 S157 -574.5 -2825 A 218 CE 623.5 -4300 C C _______ Bump shape 159 S158 -574.5 -2875 A 219 DI 623.5 -4200 160 S159 -574.5 -2925 A 220 CL 623.5 -4100 C 161 S160 -574.5 -2975 A 221 OSCI 623.5 -4000 C 162 S161 -574.5 -3025 A 222 TSIN1 623.5 -3900 C 163 S162 -574.5 -3075 A 223 TSIN2 623.5 -3800 C 164 S163 -574.5 -3125 A 224 TSIN3 623.5 -3700 C 165 S164 -574.5 -3175 A 225 TSIN4 623.5 -3600 C 166 S165 -574.5 -3225 A 226 VSS 623.5 -3500 C 167 S166 -574.5 -3275 A 227 VSS 623.5 -3400 C 168 S167 -574.5 -3325 A 228 VSS 623.5 -3300 C 169 S168 -574.5 -3375 A 229 VSS 623.5 -3200 C 170 S169 -574.5 -3425 A 230 REGE 623.5 -3100 C 171 S170 -574.5 -3475 A 231 VDD 623.5 -3000 C 172 S171 -574.5 -3525 A 232 VDD 623.5 -2900 C 173 S172 -574.5 -3575 A 233 VDD 623.5 -2800 C 174 S173 -574.5 -3625 A 234 VDD 623.5 -2700 C 175 S174 -574.5 -3675 A 235 VSS 623.5 -2600 C 176 S175 -574.5 -3725 A 236 VSS 623.5 -2500 C 177 S176 -574.5 -3775 A 237 VSS 623.5 -2400 C 178 S177 -574.5 -3825 A 238 VSS 623.5 -2300 C 179 S178 -574.5 -3875 A 239 VSS 623.5 -2200 C 180 S179 -574.5 -3925 A 240 VSS 623.5 -2100 C No.A2310-51/53 LC450210PCH X Y coordinate coordinate PAD PAD No. Name [m] [m] 241 VSS 623.5 242 VSS 243 X Y coordinate coordinate Bump PAD PAD shape No. Name Bump [m] [m] -2000 C 301 VLCD2 623.5 4000 C 623.5 -1900 C 302 VLCD2 623.5 4100 C VSS 623.5 -1800 C 303 VLCD3 623.5 4200 C 244 VBTI1 623.5 -1700 C 304 VLCD3 623.5 4300 C 245 VBTI1 623.5 -1600 C 305 VLCD3 623.5 4400 C 246 VBTI1 623.5 -1500 C 306 VLCD1 623.5 4500 C 247 VBTI1 623.5 -1400 C 307 VLCD1 623.5 4600 C 248 VBTI1 623.5 -1300 C 308 VLCD1 623.5 4700 C 249 VBTI2 623.5 -1200 C 309 VLCD4 623.5 4800 C 250 VBTI2 623.5 -1100 C 310 VLCD4 623.5 4900 C 251 VBTI2 623.5 -1000 C 311 VLCD4 623.5 5000 C 252 VBTI2 623.5 -900 C 312 DUMMY 623.5 5197 C 253 VBTI2 623.5 -800 C 313 COM1 390 5182 B 254 CP1P 623.5 -700 C 314 COM2 315 5182 B 255 CP1P 623.5 -600 C 315 COM3 240 5182 B 256 CP1P 623.5 -500 C 316 COM4 165 5182 B 257 CP1P 623.5 -400 C 317 COM5 90 5182 B 258 CP12N 623.5 -300 C 318 COM6 15 5182 B 259 CP12N 623.5 -200 C 319 COM7 -60 5182 B 260 CP12N 623.5 -100 C 320 COM8 -135 5182 B 261 CP12N 623.5 0 C 262 CP12N 623.5 100 C 263 CP12N 623.5 200 C 264 CP12N 623.5 300 C 265 CP2P 623.5 400 C 266 CP2P 623.5 500 C 267 CP2P 623.5 600 C 268 CP2P 623.5 700 C 269 CP3P 623.5 800 C 270 CP3P 623.5 900 C 271 CP3P 623.5 1000 C 272 CP3P 623.5 1100 C 273 CP34N 623.5 1200 C 274 CP34N 623.5 1300 C 275 CP34N 623.5 1400 C 276 CP34N 623.5 1500 C 277 CP34N 623.5 1600 C 278 CP34N 623.5 1700 C 279 CP34N 623.5 1800 C 280 CP4P 623.5 1900 C 281 CP4P 623.5 2000 C 282 CP4P 623.5 2100 C 283 CP4P 623.5 2200 C 284 VLCD 623.5 2300 C 285 VLCD 623.5 2400 C 286 VLCD 623.5 2500 C 287 VLCD 623.5 2600 C 288 VLCD 623.5 2700 C 289 VLCD 623.5 2800 C 290 VLCD0 623.5 2900 C 291 VLCD0 623.5 3000 C 292 VLCD0 623.5 3100 C 293 VLCD0 623.5 3200 C 294 VLCD0 623.5 3300 C 295 VLCD5 623.5 3400 C 296 VLCD5 623.5 3500 C 297 VLCD5 623.5 3600 C 298 VLCD5 623.5 3700 C 299 VLCD5 623.5 3800 C 300 VLCD2 623.5 3900 C shape No.A2310-52/53 LC450210PCH ORDERING INFORMATION Device LC450210PCH-T3 Package Shipping (Qty / Packing) Chip with Au bumps (Pb-Free) 960 / Waffle Pack ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A2310-53/53