LC450210PCH Application Note Design method of the LCD system using 1/16-duty LCD panel http://onsemi.com Overview This application note explains the design method of the LCD (Liquid Crystal Display) system using LCD driver LSI (LC450210PCH). The LC450210PCH is the 1/8 to 1/16 duty dot matrix LCD controller driver. By controlling this driver with a microcontroller, it is used in applications such as character display and simple graphic display etc. The LC450210PCH can drive an LCD panel of up to 3,200 dots (16x16 dot font : 1-line display of up to 12 digits and 128 segments, 5x7 dot font : 2-line display of up to 40 digits). LCD System Configuration Example This application note explains various function explanations and setting method example of serial data in the LCD system configuration using LCD driver LSI (LC450210PCH) as shown below. LCD Driver LSI (LC450210PCH) +5.0 [V] Cvd 4 +5.0 [V] VDD REGE TSIN1 to TSIN4 VSS VBTI1 VBTI2 Cbt 12.0 [V] (Typ.) The contrast adjuster is used VLCD0 Cvm VLCD1 Cvm VLCD2 The 1/5 bias is used Cvm VLCD3 Cvm VLCD4 Cbt Cvm CP1P VLCD5 C1 CP12N C2 CP2P The quintuple voltage booster is used CP3P C3 CP34N C4 16.0 [V] CP4P S193 to S200 S1 to S192 8 192 VLCD Cvl COM1 to COM16 The internal oscillator circuit is used. 16 AM CD USB AUTO SCN CE CL DI VLOGIC TSOUT1 to TSOUT3 TSO 3 (open) (open) (open) Figure 1. LCD system configuration using LCD driver LSI (LC450210PCH) CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. CCB is a registered trademark of Semiconductor Components Industries, LLC. April, 2014 - Rev.0 RDM LCD Panel (16x16 dot font) x 12digits + 8 icons = 3,080 segments (CCB interface) © Semiconductor Components Industries, LLC, 2014 RPT OSCI RES LCD Controller FM 1 LC450210PCH Application Note < Operation specifications of the LCD system > LCD driver LSI (LC450210PCH) specifications Selectable duty ratio by serial data: 1/8 duty to 1/16 duty Selectable LCD bias voltage ratio by serial data: 1/4 bias or 1/5 bias Selectable inversion drives of LCD drive waveforms by serial data: line inversion or frame inversion. Adjustable frame frequency and clock frequency of voltage booster by serial data. Selectable operation modes by serial data: power-saving mode (maintains display data), the state of display (ON, all ON, all OFF, all forced OFF). Built-in oscillator circuit. Selectable fundamental clock operating modes by serial data: internal oscillator operating mode or external clock operating mode. Input of serial data supports CCB* format (for 5V and 3V). Selectable voltage range of power supply for logic block by setting REGE pad. Built-in quadruple and quintuple voltage booster with discharge function. Power supply for LCD driver block (VLCD). Built-in contrast adjuster for LCD drive bias voltage (VLCD0). The initialization of this driver and the prevention of an unintended display are controllable by setting RES pad. LCD system specifications of Figure 1. The LCD panel to use has 200 segments and 16 commons. Total display segments are 3,080 segments. Therefore, LCD drive duty ratio is 1/16 duty. The 1/5 bias is used. The line inversion is used. Used. (Controlled by LCD controller) Used. (Controlled by LCD controller) The internal oscillator circuit is used. The internal oscillator operating mode is used. Used. (Controlled by LCD controller) 5V power supply. (REGE=VDD) The internal quintuple voltage booster is used. (VDD=5V) VLCD=3.2 [V] x 5 = 16.0 [V](Typ.) The internal contrast adjuster circuit is used. Used. (Controlled by LCD controller) Pad Assignment The following figure shows the pin assignment of LCD driver LSI (LC450210PCH). Y=10.63 [mm] PAD No.203 (COM16) PAD No.204 (COM15) PAD No.1 (DUMMY) PAD No.7 PAD No.6 PAD No.5 PAD No.4 PAD No.3 PAD No.2 (Alignment mark 2) (S6) (S5) (S4) (S3) (S2) (S1) (S200) (S199) (S198) (S197) (S196) (S195) PAD No.201 PAD No.200 PAD No.199 PAD No.198 PAD No.197 PAD No.196 (Alignment mark 1) PAD No.202 (DUMMY) X=1.49 [mm] PAD No.320 (COM8) PAD No.319 (COM7) (Bump Side View) Figure 2. Pad Assignment of LCD driver LSI (LC450210PCH) http://onsemi.com 2 (DUMMY) PAD No.312 (VLCD4) PAD No.311 (VLCD4) PAD No.310 (VLCD4) PAD No.309 (VLCD1) PAD No.308 (TSO) PAD No.215 (TSOUT3) PAD No.214 (TSOUT1) PAD No.212 (TSOUT2) PAD No.213 (Alignment mark 3) PAD No.314 (COM2) PAD No.313 (COM1) (DUMMY) PAD No.211 PAD No.209 (COM10) PAD No.210 (COM9) LC450210PCH Application Note Table 1. Pad function of LCD driver LSI (LC450210PCH) Pad name Pad functions Logic block power supply pad REGE=VDD : Supply a voltage from 4.5 [V] to 5.5 [V] to VDD. VDD REGE=VSS : Supply a voltage from 2.7 [V] to 3.6 [V] to VDD. In addition, make sure to connect a capacitor between VDD and VSS. Ground pad VSS Make sure to connect VSS to ground. Regulator voltage monitor output pad VLOGIC Do not use VLOGIC with an external circuit. Logic power supply regulator and voltage booster regulator control input pad Depending on specification of power supply, make sure to connect REGE to VDD or VSS. REGE=VDD : The 5V power supply is used. REGE The regulator of logic power supply and the regulator of voltage booster run. REGE=VSS : The 3V power supply is used. The regulator of logic power supply and the regulator of voltage booster stop. S1 to S200 Segment drive output pads COM1 to COM16 Common drive output pads Voltage booster base voltage input pad VBTI1 < When voltage booster is used > Make sure to connect a capacitor between VBTI1 and VSS. REGE=VDD : Input the voltage from 4.5V to VDD [V] to VBTI1. REGE=VSS : Connect VBTI1 to VBTI2, and Input the voltage from 2.7 [V] to VDD [V] to VBTI1. ( When quadruple booster is used : VBTI1 ≤ 3.6 [V], When quintuple booster is used : VBTI1 ≤ 3.3 [V]) < When voltage booster is not used > Make sure to open VBTI1. Voltage booster base voltage input-output pad VBTI2 < When voltage booster is used > Make sure to connect a capacitor between VBTI2 and VSS. REGE=VDD : VBTI2 outputs the base voltage for voltage booster. REGE=VSS : Connect VBTI1 to VBTI2, and Input the voltage from 2.7 [V] to VDD [V] to VBTI1. ( When quadruple booster is used : VBTI1 ≤ 3.6 [V], When quintuple booster is used : VBTI1 ≤ 3.3 [V]) < When voltage booster is not used > Make sure to open VBTI2. Voltage booster input-output pads CP1P, CP12N, CP2P, CP3P, CP34N, CP4P < When quadruple voltage booster is used > Make sure to connect a capacitor between CP1P(+) and CP12N(-). Make sure to connect a capacitor between CP2P(+) and CP12N(-). Make sure to connect a capacitor between CP3P(+) and CP34N(-). Make sure to connect CP4P and VLCD. < When quintuple voltage booster is used > Make sure to connect a capacitor between CP1P(+) and CP12N(-). Make sure to connect a capacitor between CP2P(+) and CP12N(-). Make sure to connect a capacitor between CP3P(+) and CP34N(-). Make sure to connect a capacitor between CP4P(+) and CP34N(-). < When voltage booster is not used > Make sure to open CP1P, CP12N, CP2P, CP3P, CP34N and CP4P. LCD driver block power supply pad Make sure to connect a capacitor between VLCD and VSS. < When quadruple voltage booster is used > VLCD outputs the booster voltage (VBTI2 x 4). VLCD < When quintuple voltage booster is used > VLCD outputs the booster voltage (VBTI2 x 5). < When voltage booster is not used > Supply a voltage from 4.5 [V] to 16.5 [V] to VLCD. When contrast adjuster is used, follow a condition of VLCD ≥ VLCD0 + 2.4 [V]. LCD drive bias voltage (High level) input-output pad Make sure to connect a capacitor between VLCD0 and VLCD5. VLCD0 < When contrast adjuster is used > VLCD0 outputs the LCD drive bias voltage (High level) set by control data from CT0 to CT5 of the “Set of display contrast” instruction. However, follow a condition of VLCD0 ≤ VLCD - 2.4 [V]. < When contrast adjuster is not used > Input the LCD drive bias voltage (High level) to VLCD0 from the outside, and follow a condition of VLCD1 < VLCD0 ≤ VLCD. http://onsemi.com 3 LC450210PCH Application Note Pad name VLCD1 VLCD2 VLCD3 Pad function LCD drive bias voltage (3/4 level, 4/5 level) input-output pad Make sure to connect a capacitor between VLCD1 and VLCD5. < When LCD drive bias voltage generator is used> When 1/4 bias is used, VLCD1 outputs the LCD drive bias voltage (3/4 VLCD0). When 1/5 bias is used, VLCD1 outputs the LCD drive bias voltage (4/5 VLCD0). < When LCD drive bias voltage generator is not used > When 1/4 bias is used, Input the LCD drive bias voltage (3/4 VLCD0) to VLCD1 from the outside, and follow a condition of VLCD2 < VLCD1 < VLCD0. When 1/5 bias is used, Input the LCD drive bias voltage (4/5 VLCD0) to VLCD1 from the outside, and follow a condition of VLCD2 < VLCD1 < VLCD0. LCD drive bias voltage (2/4 level, 3/5 level) input-output pad Make sure to connect a capacitor between VLCD2 and VLCD5. < When LCD drive bias voltage generator is used> When 1/4 bias is used, VLCD2 outputs the LCD drive bias voltage (2/4 VLCD0). When 1/5 bias is used, VLCD2 outputs the LCD drive bias voltage (3/5 VLCD0). < When LCD drive bias voltage generator is not used > When 1/4 bias is used, Input the LCD drive bias voltage (2/4 VLCD0) to VLCD2 from the outside, and follow a condition of VLCD4 < VLCD2 < VLCD1. When 1/5 bias is used, Input the LCD drive bias voltage (3/5 VLCD0) to VLCD2 from the outside, and follow a condition of VLCD3 < VLCD2 < VLCD1. LCD drive bias voltage (2/5 level) input-output pad < When LCD drive bias voltage generator is used> When 1/4 bias is used, make sure to open VLCD3. When 1/5 bias is used, VLCD3 outputs the LCD drive bias voltage (2/5 VLCD0). Make sure to connect a capacitor between VLCD3 and VLCD5. < When LCD drive bias voltage generator is not used > When 1/4 bias is used, make sure to open VLCD3. When 1/5 bias is used, Input the LCD drive bias voltage (2/5 VLCD0) to VLCD3 from the outside, and follow a condition of VLCD4 < VLCD3 < VLCD2. Make sure to connect a capacitor between VLCD3 and VLCD5. LCD drive bias voltage (1/4 level, 1/5 level) input-output pad Make sure to connect a capacitor between VLCD4 and VLCD5. VLCD4 VLCD5 OSCI CE CL DI RES TSIN1, TSIN2, TSIN3, TSIN4 TSOUT1, TSOUT2, TSOUT3 TSO DUMMY < When LCD drive bias voltage generator is used> When 1/4 bias is used, VLCD4 outputs the LCD drive bias voltage (1/4 VLCD0). When 1/5 bias is used, VLCD4 outputs the LCD drive bias voltage (1/5 VLCD0). < When LCD drive bias voltage generator is not used > When 1/4 bias is used, Input the LCD drive bias voltage (1/4 VLCD0) to VLCD4 from the outside, and follow a condition of VLCD5 < VLCD4 < VLCD2. When 1/5 bias is used, Input the LCD drive bias voltage (1/5 VLCD0) to VLCD4 from the outside, and follow a condition of VLCD5 < VLCD4 < VLCD3. LCD drive bias voltage (Low level) input-output pad Make sure to connect VLCD5 to VSS even if the LCD drive bias generator is not used. External clock input pad (When external clock operating mode was set) When internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. When external clock operating mode is set (OC=“1”), the OSCI is used to input the external clock. Serial data transfer chip enable input pad Serial data transfer synchronization clock input pad Serial data transfer data input pad Reset input pad RES=VSS : The state of this LSI is reset. RES=VDD : Normal state. Test input pads Make sure to connect these pads to VSS. Test output pads Make sure to open these pads. Test output pad Make sure to open this pad. Dummy pads These pads are not available. Don’t connect between dummy pads. Moreover, don’t use them by an external circuit. http://onsemi.com 4 LC450210PCH Application Note Explanation of the Serial Data Transfer (1) Basic Timing The LC450210PCH has several internal registers. These internal registers are written by CCB interface (Serial interface). Structure of transfer bits consists of CCB address and instruction data. First eight bits are CCB address (B2h). The bit number of instruction data is different depending on an instruction, and this is from 16 bits to 272 bits. The serial data is taken by the positive edge of the CL signal, which is latched by the negative edge of the CE signal. When the number of data in CE=“High level” period is different from the defined number, LSI does not execute the instruction and holds the old state. Even when CL signal stops at high level, the CCB interface can be received. However, serial data transfer timing (transfer form) is different. Therefore, when designing equipment, refer to the “Delivery specification for the LC450210PCH”. For more information about the number of instruction data, refer to “(3) Explanation of Instruction Data”. CE CL DI 0 1 0 0 1 1 0 1 D0 D1 D2 D3 D4 D5 D6 D7 D264 D265 D266 D267 D268 D269 D270 D271 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Instruction data (from 16 bits to 272 bits) Figure 3. Basic timing when CL signal is stopped at the Low Level http://onsemi.com 5 LC450210PCH Application Note (2) Allowable Operating Ranges of the Serial Data Transfer The following figure shows the specifications of the allowable operating ranges when CL signal is stopped at the low level. VIH1 50% VIL1 CE tclL tclH VIH1 50% VIL1 CL tf tcp tr tcs tch VIH1 50% VIL1 DI tds tdh Figure 4. Allowable operating ranges of serial data transfer Table 2. Allowable operating ranges at Ta = -40 to +105 [°C], VSS=0 [V] Parameter Power Supply Voltage Input High Level Voltage Input Low Level Voltage Symbol Max. Unit VDD VDD, REGE=VDD 4.5 5.5 V VDD, REGE=VSS 2.7 3.6 V VIH1 CE, CL, DI, VDD=4.5V to 5.5V (REGE=VDD) 0.5 VDD 5.5 V CE, CL, DI, VDD=2.7V to 3.6V (REGE=VSS) 0.8 VDD 3.6 V CE, CL, DI, VDD=4.5V to 5.5V (REGE=VDD) 0 0.2 VDD V CE, CL, DI, VDD=2.7V to 3.6V (REGE=VSS) 0 0.2 VDD V 3.125 MHz VIL1 Conditions Min. Typ. Serial Data Transfer Synchronization Clock Frequency fcl CL, 1/(tclL+tclH) Data Setup Time tds CL, DI Data Hold Time tdh CL, DI 160 ns CE Wait Time tcp CE, CL 160 ns CE Setup Time tcs CE, CL 160 ns CE Hold Time tch CE, CL 160 ns High Level Clock Pulse Width tclH CL 160 ns Low Level Clock Pulse Width tclL CL 160 ns 160 ns Rise Time tr CE, CL, DI 160 ns Fall Time tf CE, CL, DI 160 ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. http://onsemi.com 6 LC450210PCH Application Note (3) Explanation of Instruction Data (3-1) “Set of display method” instruction The display method is set by “Set of display method” instruction. After having reset a system by RES=“Low level”, make sure to execute “Set of display method” first. CE CL DI 0 1 0 0 1 1 0 1 OC 0 1 0 CTC DBC CTC 0 1 0 DT0 DT1 DT2 DT3 DR WVC 1 0 CDIR SDIR 1 0 DBF DBF DBF 2 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Control data (32 bits) FC0 FC1 FC2 FC3 0 0 0 1 B0 to B3, A0 to A3 : CCB address. (=B2h) OC DBC CTC0, CTC1 DT0 to DT3 DR WVC CDIR SDIR DBF0 to DBF2 FC0 to FC3 : Control data to set a fundamental clock operating mode. : Control data to set a state of voltage booster circuit. : Control data to set a state of contrast adjuster circuit and LCD drive bias voltage generator circuit. : Control data to set duty from 1/8 to 1/16. : Control data to set 1/4 bias or 1/5 bias. : Control data to set inversion drive of LCD drive waveforms. : Control data to set scan direction of common outputs. : Control data to set a correspondence of a segment output and a column address of RAM. : Control data to set clock frequency of voltage booster. : Control data to set frame frequency of common and segment output waveforms. (3-2) “Control of display ON / OFF” instruction A state of display is set by “Control of display ON / OFF” instruction. CE CL DI 0 1 0 0 1 1 0 1 PNC 0 1 0 SC0 SC1 0 BU 0 0 1 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Control data (16 bits) B0 to B3, A0 to A3 : CCB address. (=B2h) PNC SC0, SC1 BU : Control data to set normal display or reversed display. : Control data to set a state of display. : Control data to set normal mode or power-saving mode. http://onsemi.com 7 0 1 0 LC450210PCH Application Note (3-3) “Set of line address” instruction A line address of RAM to appoint a start display position is set by “Set of line address” instruction. CE CL DI 0 1 0 0 1 1 0 1 LNA 0 LNA LNA LNA 1 2 3 0 0 0 0 0 1 0 0 0 0 1 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Control data (16 bits) B0 to B3, A0 to A3 : CCB address. (=B2h) LNA0 to LNA3 : Control data to set a line address of RAM. (3-4) “Write display data to RAM (8 x 15 bits in a lump)” instruction The display data of “8 x 15 bits (8 common outputs x 15 segment outputs)” is written to RAM in a lump by setting of page address and column address of RAM. This LCD system configuration example does not use this serial data to use the LCD panel of 1/16 duty. (3-5) “Write display data to RAM (16 x 16 bits in a lump)” instruction The display data of “16 x 16 bits (16 common outputs x 16 segment outputs)” is written to RAM in a lump by setting of page address and column address of RAM. CE CL DI 0 1 0 0 1 1 0 1 Dn_ m Dn_ Dn_ Dn_ Dn_ m+1 m+2 m+3 m+4 Dn+15_Dn+15_Dn+15_Dn+15_Dn+15_ m+11 m+12 m+13 m+14 m+15 Note : n=1 to 185, n+15=16 to 200, m=1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Display data (256 bits) CRA CRA CRA CRA CRA CRA CRA CRA 0 1 2 3 4 5 6 7 PGA 0 Control data (16 bits) B0 to B3, A0 to A3 : CCB address. (=B2h) Dn_m, Dn_m+1 to Dn+15_m+15 CRA0 to CRA7 PGA : A display data which are written to RAM. : Control data to set a column address of RAM. : Control data to set a page address of RAM. http://onsemi.com 8 0 0 0 1 0 1 LC450210PCH Application Note (3-6) “Set of display contrast” instruction When contrast adjuster is used, LCD drive bias voltage VLCD0 (High level) is set by “Set of display contrast” instruction. CE CL DI 0 1 0 0 1 1 0 1 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 0 1 0 1 1 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address (8 bits) Control data (16 bits) B0 to B3, A0 to A3 : CCB address. (=B2h) CT0 to CT5 : Control data to set a display contrast. Correspondence relation between the display data RAM and segment outputs The customer can write display data to the display data RAM in a lump by setting a page address and a column address of the RAM by control data. The display data of 120 bits (for 8 common outputs x 15 segment outputs) are written to the display data RAM in a lump by “Write display data to RAM (8 x 15 bits in a lump)” instruction. Besides, the display data of 256 bits (for 16 common outputs x 16 segment outputs) are written to the display data RAM in a lump by “Write display data to RAM (16 x 16 bits in a lump)” instruction. For details, refer to “Explanation of How to Write a Display Data RAM”. Table 3. Display data RAM address mapping Segment outputs Normal direction (SDIR=0) Reverse direction (SDIR=1) PGA=0 Page address PGA=1 S1 S2 S3 S4 ..... ..... S200 S199 S198 S197 D1_1 D2_1 D3_1 D4_1 D1_2 D2_2 D3_2 D4_2 D1_3 D2_3 D3_3 D4_3 D1_4 D2_4 D3_4 D4_4 D1_5 D2_5 D3_5 D4_5 D1_6 D2_6 D3_6 D4_6 D1_7 D2_7 D3_7 D4_7 D1_8 D2_8 D3_8 D4_8 D1_9 D2_9 D3_9 D4_9 D1_10 D2_10 D3_10 D4_10 D1_11 D2_11 D3_11 D4_11 D1_12 D2_12 D3_12 D4_12 D1_13 D2_13 D3_13 D4_13 D1_14 D2_14 D3_14 D4_14 D1_15 D2_15 D3_15 D4_15 D1_16 D2_16 D3_16 D4_16 ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... 00H 01H 02H 03H ..... S197 S198 S199 S200 Common address Normal direction (CDIR=0) Reverse direction (CDIR=1) S4 S3 S2 S1 D197_1 D198_1 D199_1 D200_1 0H 0H COM1 COM16 D197_2 D198_2 D199_2 D200_2 1H 1H COM2 COM15 D197_3 D198_3 D199_3 D200_3 2H 2H COM3 COM14 D197_4 D198_4 D199_4 D200_4 3H 3H COM4 COM13 D197_5 D198_5 D199_5 D200_5 4H 4H COM5 COM12 D197_6 D198_6 D199_6 D200_6 5H 5H COM6 COM11 D197_7 D198_7 D199_7 D200_7 6H 6H COM7 COM10 D197_8 D198_8 D199_8 D200_8 7H Line address 7H COM8 COM9 D197_9 D198_9 D199_9 D200_9 8H 8H COM9 COM8 D197_10 D198_10 D199_10 D200_10 9H LNA0 to LNA3 9H COM10 COM7 D197_11 D198_11 D199_11 D200_11 AH AH COM11 COM6 D197_12 D198_12 D199_12 D200_12 BH BH COM12 COM5 D197_13 D198_13 D199_13 D200_13 CH CH COM13 COM4 D197_14 D198_14 D199_14 D200_14 DH DH COM14 COM3 D197_15 D198_15 D199_15 D200_15 EH EH COM15 COM2 D197_16 D198_16 D199_16 D200_16 FH FH COM16 COM1 C4H C5H C6H Column address CRA0 to CRA7 http://onsemi.com 9 C7H Start LC450210PCH Application Note Explanation of the Clock Control (1) Setting of the Fundamental Clock Operating Mode (OC) The control data of the OC can set the internal oscillator operating mode or external clock operating mode. When the internal oscillator operating mode is set, clock generator begins to run after power saving mode is canceled (BU=“0”). This LCD system configuration example sets OC=“0” to use the internal oscillator operating mode. OC Fundamental clock operating mode The state of OSCI 0 1 Internal oscillator operating mode External clock operating mode Make sure to connect OSCI to VSS Input the clock of 300 [kHz](Typ.) The explanation mentioned above is used only to explain internal operation and how to use the LSI, and the characteristic of the products is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. LCD Driver LSI (LC450210PCH) Internal oscillator clock frequency fosc [kHz] OSCI Internal oscillator circuit clock Figure 5. Peripheral circuits configuration example of the external clock input pad (2) Setting of the Voltage Booster Clock Frequency (DBF0 to DBF2) The control data from DBF0 to DBF2 can set the voltage booster clock frequency. It is easy to evade the interference of the frequency of other devices by this setting. This LCD system configuration example sets DBF0=“0”, DBF1=“1” and DBF2=“1” to operate voltage booster clock frequency at 13.63 [kHz]. DBF0 DBF1 DBF2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Voltage Booster Clock Frequency (fcp) fosc/12 fosc/14 fosc/18 fosc/22 fosc/26 fosc/28 fosc/30 fosc/34 The voltage booster clock frequency when fosc is 300 [kHz] 25.00 [kHz] 21.43 [kHz] 16.66 [kHz] 13.63 [kHz] 11.54 [kHz] 10.71 [kHz] 10.00 [kHz] 8.82 [kHz] (3) Setting of the Frame Frequency for LCD Drive Waveforms (FC0 to FC3) The control data from FC0 to FC3 can set the LCD drive frame frequency (fo). There is a lot of flexibility for various LCDs (TN-LCD, VA/TN-LCD). VA (Vertical Alignment) type has the characteristic of high contrast and wants a high frequency. In addition, it is easy to evade the interference of the frequency of other devices by this setting. This LCD system configuration example sets FC0=“0”, FC1=“1”, FC2=“0” and FC3=“0” to operate LCD drive frame frequency at 101.9 [Hz]. FC0 FC1 FC2 FC3 0 0 0 1 0 0 LCD drive frame frequency (fo) 1/8duty 1/9duty 1/10duty 1/11duty 1/12duty 1/13duty 1/14duty 1/15duty 1/16duty 0 fosc/4352 <68.9[Hz]> fosc/4320 <69.4[Hz]> fosc/4320 <69.4[Hz]> fosc/4400 <68.2[Hz]> fosc/4320 <69.4[Hz]> fosc/4264 <70.4[Hz]> fosc/4256 <70.5[Hz]> fosc/4320 <69.4[Hz]> fosc/4352 <68.9[Hz]> 0 0 fosc/3712 <80.8[Hz]> fosc/3744 <80.1[Hz]> fosc/3760 <79.8[Hz]> fosc/3784 <79.3[Hz]> fosc/3744 <80.1[Hz]> fosc/3744 <80.1[Hz]> fosc/3808 <78.8[Hz]> fosc/3720 <80.7[Hz]> fosc/3712 <80.8[Hz]> 1 0 0 fosc/2944 fosc/2952 fosc/2960 fosc/2992 fosc/2976 fosc/2964 fosc/2968 fosc/3000 fosc/2944 <101.9[Hz]> <101.6[Hz]> <101.4[Hz]> <100.3[Hz]> <100.8[Hz]> <101.2[Hz]> <101.1[Hz]> <100.0[Hz]> <101.9[Hz]> 1 1 0 0 fosc/2368 fosc/2376 fosc/2400 fosc/2376 fosc/2400 fosc/2392 fosc/2408 fosc/2400 fosc/2368 <126.7[Hz]> <126.3[Hz]> <125.0[Hz]> <126.3[Hz]> <125.0[Hz]> <125.4[Hz]> <124.6[Hz]> <125.0[Hz]> <126.7[Hz]> 0 0 1 0 fosc/1984 fosc/1944 fosc/2000 fosc/1936 fosc/1968 fosc/1976 fosc/1960 fosc/1980 fosc/1984 <151.2[Hz]> <154.3[Hz]> <150.0[Hz]> <155.0[Hz]> <152.4[Hz]> <151.8[Hz]> <153.1[Hz]> <151.5[Hz]> <151.2[Hz]> 1 0 1 0 fosc/1696 fosc/1692 fosc/1720 fosc/1672 fosc/1728 fosc/1716 fosc/1708 fosc/1710 fosc/1696 <176.9[Hz]> <177.3[Hz]> <174.4[Hz]> <179.4[Hz]> <173.6[Hz]> <174.8[Hz]> <175.6[Hz]> <175.4[Hz]> <176.9[Hz]> http://onsemi.com 10 LC450210PCH Application Note LCD drive frame frequency (fo) 1/10duty 1/11duty 1/12duty 1/13duty 1/14duty 1/15duty 1/16duty FC0 FC1 FC2 FC3 0 1 1 0 fosc/1472 fosc/1476 fosc/1480 fosc/1496 fosc/1488 fosc/1482 fosc/1456 fosc/1500 fosc/1472 <203.8[Hz]> <203.3[Hz]> <202.7[Hz]> <200.5[Hz]> <201.6[Hz]> <202.4[Hz]> <206.0[Hz]> <200.0[Hz]> <203.8[Hz]> 1 1 1 0 fosc/1312 fosc/1332 fosc/1320 fosc/1320 fosc/1320 fosc/1326 fosc/1316 fosc/1350 fosc/1312 <228.7[Hz]> <225.2[Hz]> <227.3[Hz]> <227.3[Hz]> <227.3[Hz]> <226.2[Hz]> <228.0[Hz]> <222.2[Hz]> <228.7[Hz]> 0 0 0 1 fosc/1184 fosc/1188 fosc/1200 fosc/1188 fosc/1200 fosc/1196 fosc/1204 fosc/1200 fosc/1184 <253.4[Hz]> <252.5[Hz]> <250.0[Hz]> <252.5[Hz]> <250.0[Hz]> <250.8[Hz]> <249.2[Hz]> <250.0[Hz]> <253.4[Hz]> 1 0 0 1 fosc/1088 fosc/1080 fosc/1080 fosc/1100 fosc/1104 fosc/1118 fosc/1092 fosc/1080 fosc/1088 <275.7[Hz]> <277.8[Hz]> <277.8[Hz]> <272.7[Hz]> <271.7[Hz]> <268.3[Hz]> <274.7[Hz]> <277.8[Hz]> <275.7[Hz]> 0 1 0 1 fosc/1056 fosc/1044 fosc/1040 fosc/1056 fosc/1056 fosc/1040 fosc/1036 fosc/1050 fosc/1056 <284.1[Hz]> <287.4[Hz]> <288.5[Hz]> <284.1[Hz]> <284.1[Hz]> <288.5[Hz]> <289.6[Hz]> <285.7[Hz]> <284.1[Hz]> 1 1 0 1 fosc/992 fosc/1008 fosc/1000 fosc/990 fosc/984 fosc/988 fosc/980 fosc/990 fosc/992 <302.4[Hz]> <297.6[Hz]> <300.0[Hz]> <303.0[Hz]> <304.9[Hz]> <303.6[Hz]> <306.1[Hz]> <303.0[Hz]> <302.4[Hz]> 0 0 1 1 fosc/960 fosc/972 fosc/960 fosc/946 fosc/960 fosc/962 fosc/952 fosc/960 fosc/960 <312.5[Hz]> <308.6[Hz]> <312.5[Hz]> <317.1[Hz]> <312.5[Hz]> <311.9[Hz]> <315.1[Hz]> <312.5[Hz]> <312.5[Hz]> 1 0 1 1 fosc/928 fosc/936 fosc/920 fosc/924 fosc/936 fosc/936 fosc/924 fosc/930 fosc/928 <323.3[Hz]> <320.5[Hz]> <326.1[Hz]> <324.7[Hz]> <320.5[Hz]> <320.5[Hz]> <324.7[Hz]> <322.6[Hz]> <323.3[Hz]> 0 1 1 1 fosc/896 fosc/900 fosc/900 fosc/902 fosc/888 fosc/884 fosc/896 fosc/900 fosc/896 <334.8[Hz]> <333.3[Hz]> <333.3[Hz]> <332.6[Hz]> <337.8[Hz]> <339.4[Hz]> <334.8[Hz]> <333.3[Hz]> <334.8[Hz]> 1 1 1 1 fosc/864 fosc/864 fosc/860 fosc/858 fosc/864 fosc/858 fosc/868 fosc/870 fosc/864 <347.2[Hz]> <347.2[Hz]> <348.8[Hz]> <349.7[Hz]> <347.2[Hz]> <349.7[Hz]> <345.6[Hz]> <344.8[Hz]> <347.2[Hz]> 1/8duty 1/9duty The value of “< >” is an LCD drive frame frequency when fosc is 300 [kHz]. The explanation mentioned above is used only to explain internal operation and how to use the LSI, and the characteristic of the products is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. http://onsemi.com 11 LC450210PCH Application Note Explanation of the Internal Circuit Control (1) State Setting of the Voltage Booster Circuit, Contrast Adjuster Circuit and LCD Drive Bias Voltage Generator Circuit (DBC, CTC0, CTC1) The control data of the DBC can set the voltage booster circuit to the run state or stop state. The control data of the CT0 and CT1 can set the contrast adjuster circuit and LCD drive bias voltage generator circuit to the run state or stop state. This LCD system configuration example sets DBC=“1”, CTC0=“1” and CTC1=“1” to use the all circuits (voltage booster circuit, contrast adjuster circuit and LCD drive bias voltage generator circuit). DBC CTC0 CTC1 Voltage booster circuit Contrast adjuster circuit 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Stop Stop Stop Stop Run Run Run Run Stop Stop Run Run Stop Stop Run Run LCD drive bias voltage generator circuit Stop Run Stop Run Stop Run Stop Run This LCD system configuration example sets as follows to use the quintuple voltage booster circuit. VBTI1 : The REGE pad is set to VDD, and input the voltage from 4.5 [V] to VDD [V]. VBTI2 : The REGE pad is set to VDD, and outputs the base voltage for voltage booster. VLCD : The quintuple VBTI2 voltage is outputted. This LCD system configuration example sets as follows to use the contrast adjuster circuit. VLCD0 : The VLCD0 outputs the LCD drive bias voltage (5/5 level) according to control data from CT0 to CT5 in “Set of display contrast” instruction. Make sure to connect a capacitor between VLCD0 and VLCD5. This LCD system configuration example sets as follows to use the LCD drive bias voltage generator circuit and 1/5 bias circuit. VLCD1 : The VLCD outputs the LCD drive bias voltage (4/5 level). Make sure to connect a capacitor between VLCD1 and VLCD5. VLCD2 : The VLCD outputs the LCD drive bias voltage (3/5 level). Make sure to connect a capacitor between VLCD2 and VLCD5. VLCD3 : The VLCD outputs the LCD drive bias voltage (2/5 level). Make sure to connect a capacitor between VLCD3 and VLCD5. VLCD4 : The VLCD outputs the LCD drive bias voltage (1/5 level). Make sure to connect a capacitor between VLCD4 and VLCD5. VLCD5 : Make sure to connect VLCD5 to VSS (0/5 level). LCD Driver LSI (LC450210PCH) 5.0 [V] REGE VBTI1 5.0 [V] VLCD 16 [V] VBTI2 Cbt Cbt CP1P C1 CP12N C2 CP2P CP3P C3 CP34N C4 CP4P Cvl Quintuple Voltage Booster Contrast Adjuster LCD Drive Bias Voltage Generator VLCD0 Cvm 12 [V] VLCD1 Cvm VLCD2 Cvm 9.6 [V] VLCD3 Cvm VLCD4 Cvm VLCD5 7.2 [V] 4.8 [V] 2.4 [V] 0 [V] Figure 6. Peripheral circuits configuration example of the internal circuit for LC450210PCH http://onsemi.com 12 1/5 bias LC450210PCH Application Note (2) Setting of the LCD Drive Bias Voltage Using the Contrast Adjuster Circuit (CT0 to CT5) The control data from CT0 to CT5 can set the LCD drive bias voltage (VLCD0) using the contrast adjuster circuit. However, satisfy a condition of VLCD0 ≤ VLCD - 2.4 [V]. This LCD system configuration example sets CT0=“0”, CT1=“1”, CT2=“1”, CT3=“1”, CT4=“0” and CT5=“0” to use the LCD drive bias voltage (VLCD0) as 12.0 [V]. When VBTI1=5.0 [V], REGE=VDD, quintuple voltage booster and contrast adjuster are used, LCD power supply voltage (VLCD) becomes 16 [V] that quintupled the VBTI2 output of 3.2 [V] (Typical electrical characteristics). In addition, when the VBTI2 output of 3.3 [V] (Maximum electrical characteristics), the VLCD is 16.5 [V]. Moreover, when the VBTI2 output of 3.09 [V] (Minimum electrical characteristics), the VLCD is 15.45 [V]. The customer can select from step 7 (13.05 [V]) to step 63 (4.65 [V]) at the time of this setting state. When these are set from step 0 (14.10 [V]) to step 6 (13.20 [V]), the VLCD0 voltage is not guaranteed. VLCD0 [V] 13.05 ≥ 2.4V VLCD=15.45 [V] 4.65 0 7 63 Value from CT0 to CT5 Figure 7. Adjustment range of the LCD drive bias voltage (VLCD0) Table 4. Setting of settable contrast adjustment Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 VLCD0 voltage not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed 13.05 V 12.90 V 12.75 V 12.60 V 12.45 V 12.30 V 12.15 V 12.00 V 11.85 V 11.70 V 11.55 V 11.40 V 11.25 V 11.10 V 10.95 V 10.80 V 10.65 V 10.50 V 10.35 V 10.20 V 10.05 V 9.90 V 9.75 V 9.60 V 9.45 V Step 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 VLCD0 voltage 9.30 V 9.15 V 9.00 V 8.85 V 8.70 V 8.55 V 8.40 V 8.25 V 8.10 V 7.95 V 7.80 V 7.65 V 7.50 V 7.35 V 7.20 V 7.05 V 6.90 V 6.75 V 6.60 V 6.45 V 6.30 V 6.15 V 6.00 V 5.85 V 5.70 V 5.55 V 5.40 V 5.25 V 5.10 V 4.95 V 4.80 V 4.65 V The explanation mentioned above is used only to explain internal operation and how to use the LSI, and the characteristic of the products is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. http://onsemi.com 13 LC450210PCH Application Note (3) Explanation of the Setting to the Discharge Condition The voltage booster circuit, the contrast adjuster circuit and the LCD drive bias voltage generator circuit have the discharge circuit to discharge an electric charge of the external capacitor. When the voltage booster is set to the discharge condition, the VLCD level is same as VBTI1 level. When the contrast adjuster and the LCD drive bias voltage generator are set to the discharge condition, the levels from VLCD0 to VLCD4 are same as VLCD5 level. Table 5. Discharge condition setting in the internal circuit Pad Control data RES BU DBC Low High X 0 High 1 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CTC0 CTC1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage booster circuit (VLCD output) Contrast adjuster circuit (VLCD0 output) Discharge Stop (High-impedance) Stop (High-impedance) Stop (High-impedance) Stop (High-impedance) Run (Voltage output) Run (Voltage output) Run (Voltage output) Run (Voltage output) Stop (High-impedance) Stop (High-impedance) Stop (High-impedance) Stop (High-impedance) Discharge (VBTI1 level) Discharge (VBTI1 level) Discharge (VBTI1 level) Discharge (VBTI1 level) Discharge Stop (High-impedance) Stop (High-impedance) Run (Voltage output) Run (Voltage output) Stop (High-impedance) Stop (High-impedance) Run (Voltage output) Run (Voltage output) Stop (High-impedance) Stop (High-impedance) Discharge (VLCD5 level) Discharge (VLCD5 level) Stop (High-impedance) Stop (High-impedance) Discharge (VLCD5 level) Discharge (VLCD5 level) X : Don't care (0 or 1) http://onsemi.com 14 LCD drive bias voltage generator circuit (VLCD1 to VLCD4 outputs) Discharge Stop (High-impedance) Run (Voltage output) Stop (High-impedance) Run (Voltage output) Stop (High-impedance) Run (Voltage output) Stop (High-impedance) Run (Voltage output) Stop (High-impedance) Discharge (VLCD5 level) Stop (High-impedance) Discharge (VLCD5 level) Stop (High-impedance) Discharge (VLCD5 level) Stop (High-impedance) Discharge (VLCD5 level) LC450210PCH Application Note Explanation of the LCD Drive Control LCD Driver LSI (LC450210PCH) S193 to S200 S1 to S192 COM1 to COM16 8 192 16 AM FM CD USB AUTO SCN RPT RDM LCD Panel (16x16 dot font) x 12digits + 8 icons = 3,080 segments Figure 8. Peripheral circuits configuration example of the LCD driver outputs (1) LCD Drive Waveform It is explanation about the drive type of the 1/16 duty and 1/5 bias. The common outputs (COM1 to COM16) repeat VLCD0 level, VLCD1 level, VLCD4 level and VLCD5 level in turn. On the other hand, the segment outputs (S1 to S200) repeat VLCD0 level, VLCD2 level, VLCD3 level and VLCD5 level by a state of display ON/OFF (Display data setting register is 1/0). When the LCD segment is ON (It interrupt light), the potential difference of segment output and common output becomes VLCD0 level. When the LCD segment is OFF (It penetrate light), the potential difference of segment output and common output becomes 1/5 VLCD0 level. This drive method assigns a sixteenth of a frame to control of ON/OFF of one segments. Thus, this drive method is called the “1/16 duty and 1/5 bias drive”. When set the 1/16 duty, the 1/5 bias and the line inversion drive mode, the following figure shows the LCD drive waveform. VLCD0 VLCD1 COM1 output VLCD4 VLCD5 VLCD0 VLCD1 COM2 output VLCD4 VLCD5 VLCD0 VLCD1 COM3 output VLCD4 VLCD5 VLCD0 VLCD1 COM16 output VLCD4 VLCD5 VLCD0 LCD driver output when all LCD segments corresponding from COM1 to COM16 are off. VLCD2 VLCD3 VLCD5 VLCD0 LCD driver output when only LCD segment corresponding to COM1 is on. VLCD2 VLCD3 VLCD5 VLCD0 LCD driver output when only LCD segment corresponding to COM2 is on. VLCD2 VLCD3 VLCD5 VLCD0 LCD driver output when LCD segments corresponding from COM4 to COM6 are on. VLCD2 VLCD3 VLCD5 VLCD0 LCD driver output when all LCD segments corresponding from COM1 to COM16 are on. VLCD2 VLCD3 VLCD5 1 line 1 frame (fo) Figure 9. When the 1/16 duty, the 1/5 bias and the line inversion are set, waveform of the LCD driver output http://onsemi.com 15 LC450210PCH Application Note (2) Setting of the LCD Drive Duty (DT0 to DT3) The control data from DT0 to DT3 can set the LCD drive duty from 1/8 to 1/16. The customer can select the LCD drive duty by the specifications of an LCD panel used. This LCD system configuration example is using LCD panel of the 1/16 duty. Therefore, this system sets DT0=“1”, DT1=“1”, DT2=“1” and DT3=“1”. DT0 DT1 DT2 DT3 LCD drive duty type 0 1 0 1 0 1 0 1 X 0 0 1 1 0 0 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 0 0 0 0 1 1/8 duty 1/9 duty 1/10 duty 1/11 duty 1/12 duty 1/13 duty 1/14 duty 1/15 duty 1/16 duty The state of COM1 to COM16 Pads which output pulse of Pads which output scan pulse display off Normal scan Reversed scan Normal scan Reversed scan CDIR=“0” CDIR=“1” CDIR=“0” CDIR=“1” COM1 to COM8 COM16 to COM9 COM9 to COM16 COM8 to COM1 COM1 to COM9 COM16 to COM8 COM10 to COM16 COM7 to COM1 COM1 to COM10 COM16 to COM7 COM11 to COM16 COM6 to COM1 COM1 to COM11 COM16 to COM6 COM12 to COM16 COM5 to COM1 COM1 to COM12 COM16 to COM5 COM13 to COM16 COM4 to COM1 COM1 to COM13 COM16 to COM4 COM14 to COM16 COM3 to COM1 COM1 to COM14 COM16 to COM3 COM15, COM16 COM2, COM1 COM1 to COM15 COM16 to COM2 COM16 COM1 COM1 to COM16 COM16 to COM1 --- --- X : Don't care (0 or 1) VLCD0 VLCD1 VLCD0 VLCD1 Common Common VLCD4 VLCD5 VLCD4 VLCD5 VLCD0 VLCD2 VLCD3 Segment VLCD0 VLCD2 VLCD3 Segment VLCD5 VLCD5 1 line 1 line 1 frame = 8 line 1 frame = 16 line Figure 10. LCD drive waveform when 1/8 duty Figure 11. LCD drive waveform when 1/16 duty (3) Setting of the LCD Drive Bias (DR) The control data of the DR can set the 1/4 bias or 1/5 bias. Typically, the optimum LCD drive bias (maximum contrast) is determined according to an LCD drive duty, and it shown in the following equations. The customer can select the LCD drive bias by the specifications of an LCD panel used. This LCD system configuration example sets DR=“1” to use the 1/5 bias. Equations : (duty) + 1 For example, this LCD system configuration example is using LCD panel of 1/16 duty. Hence, 16 + 1 = 5 DR LCD drive bias type 0 1/4 bias VLCD0 1 1/5 bias VLCD0 VLCD0 The state from VLCD0 to VLCD5 VLCD2 VLCD3 VLCD4 Make sure to 3/4 VLCD0 2/4 VLCD0 1/4 VLCD0 open VLCD3 4/5 VLCD0 3/5 VLCD0 2/5 VLCD0 1/5 VLCD0 VLCD1 VLCD0 = 12V VLCD1 = 9V Common VLCD4 = 3V VLCD5 = 0V VLCD2 = 6V VSS VSS VLCD0 = 12V VLCD1 = 9.6V Common VLCD4 = 2.4V VLCD5 = 0V VLCD0 = 12V Segment VLCD5 VLCD0 = 12V Segment VLCD5 = 0V Figure 12. LCD drive waveform when 1/4 bias http://onsemi.com 16 VLCD2 = 7.2V VLCD3 = 4.8V VLCD5 = 0V Figure 13. LCD drive waveform when 1/5 bias LC450210PCH Application Note (4) Setting of the Inversion Drive for LCD Drive Waveforms (WVC) The control data of the WVC can set the line inversion or frame inversion. Typically, the line inversion drive can do display of high contrast, but there is more power consumption than frame inversion drive. In addition, the frame inversion drive is low little power consumption, but contrast decreases than line inversion drive. Therefore, the customer can select the inversion drive type by a purpose and the characteristic of the LCD panel used. This LCD system configuration example sets WVC=“0” to use the line inversion. WVC Inversion drive type of LCD drive waveforms 0 1 Line inversion Frame inversion VLCD0 VLCD1 Common VLCD0 VLCD1 Common VLCD4 VLCD5 VLCD4 VLCD5 VLCD0 VLCD2 VLCD3 Segment VLCD0 VLCD2 VLCD3 Segment VLCD5 VLCD5 1 line 1 line 1 frame 1 frame Figure 14. LCD drive waveform when line inversion Figure 15. LCD drive waveform when frame inversion (5) Setting of the Scan Direction for the Common Output (CDIR) The control data of the CDIR can set the normal scan direction or reverse scan direction. Typically, the scan direction is a bottom from the top. The customer can select the scan direction for the common output by the mounted LSI position and the direction of the LCD panel. The SDIR and CDIR are often set in combination. This LCD system configuration example sets CDIR=“0”. CDIR Scan direction Scan sequence 0 1 Normal scan Reverse scan COM1 => COM2 => COM3 => ..... => COM15 =>COM16 COM16 => COM15 => COM14 => ..... => COM2 => COM1 Scan direction COM1 LCD Panel S200 S1 COM16 Normal Reverse LCD Panel COM16 S1 Scan direction COM1 S200 Figure 16. When LSI is mounted to become the normal scan direction http://onsemi.com 17 Figure 17. When LSI is mounted to become the reverse scan direction LC450210PCH Application Note (6) Setting of the Correspondence of a Segment Output and a Column Address of RAM (SDIR) The control data of the SDIR can set the correspondence relation between a column address of the display data RAM and a segment output. The customer can select the correspondence relation between a column address of the display data RAM and a segment output by the mounted LSI position and the direction of the LCD panel. The SDIR and CDIR are often set in combination. The display of LCD does not change by only changing the setting of SDIR data. When display data is written to RAM, column address of the display data RAM is converted. Then display data is saved to there. This LCD system configuration example sets SDIR=“0”. SDIR Direction corresponding to the segment output 0 Normal direction 1 Reverse direction (1,1) Microcontroller address mapping (1,16) The segment output of S1 corresponds to a column address (CRA0 to CRA7) of 00H, and the segment output of S200 corresponds to a column address (CRA0 to CRA7) of C7H. The segment output of S1 corresponds to a column address (CRA0 to CRA7) of C7H, and the segment output of S200 corresponds to a column address (CRA0 to CRA7) of 00H. (200,1) (1,1) (200,16) (1,16) same (D1_1) (D1_16) Column address Display data RAM address mapping 00H Correspondence relation between a column address of the display data RAM and a segment output (D200_1) 0H (D1_1) (D200_16) FH (D1_16) Column address C7H Display data RAM address mapping 00H Line address (D200_1) 0H (D200_16) FH C7H COM1 frontside (200,16) reverse (CRA0 to CRA7) COM1 LCD Panel S1 (200,1) same Line address normal (CRA0 to CRA7) Microcontroller address mapping LCD Panel backside COM16 S200 S200 Figure 18. When LSI is mounted to become the normal direction corresponding to the segment output COM16 S1 Figure 19. When LSI is mounted to become the reverse direction corresponding to the segment output (7) Setting of the ON/OFF Reverse Display (PNC) The control data of the PNC can set the normal display mode or the reverse display mode. When display states are normal mode (SC0=“0”, SC1=“0”), the setting of PNC becomes effective. There are two kinds of an LCD panels: normally-white and normally-black. When the normally-black LCD panel, the display data of the microcontroller are same and can display correctly by setting this PNC to “1”. When display data (Dn_m) When display data (Dn_m) are set to “0” are set to “1” PNC Display state 0 Normal mode The segment is OFF display The segment is ON display 1 Reverse display mode The segment is ON display The segment is OFF display Note : Display data “Dn_m” is from D1_1 to D200_16. http://onsemi.com 18 LC450210PCH Application Note Microcontroller 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 LC450210PCH Display data RAM 0 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 1 Normally-white LCD panel Normally-black LCD panel Normally-white LCD panel Normally-black LCD panel PNC=“0” PNC=“1” Figure 20. Relations of display data and the LCD panel display (8) Setting of the Display State (SC0, SC1) The control data of the SC0 and SC1 can set the normal mode, the display OFF mode, the display ON mode or the display forced OFF mode. When the display forced OFF mode, the segment outputs and the common outputs are outputted to VLCD5 level. Therefore, this setting is used to discharge the capacity of the liquid crystal display cell. SC0 SC1 0 0 1 0 1 0 1 1 Display state Normal mode (Displayable) Display OFF mode Display ON mode Display forced OFF mode Segment outputs state (from S1 to S200) Waveform corresponding to the display data OFF waveform ON waveform VLCD5 level Common outputs state (from COM1 to COM16) Scan pulse Scan pulse Scan pulse VLCD5 level (9) Setting of the Power Saving Mode (BU) The control data of the BU can set the normal mode or power saving mode. When the power saving mode is set, all the internal circuits are stopped, and it becomes a low power consumption state. The LCD is not displayed then. BU Low power consumption mode 0 Normal mode Internal operating conditions Normal mode • Segment outputs (S1 to S200) are VLCD5 level. • Common outputs (COM1 to COM16) are VLCD5 level. • LCD driver block power supply output (VLCD) is same as VBTI1 level • LCD drive bias voltage outputs (from VLCD0 to VLCD4) are same as VLCD5 level. 1 Power saving mode • The internal oscillator circuit is stopped. • External clock input is not received. • The voltage booster circuit is stopped and discharge state. • The contrast adjuster circuit is stopped and discharge state. • The LCD drive bias voltage generator circuit is stopped and discharge state. • The reception of serial data is possible. (Registers are updated) http://onsemi.com 19 LC450210PCH Application Note (10) Setting of the line address of RAM (LNA0 to LNA3) The control data from LNA0 to LNA3 can set a line address of RAM. The common address circuit is reset at the trigger of internal frame signal, and this circuit counts up synchronized with the scanning signal. Therefore, generates common address by this circuit. The common address increases from the top of the display line to the number of display lines set by control data of the LCD drive duty (DT0 to DT3). When the scan direction is set to normal scan (CDIR=“0”), the common address begins outputting from COM1. When the scan direction is set to reverse scan (CDIR=“1”), the common address begins outputting from COM16. The RAM data of 200 bits on the line address set by the line counter are read from display data RAM. And these RAM data is latched to the display data latch. A controller writing to the display data RAM and the this LSI reading from the display data latch operate independently. Therefore, even if data is rewritten with the asynchronous, the display is not influenced. This LCD system configuration example sets LNA0=“0”, LNA1=“0”, LNA2=“0” and LNA3=“0” to begin to read it from a line address of “0H”. Table 6. Display data RAM address mapping when a line address (LNA0 to LNA3) is set to “0H” Segment outputs Normal direction (SDIR=0) PGA=0 Page address PGA=1 ..... S1 S2 S3 S4 D1_1 D2_1 D3_1 D4_1 D1_2 D2_2 D3_2 D4_2 D1_3 D2_3 D3_3 D4_3 D1_4 D2_4 D3_4 D4_4 D1_5 D2_5 D3_5 D4_5 D1_6 D2_6 D3_6 D4_6 D1_7 D2_7 D3_7 D4_7 D1_8 D2_8 D3_8 D4_8 D1_9 D2_9 D3_9 D4_9 D1_10 D2_10 D3_10 D4_10 D1_11 D2_11 D3_11 D4_11 D1_12 D2_12 D3_12 D4_12 D1_13 D2_13 D3_13 D4_13 D1_14 D2_14 D3_14 D4_14 D1_15 D2_15 D3_15 D4_15 D1_16 D2_16 D3_16 D4_16 ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... 00H 01H 02H 03H ..... Common address Normal direction (CDIR=0) S197 S198 S199 S200 D197_1 D198_1 D199_1 D200_1 0H 0H COM1 D197_2 D198_2 D199_2 D200_2 1H 1H COM2 D197_3 D198_3 D199_3 D200_3 2H 2H COM3 D197_4 D198_4 D199_4 D200_4 3H 3H COM4 D197_5 D198_5 D199_5 D200_5 4H 4H COM5 D197_6 D198_6 D199_6 D200_6 5H 5H COM6 D197_7 D198_7 D199_7 D200_7 6H 6H COM7 D197_8 D198_8 D199_8 D200_8 7H Line address 7H COM8 D197_9 D198_9 D199_9 D200_9 8H 8H COM9 D197_10 D198_10 D199_10 D200_10 9H LNA0 to LNA3 9H COM10 D197_11 D198_11 D199_11 D200_11 AH AH COM11 D197_12 D198_12 D199_12 D200_12 BH BH COM12 D197_13 D198_13 D199_13 D200_13 CH CH COM13 D197_14 D198_14 D199_14 D200_14 DH DH COM14 D197_15 D198_15 D199_15 D200_15 EH EH COM15 D197_16 D198_16 D199_16 D200_16 FH FH COM16 Common address Normal direction (CDIR=0) C4H C5H C6H Start C7H Column address CRA0 to CRA7 Table 7. Display data RAM address mapping when a line address (LNA0 to LNA3) is set to “4H” Segment outputs Normal direction (SDIR=0) PGA=0 Page address PGA=1 ..... S1 S2 S3 S4 D1_1 D2_1 D3_1 D4_1 D1_2 D2_2 D3_2 D4_2 D1_3 D2_3 D3_3 D4_3 D1_4 D2_4 D3_4 D4_4 D1_5 D2_5 D3_5 D4_5 D1_6 D2_6 D3_6 D4_6 D1_7 D2_7 D3_7 D4_7 D1_8 D2_8 D3_8 D4_8 D1_9 D2_9 D3_9 D4_9 D1_10 D2_10 D3_10 D4_10 D1_11 D2_11 D3_11 D4_11 D1_12 D2_12 D3_12 D4_12 D1_13 D2_13 D3_13 D4_13 D1_14 D2_14 D3_14 D4_14 D1_15 D2_15 D3_15 D4_15 D1_16 D2_16 D3_16 D4_16 ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... 00H 01H 02H 03H ..... S197 S198 S199 S200 D197_1 D198_1 D199_1 D200_1 0H CH COM13 D197_2 D198_2 D199_2 D200_2 1H DH COM14 D197_3 D198_3 D199_3 D200_3 2H EH COM15 D197_4 D198_4 D199_4 D200_4 3H FH COM16 D197_5 D198_5 D199_5 D200_5 4H D197_6 D198_6 D199_6 D200_6 5H D197_7 D198_7 D199_7 D200_7 6H D197_8 D198_8 D199_8 D200_8 7H D197_9 D198_9 D199_9 D200_9 8H D197_10 D198_10 D199_10 D200_10 9H D197_11 D198_11 D199_11 D200_11 D197_12 D198_12 D199_12 D200_12 0H COM1 1H COM2 Line address 2H COM3 3H COM4 LNA0 to LNA3 4H COM5 5H COM6 AH 6H COM7 BH 7H COM8 D197_13 D198_13 D199_13 D200_13 CH 8H COM9 D197_14 D198_14 D199_14 D200_14 DH 9H COM10 D197_15 D198_15 D199_15 D200_15 EH AH COM11 D197_16 D198_16 D199_16 D200_16 FH BH COM12 C4H C5H Column address CRA0 to CRA7 http://onsemi.com 20 C6H C7H Start LC450210PCH Application Note Table 8. Display data RAM address mapping when a line address (LNA0 to LNA3) is set to “0H” Segment outputs Normal direction (SDIR=0) PGA=0 Page address PGA=1 ..... S1 S2 S3 S4 D1_1 D2_1 D3_1 D4_1 D1_2 D2_2 D3_2 D4_2 D1_3 D2_3 D3_3 D4_3 D1_4 D2_4 D3_4 D4_4 D1_5 D2_5 D3_5 D4_5 D1_6 D2_6 D3_6 D4_6 D1_7 D2_7 D3_7 D4_7 D1_8 D2_8 D3_8 D4_8 D1_9 D2_9 D3_9 D4_9 D1_10 D2_10 D3_10 D4_10 D1_11 D2_11 D3_11 D4_11 D1_12 D2_12 D3_12 D4_12 D1_13 D2_13 D3_13 D4_13 D1_14 D2_14 D3_14 D4_14 D1_15 D2_15 D3_15 D4_15 D1_16 D2_16 D3_16 D4_16 ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... 00H 01H 02H 03H ..... Common address Reverse direction (CDIR=1) S197 S198 S199 S200 D197_1 D198_1 D199_1 D200_1 0H 0H COM16 D197_2 D198_2 D199_2 D200_2 1H 1H COM15 D197_3 D198_3 D199_3 D200_3 2H 2H COM14 D197_4 D198_4 D199_4 D200_4 3H 3H COM13 D197_5 D198_5 D199_5 D200_5 4H 4H COM12 D197_6 D198_6 D199_6 D200_6 5H 5H COM11 D197_7 D198_7 D199_7 D200_7 6H 6H COM10 D197_8 D198_8 D199_8 D200_8 7H Line address 7H COM9 D197_9 D198_9 D199_9 D200_9 8H 8H COM8 D197_10 D198_10 D199_10 D200_10 9H LNA0 to LNA3 9H COM7 D197_11 D198_11 D199_11 D200_11 AH AH COM6 D197_12 D198_12 D199_12 D200_12 BH BH COM5 D197_13 D198_13 D199_13 D200_13 CH CH COM4 D197_14 D198_14 D199_14 D200_14 DH DH COM3 D197_15 D198_15 D199_15 D200_15 EH EH COM2 D197_16 D198_16 D199_16 D200_16 FH FH COM1 Common address Reverse direction (CDIR=1) C4H C5H C6H Start C7H Column address CRA0 to CRA7 Table 9. Display data RAM address mapping when a line address (LNA0 to LNA3) is set to “4H” Segment outputs Normal direction (SDIR=0) PGA=0 Page address PGA=1 ..... S1 S2 S3 S4 D1_1 D2_1 D3_1 D4_1 D1_2 D2_2 D3_2 D4_2 D1_3 D2_3 D3_3 D4_3 D1_4 D2_4 D3_4 D4_4 D1_5 D2_5 D3_5 D4_5 D1_6 D2_6 D3_6 D4_6 D1_7 D2_7 D3_7 D4_7 D1_8 D2_8 D3_8 D4_8 D1_9 D2_9 D3_9 D4_9 D1_10 D2_10 D3_10 D4_10 D1_11 D2_11 D3_11 D4_11 D1_12 D2_12 D3_12 D4_12 D1_13 D2_13 D3_13 D4_13 D1_14 D2_14 D3_14 D4_14 D1_15 D2_15 D3_15 D4_15 D1_16 D2_16 D3_16 D4_16 ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... 00H 01H 02H 03H ..... S197 S198 S199 S200 D197_1 D198_1 D199_1 D200_1 0H CH COM4 D197_2 D198_2 D199_2 D200_2 1H DH COM3 D197_3 D198_3 D199_3 D200_3 2H EH COM2 D197_4 D198_4 D199_4 D200_4 3H FH COM1 D197_5 D198_5 D199_5 D200_5 4H D197_6 D198_6 D199_6 D200_6 5H D197_7 D198_7 D199_7 D200_7 6H D197_8 D198_8 D199_8 D200_8 7H D197_9 D198_9 D199_9 D200_9 8H D197_10 D198_10 D199_10 D200_10 9H D197_11 D198_11 D199_11 D200_11 D197_12 D198_12 D199_12 D200_12 0H COM16 1H COM15 Line address 2H COM14 3H COM13 LNA0 to LNA3 4H COM12 5H COM11 AH 6H COM10 BH 7H COM9 D197_13 D198_13 D199_13 D200_13 CH 8H COM8 D197_14 D198_14 D199_14 D200_14 DH 9H COM7 D197_15 D198_15 D199_15 D200_15 EH AH COM6 D197_16 D198_16 D199_16 D200_16 FH BH COM5 C4H C5H Column address CRA0 to CRA7 http://onsemi.com 21 C6H C7H Start LC450210PCH Application Note Explanations of How to Write a Display Data RAM (1) LCD panel segment allotment This LCD system configuration example uses the LCD panel of the segment allotment as shown below. When the LCD panel of 1/16 duty is used, the customer sets a page address (PGA) and a column address (CRA0 to CRA7) by “Write display data to RAM (16 x 16 bits in a lump)” instruction, and display data of 256 bits (16 common outputs x 16 segment outputs)” is written to the display data RAM in a lump. COM1 S193 AM S194 FM S195 CD S196 S197 USB AUTO S198 S199 SCN RPT S200 COM9 RDM S1.......S16 S17.....S32 S33.....S48 S49.....S64 S65.....S80 S81.....S96 S97....S112 S113...S128 S129...S144 S145...S160 S161...S176 S177...S192 1st digit 2nd digit 3rd digit 4th digit 5th digit 6th digit 7th digit COM8 8th digit 9th digit 10th digit 11th digit 12th digit COM16 LCD Driver LSI COM9 COM1 FPC/FFC LCD Panel (16x16 dot font) x 12digits + 8 icons = 3,080 segments Segment outputs Normal direction (SDIR=0) S1 ..... D1_1 ..... D1_2 Page address PGA=0 D1_3 D1_4 D1_5 D1_6 D1_7 D1_8 D1_9 D1_10 Page address PGA=1 D1_11 D1_12 D1_13 D1_14 D1_15 D1_16 Allotment ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... ..... S17 ..... D16_1 D17_1 ..... D16_2 D17_2 D16_3 D17_3 D16_4 D17_4 D16_5 D17_5 D16_6 D17_6 D16_7 D17_7 D16_8 D17_8 D16_9 D17_9 D16_10 D17_10 D16_11 D17_11 D16_12 D17_12 D16_13 D17_13 D16_14 D17_14 D16_15 D17_15 D16_16 D17_16 ..... ..... ..... ..... ..... ..... ..... 2nd digit ..... 12th digit 10H ..... BFH S16 1st digit 00H ..... 0FH ..... ..... ..... ..... ..... ..... ..... ..... S192 S193 S194 S195 S196 D192_1 D193_1 (AM) D194_1 (PM) D195_1 (CD) D196_1 (USB) S197 S198 S199 S200 D197_1 D198_1 D199_1 D200_1 D192_2 D193_2 D194_2 D195_2 D196_2 D197_2 D198_2 D199_2 D200_2 D192_3 D193_3 D194_3 D195_3 D196_3 D197_3 D198_3 D199_3 D200_3 D192_4 D193_4 D194_4 D195_4 D196_4 D197_4 D198_4 D199_4 D200_4 D192_5 D193_5 D194_5 D195_5 D196_5 D197_5 D198_5 D199_5 D200_5 D192_6 D193_6 D194_6 D195_6 D196_6 D197_6 D198_6 D199_6 D200_6 D192_7 D193_7 D194_7 D195_7 D196_7 D197_7 D198_7 D199_7 D200_7 D192_8 D193_8 D194_8 D195_8 D196_8 D197_8 D198_8 D199_8 D200_8 D192_9 D193_9 D194_9 D195_9 D196_9 D197_9 (AUTO) D198_9 (SCN) D199_9 (RPT) D200_9 (RDM) D192_10 D193_10 D194_10 D195_10 D196_10 D197_10 D198_10 D199_10 D200_10 D192_11 D193_11 D194_11 D195_11 D196_11 D197_11 D198_11 D199_11 D200_11 D192_12 D193_12 D194_12 D195_12 D196_12 D197_12 D198_12 D199_12 D200_12 D192_13 D193_13 D194_13 D195_13 D196_13 D197_13 D198_13 D199_13 D200_13 D192_14 D193_14 D194_14 D195_14 D196_14 D197_14 D198_14 D199_14 D200_14 D192_15 D193_15 D194_15 D195_15 D196_15 D197_15 D198_15 D199_15 D200_15 D192_16 D193_16 D194_16 D195_16 D196_16 D197_16 D198_16 D199_16 D200_16 icon C0H C1H C2H C3H C4H C5H C6H C7H Column address CRA0 to CRA7 Figure 21. Relations between an LCD panel and the segment of the LCD driver LSI (2) Setting of the column address (CRA0 to CRA7) The control data from CRA0 to CRA7 can set a column address of RAM. The settable range of a column address from CRA0 to CRA7 are from “00H” to “C7H”. When a column address is set more than “B9H”, display data is written from start position and the overflowed data from RAM is canceled. (3) Setting of the page address (PGA) The control data of the PGA can set a page address of RAM. When the display data of 256 bits are written to the display data RAM in a lump by “Write display data to RAM (16 x 16 bits in a lump)” instruction, the recommended setting of the page address (PGA) is “0”. When PGA is set to “1”, display data is written from start position and the overflowed data from RAM is canceled. http://onsemi.com 22 LC450210PCH Application Note (4) Setting of the display data which are written to RAM (Dn_m, Dn_m+1 to Dn+15_m+15) The control data from Dn_m to Dn+15_m+15 can set a display data which are written to RAM. The start position of writing to RAM is set by the data from CRA0 to CRA7 and PGA. At this time, note that the overflowing data from RAM is canceled by the setting from CRA0 to CRA7 and PGA. Table 10. How to write a display data in an LCD panel used in this LCD system configuration example Instruction data bit number Allotment 1st digit D0 D1 D2 ... D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 Dn_m Dn_ m+1 Dn_ m+2 ... Dn+15_ +m+13 Dn+15_ +m+14 Dn+15_ +m+15 CRA0 CRA1 CRA2 CRA3 CRA4 CRA5 CRA6 CRA7 PGA D1_3 ... D16_14 D16_15 D16_16 0 0 0 0 0 0 0 0 0 D1_1 D1_2 2nd digit D17_1 D17_2 D17_3 ... D32_14 D32_15 D32_16 0 0 0 0 1 0 0 0 0 3rd digit D33_1 D33_2 D33_3 ... D48_14 D48_15 D48_16 0 0 0 0 0 1 0 0 0 D49_3 ... D64_14 D64_15 D64_16 0 0 0 0 1 1 0 0 0 4th digit D49_1 D49_2 5th digit D65_1 D65_2 D65_3 ... D80_14 D80_15 D80_16 0 0 0 0 0 0 1 0 0 6th digit D81_1 D81_2 D81_3 ... D96_14 D96_15 D96_16 0 0 0 0 1 0 1 0 0 7th digit D97_1 D97_2 D97_3 ... D112_14 D112_15 D112_16 0 0 0 0 0 1 1 0 0 8th digit D113_1 D113_2 D113_3 ... D128_14 D128_15 D128_16 0 0 0 0 1 1 1 0 0 9th digit D129_1 D129_2 D129_3 ... D145_14 D145_15 D145_16 0 0 0 0 0 0 0 1 0 10th digit D145_1 D145_2 D145_3 ... D161_14 D161_15 D161_16 0 0 0 0 1 0 0 1 0 11th digit D161_1 D161_2 D161_3 ... D176_14 D176_15 D176_16 0 0 0 0 0 1 0 1 0 12th digit D177_1 D177_2 D177_3 ... D192_14 D192_15 D192_16 0 0 0 0 1 1 0 1 0 Icon D193_1 (AM) D193_2 D193_3 ... 0 0 0 0 0 0 0 0 0 1 1 0 Note : The display data of the icon area (D0 to D255) are assigned to D0=D193_1(AM), D16=D194_1(FM), D32=D195_1(CD), D48=D196_1(USB), D72=D197_9(AUTO), D88=D198_9(SCN), D104=D199_9(RPT), D120=D200_9(RDM), and other bits are set to “0”. Dn_m, Dn_m+1 to Dn+15_m+15 CRA0 to CRA7 PGA : A display data which are written to RAM. : Control data to set a column address of RAM. : Control data to set a page address of RAM. http://onsemi.com 23 LC450210PCH Application Note Software Control Example of the LCD Controller (1) Timing Chart from Power-on State to LCD Display ON First, the following figure shows the timing waveform from power-on state to initial setting and LCD display ON in this LCD system configuration example. +5.0 [V] VDD +5.0 [V] VBTI1 twres ≥ 1 [msec] RES Low CE Low CL Low DI Low High t9 ≥ 1 [msec] +16.0 [V] VBTI1 VLCD t4 ≥ 200 [msec] +12.0 [V] VLCD0 to VLCD4 Internal oscillator VLCD5 Low State of commons (COM1 to COM16) Display forced off (VLCD5 level) Normal display (Scanning) State of segments (S1 to S200) Display forced off (VLCD5 level) Normal display (5) (1) (2) (3) (4) (6) (7) < Operation sequence > (1) Power-on. Please input the 5V signal into CE, CL, DI, RES and OSCI by all means to prevent the destruction of these input pads after a logic power supply (VDD) was turned on. (2) The RES signal is set to High level. (3) The instruction of initial setting is transferred after passage of the “Wait time for inputting of serial data: t9 ≥ 1 [msec]”. Make sure to execute “Set of display method” instruction first. The “Set of display method” instruction is executed. (OC=0, DBC=1, CTC0=1, CTC1=1, DT0=1, DT1=1, DT2=1, DT3=1, DR=1, WVC=0, CDIR=0, SDIR=0, DBF0=0, DBF1=1, DBF2=1, FC0=0, FC1=1, FC2=0, FC3=0) (4) The “Set of display contrast” instruction is executed. (CT0=0, CT1=1, CT2=1, CT3=1, CT4=0, CT5=0) (5) The “Write display data to RAM (16x16 bits in a lump)” instructions are executed. (6) The “Set of line address” instruction is executed. (LNA0=0, LNA1=0, LNA2=0 ,LNA3=0) (7) The instruction of display ON setting is transferred after passage of the “Stabilization time of voltage booster, contrast adjuster and LCD drive bias voltage generator: t4 ≥ 200 [msec]” from operation sequence (3). The “Control of display ON / OFF” instruction is executed. (PNC=0, SC0=0, SC1=0, BU=0) http://onsemi.com 24 LC450210PCH Application Note (2) Timing Chart Power-Saving Mode is Set and Canceled The following figure shows the timing waveform from normal display state to power-saving mode setting and from power-saving mode state to normal display setting in this LCD system configuration example. Power-saving mode VDD +5.0 [V] VBTI1 +5.0 [V] RES High CE CL DI t16 ≥ 200 [msec] VLCD +16.0 [V] t4 ≥ 200 [msec] +16.0 [V] VBTI1 Discharge +12.0 [V] +12.0 [V] VLCD0 to VLCD4 VLCD5 Discharge Internal oscillator State of commons (COM1 to COM16) State of segments (S1 to S200) Stop Normal display (Scanning) Display forced off (VLCD5 level) Normal display (Scanning) Normal display Display forced off (VLCD5 level) Normal display (8) (9) (10) < Operation sequence > (8) The instruction of the power saving mode setting is transferred. The “Control of display ON / OFF” instruction is executed (PNC=0, SC0=1, SC1=1, BU=1). The output of these circuits becomes the discharge condition by the setting of the power saving mode (BU=1) because the voltage booster, the contrast adjuster and the LCD drive bias voltage generator are set to run state (DBC=1, CTC0=1, CTC1=1). (9) The instruction of the power saving mode cancellation setting is transferred. The “Control of display ON / OFF” instruction is executed. (PNC=0, SC0=1, SC1=1, BU=0) (10) The instruction of display ON setting is transferred after passage of the “Stabilization time of voltage booster, contrast adjuster and LCD drive bias voltage generator: t4 ≥ 200 [msec]” from operation sequence (9). The “Control of display ON / OFF” instruction is executed. (PNC=0, SC0=0, SC1=0, BU=0) http://onsemi.com 25 LC450210PCH Application Note (3) Timing Chart from Normal Display to Power-off State The following figure shows the timing waveform from normal display to power-off state. VDD +5.0 [V] VBTI1 +5.0 [V] RES High Low CE Low CL Low DI Low t6 ≥ 200 [msec] VLCD +16.0 [V] VBTI1 Discharge +12.0 [V] VLCD0 to VLCD4 VLCD5 Discharge Internal oscillator State of commons (COM1 to COM16) State of segments (S1 to S200) Stop Normal display (Scanning) Display forced off (VLCD5 level) Normal display Display forced off (VLCD5 level) (12) (11) Low (13) < Operation sequence > (11) The instruction of display OFF setting is transferred. The “Control of display ON / OFF” instruction is executed. (PNC=0, SC0=1, SC1=1, BU=0) In addition, the customer can be set by one instruction transfer at the same time because display OFF setting (SC0, SC1) and power saving mode setting (BU) are assigned to the same instruction. (12) The instruction of power-saving mode setting is transferred. The “Control of display ON / OFF” instruction is executed. (PNC=0, SC0=1, SC1=1, BU=1) (13) Power-off. Please input a signal of 0V into CE, CL, DI, RES and OSCI by all means to prevent the destruction of these input pads before a logic power supply (VDD) was turned off. http://onsemi.com 26 LC450210PCH Application Note Additional Explanation of Peripheral Circuits (1) About the resistors of the logic signal (OSCI, RES, CE, CL and DI) The resistors are the dumping resistance for waveform shaping. In addition, when waveform shaping is more necessary, connect a capacitor (For example, from 100 to 1000 [pF]) between logic input pad and VSS. LCD Controller LCD Driver LSI (LC450210PCH) Resistor OSCI RES CE CL DI Capacitor Figure 22. Peripheral circuits of the logic input signal Also make sure that the waveform of the input signal is not heavily distorted. The following figure shows the waveform example when waveform shaping by only a resistors. CE CE VIH=0.4VDD VIL=0.2VDD CL CL VIH=0.4VDD VIL=0.2VDD DI DI VIH=0.4VDD VIL=0.2VDD Figure 23. CCB serial data Signal (LCD controller output) Figure 24. CCB serial data Signal (LCD Driver LSI input) (2) About the resistors of the OSCI signal When internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. At this time, it may be connected to VSS through a pull-down resistor for the protection of the input circuit. The reason to insert a pull-down resistor are the incorrect operation by the noise, destruction with the excess voltage (the abnormal voltage of instants such as at the time of power-up), and consumption electric current reduction. If nothing inputs from the outside, the customer may be connected to the direct VSS without using the resistor, but the one that is not connected to direct VSS is safer. However, there is some demerit: parts increase, it may become weak in noise because impedance from VSS increases and there are not most of the consumption electric current reduction effects. LCD Driver LSI (LC450210PCH) OSCI Resistor Figure 25. Peripheral circuits of the OSCI signal http://onsemi.com 27 LC450210PCH Application Note (3) About the zener diode of the VBTI1 The voltage booster circuit, the contrast adjuster circuit and the LCD drive bias voltage generator circuit have the discharge circuit to discharge an electric charge of the external capacitor. When the voltage booster is set to the discharge condition, the VLCD level is same as VBTI1 level. When the contrast adjuster and the LCD drive bias voltage generator are set to the discharge condition, the levels from VLCD0 to VLCD4 are same as VLCD5 level. When the booster circuit was set to the discharge condition, the electric charge accumulated to the capacitors for booster circuit passes through to the VBTI1 pad. Therefore, when the impedance of the VBTI1 power supply line is high or there is not an electric discharge route (For example, the diode is inserted in series), the voltage of the VBTI1 pad may rise temporarily. In the case of the system configuration that VBTI1 and VBTI2 or VBTI1 and VDD are connected, if the absolute maximum ratings are exceeded, device functionality should not be assumed, damage may occur and reliability be affected. The measures of this case connect the zener diode to a power supply line of VBTI1, and please suppress the rise in voltage. LCD Driver LSI (LC450210PCH) VDD Power supply circuit CP1P Electric discharge route CP12N VBTI1 Zener diode VBTI2 REGE VSS Figure 26. Peripheral circuits of the VBTI1 http://onsemi.com 28 CP2P CP3P CP34N CP4P VLCD The electric charge accumulated to the capacitors for booster circuit LC450210PCH Application Note Application Circuit (1) In the Case of the LCD System Configuration to Input an External Clock (300 [kHz]) LCD Driver LSI (LC450210PCH) +5.0 [V] Cvd 4 +5.0 [V] VDD REGE TSIN1 to TSIN4 VSS VBTI1 VBTI2 Cbt Cbt 12.0 [V] (Typ.) The contrast adjuster is used VLCD0 Cvm VLCD1 Cvm VLCD2 The 1/5 bias is used Cvm VLCD3 Cvm VLCD4 Cvm CP1P C1 VLCD5 CP12N C2 CP2P The quintuple voltage booster is used CP3P C3 CP34N C4 16.0 [V] CP4P S193 to S200 S1 to S192 8 192 VLCD Cvl COM1 to COM16 16 AM OSCI RES CD USB AUTO SCN RPT RDM LCD Panel (16x16 dot font) x 12digits + 8 icons = 3,080 segments The internal oscillator circuit is not used. LCD Controller FM VLOGIC TSOUT1 to TSOUT3 TSO 3 (open) (open) (open) CE CL DI (CCB interface) Figure 27. LCD system configuration to input an external clock (300 [kHz]) The LC450210PCH is able to set the “Internal oscillator operating mode” or “External clock input operating mode”. The reason why a customer selects the LCD system configuration using the “External clock input operating mode” is because the characteristic of the internal oscillator clock frequency (fosc) is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore the customer may worry about the flicker of the liquid crystal display occurring by interference with other frequency. Furthermore, there may be a customer hoping to lower clock frequency more because of the low power consumption and EMI (Electro Magnetic Interference) measures, etc. First of all, the following table shows the pin explanation of the external clock input pin (OSCI) and the specifications of the allowable operating ranges. Pad name OSCI Pad function External clock input pad (When external clock operating mode was set) When internal oscillator operating mode is set (OC=“0”), make sure to connect OSCI to VSS. When external clock operating mode is set (OC=“1”), the OSCI is used to input the external clock. http://onsemi.com 29 LC450210PCH Application Note Allowable operating ranges at Ta= -40 to +105 [°C], VSS=0 [V] Parameter Symbol VDD Power Supply Voltage Input High Level Voltage VIH1 Input Low Level Voltage VIL1 Conditions Min. Typ. Max. Unit V VDD, REGE=VDD 4.5 6.3 VDD, REGE=VSS 2.7 3.6 V OSCI, VDD=4.5V to 5.5V (REGE=VDD) 0.5 VDD 5.5 V OSCI, VDD=2.7V to 3.6V (REGE=VSS) 0.8 VDD 3.6 V OSCI, VDD=4.5V to 5.5V (REGE=VDD) 0 0.2 VDD V OSCI, VDD=2.7V to 3.6V (REGE=VSS) 0 0.2 VDD V External Clock Input Frequency fck OSCI, External clock input operating mode 10 300 600 kHz External Clock Duty Ratio Dck OSCI, External clock input operating mode 30 50 70 % Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. The following explains a setting method example of serial data in this case. This system sets OC=“1” to use the “External clock 300 [kHz] input mode” OC 0 1 Fundamental clock operating mode Internal oscillator operating mode External clock operating mode The state of OSCI Make sure to connect OSCI to VSS Input the clock of 300 [kHz](Typ.) The registers from DBF0 to DBF2 can set the voltage booster clock frequency. When OC is set to “1”, the following table shows the voltage booster clock frequency. DBF0 DBF1 DBF2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Voltage Booster Clock Frequency (fcp) fCK/12 fCK/14 fCK/18 fCK/22 fCK/26 fCK/28 fCK/30 fCK/34 The voltage booster clock frequency when fCK is 300 [kHz] 25.00 [kHz] 21.43 [kHz] 16.66 [kHz] 13.63 [kHz] 11.54 [kHz] 10.71 [kHz] 10.00 [kHz] 8.82 [kHz] The explanation mentioned above is used only to explain internal operation and how to use the LSI, and the characteristic of the products is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. The registers from FC0 to FC3 can set the LCD drive frame frequency (fo). When OC is set to “1”, the following table shows the LCD drive frame frequency. FC0 FC1 FC2 FC3 0 0 0 1 0 0 LCD drive frame frequency (fo) 1/8duty 1/9duty 1/10duty 1/11duty 1/12duty 1/13duty 1/14duty 1/15duty 1/16duty 0 fCK/4352 <68.9[Hz]> fCK/4320 <69.4[Hz]> fCK/4320 <69.4[Hz]> fCK/4400 <68.2[Hz]> fCK/4320 <69.4[Hz]> fCK/4264 <70.4[Hz]> fCK/4256 <70.5[Hz]> fCK/4320 <69.4[Hz]> fCK/4352 <68.9[Hz]> 0 0 fCK/3712 <80.8[Hz]> fCK/3744 <80.1[Hz]> fCK/3760 <79.8[Hz]> fCK/3784 <79.3[Hz]> fCK/3744 <80.1[Hz]> fCK/3744 <80.1[Hz]> fCK/3808 <78.8[Hz]> fCK/3720 <80.7[Hz]> fCK/3712 <80.8[Hz]> 1 0 0 fCK/2944 fCK/2952 fCK/2960 fCK/2992 fCK/2976 fCK/2964 fCK/2968 fCK/3000 fCK/2944 <101.9[Hz]> <101.6[Hz]> <101.4[Hz]> <100.3[Hz]> <100.8[Hz]> <101.2[Hz]> <101.1[Hz]> <100.0[Hz]> <101.9[Hz]> 1 1 0 0 fCK/2368 fCK/2376 fCK/2400 fCK/2376 fCK/2400 fCK/2392 fCK/2408 fCK/2400 fCK/2368 <126.7[Hz]> <126.3[Hz]> <125.0[Hz]> <126.3[Hz]> <125.0[Hz]> <125.4[Hz]> <124.6[Hz]> <125.0[Hz]> <126.7[Hz]> 0 0 1 0 fCK/1984 fCK/1944 fCK/2000 fCK/1936 fCK/1968 fCK/1976 fCK/1960 fCK/1980 fCK/1984 <151.2[Hz]> <154.3[Hz]> <150.0[Hz]> <155.0[Hz]> <152.4[Hz]> <151.8[Hz]> <153.1[Hz]> <151.5[Hz]> <151.2[Hz]> 1 0 1 0 fCK/1696 fCK/1692 fCK/1720 fCK/1672 fCK/1728 fCK/1716 fCK/1708 fCK/1710 fCK/1696 <176.9[Hz]> <177.3[Hz]> <174.4[Hz]> <179.4[Hz]> <173.6[Hz]> <174.8[Hz]> <175.6[Hz]> <175.4[Hz]> <176.9[Hz]> 0 1 1 0 fCK/1472 fCK/1476 fCK/1480 fCK/1496 fCK/1488 fCK/1482 fCK/1456 fCK/1500 fCK/1472 <203.8[Hz]> <203.3[Hz]> <202.7[Hz]> <200.5[Hz]> <201.6[Hz]> <202.4[Hz]> <206.0[Hz]> <200.0[Hz]> <203.8[Hz]> 1 1 1 0 fCK/1312 fCK/1332 fCK/1320 fCK/1320 fCK/1320 fCK/1326 fCK/1316 fCK/1350 fCK/1312 <228.7[Hz]> <225.2[Hz]> <227.3[Hz]> <227.3[Hz]> <227.3[Hz]> <226.2[Hz]> <228.0[Hz]> <222.2[Hz]> <228.7[Hz]> http://onsemi.com 30 LC450210PCH Application Note LCD drive frame frequency (fo) 1/10duty 1/11duty 1/12duty 1/13duty 1/14duty 1/15duty 1/16duty FC0 FC1 FC2 FC3 0 0 0 1 fCK/1184 fCK/1188 fCK/1200 fCK/1188 fCK/1200 fCK/1196 fCK/1204 fCK/1200 fCK/1184 <253.4[Hz]> <252.5[Hz]> <250.0[Hz]> <252.5[Hz]> <250.0[Hz]> <250.8[Hz]> <249.2[Hz]> <250.0[Hz]> <253.4[Hz]> 1 0 0 1 fCK/1088 fCK/1080 fCK/1080 fCK/1100 fCK/1104 fCK/1118 fCK/1092 fCK/1080 fCK/1088 <275.7[Hz]> <277.8[Hz]> <277.8[Hz]> <272.7[Hz]> <271.7[Hz]> <268.3[Hz]> <274.7[Hz]> <277.8[Hz]> <275.7[Hz]> 0 1 0 1 fCK/1056 fCK/1044 fCK/1040 fCK/1056 fCK/1056 fCK/1040 fCK/1036 fCK/1050 fCK/1056 <284.1[Hz]> <287.4[Hz]> <288.5[Hz]> <284.1[Hz]> <284.1[Hz]> <288.5[Hz]> <289.6[Hz]> <285.7[Hz]> <284.1[Hz]> 1 1 0 1 fCK/992 fCK/1008 fCK/1000 fCK/990 fCK/984 fCK/988 fCK/980 fCK/990 fCK/992 <302.4[Hz]> <297.6[Hz]> <300.0[Hz]> <303.0[Hz]> <304.9[Hz]> <303.6[Hz]> <306.1[Hz]> <303.0[Hz]> <302.4[Hz]> 0 0 1 1 fCK/960 fCK/972 fCK/960 fCK/946 fCK/960 fCK/962 fCK/952 fCK/960 fCK/960 <312.5[Hz]> <308.6[Hz]> <312.5[Hz]> <317.1[Hz]> <312.5[Hz]> <311.9[Hz]> <315.1[Hz]> <312.5[Hz]> <312.5[Hz]> 1 0 1 1 fCK/928 fCK/936 fCK/920 fCK/924 fCK/936 fCK/936 fCK/924 fCK/930 fCK/928 <323.3[Hz]> <320.5[Hz]> <326.1[Hz]> <324.7[Hz]> <320.5[Hz]> <320.5[Hz]> <324.7[Hz]> <322.6[Hz]> <323.3[Hz]> 0 1 1 1 fCK/896 fCK/900 fCK/900 fCK/902 fCK/888 fCK/884 fCK/896 fCK/900 fCK/896 <334.8[Hz]> <333.3[Hz]> <333.3[Hz]> <332.6[Hz]> <337.8[Hz]> <339.4[Hz]> <334.8[Hz]> <333.3[Hz]> <334.8[Hz]> 1 1 1 1 fCK/864 fCK/864 fCK/860 fCK/858 fCK/864 fCK/858 fCK/868 fCK/870 fCK/864 <347.2[Hz]> <347.2[Hz]> <348.8[Hz]> <349.7[Hz]> <347.2[Hz]> <349.7[Hz]> <345.6[Hz]> <344.8[Hz]> <347.2[Hz]> 1/8duty 1/9duty The value of “< >” is an LCD drive frame frequency when fCK is 300 [kHz]. The explanation mentioned above is used only to explain internal operation and how to use the LSI, and the characteristic of the products is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. The setting method about the registers except the above is the same as “Explanation of the Internal Circuit Control”, “Explanation of the LCD Drive Control” and “Explanation of How to Write a Display Data RAM”. http://onsemi.com 31 LC450210PCH Application Note (2) In the case of an LCD system to compose of only the 3V power supply LCD Driver LSI (LC450210PCH) +3.0 [V] Cvd 4 +3.0 [V] (+2.7 to +3.3 [V]) VDD REGE TSIN1 to TSIN4 VSS 10.05 [V] (Typ.) The contrast adjuster is used VLCD0 Cvm VLCD1 Cvm VLCD2 VBTI1 VLCD3 VBTI2 Cbt The 1/5 bias is used Cvm Cvm VLCD4 Cvm CP1P C1 VLCD5 CP12N C2 CP2P The quintuple voltage booster is used CP3P C3 CP34N C4 15.0 [V] CP4P S193 to S200 S1 to S192 8 192 VLCD Cvl COM1 to COM16 The internal oscillator circuit is used. +3.0 [V] AM FM CD USB AUTO SCN RPT RDM OSCI LCD Panel (16x16 dot font) x 12digits + 8 icons = 3,080 segments RES LCD Controller 16 VLOGIC TSOUT1 to TSOUT3 TSO 3 (open) (open) (open) CE CL DI (CCB interface) Figure 28. LCD system to compose of only the 3V power supply This LCD system configuration example sets DBC=“1”, CTC0=“1” and CTC1=“1” to use the all circuits (voltage booster circuit, contrast adjuster circuit and LCD drive bias voltage generator circuit). The control data from CT0 to CT5 can set the LCD drive bias voltage (VLCD0) using the contrast adjuster circuit. However, satisfy a condition of VLCD0 ≤ VLCD - 2.4[V]. This LCD system configuration example sets CT0=“1”, CT1=“1”, CT2=“0”, CT3=“1”, CT4=“1” and CT5=“0” to use the LCD drive bias voltage (VLCD0) as 10.05 [V]. When VBTI1=VBTI2=3.0 [V], REGE=VSS, quintuple voltage booster and contrast adjuster are used, LCD power supply voltage (VLCD) becomes 15.0 [V] that quintupled the VBTI2 input of 3.0 [V] (Typical allowable operating range). In addition, when the VBTI2 input of 3.3 [V] (The voltage that added a fluctuation of 0.3 [V] to the 3.0 [V] voltage), the VLCD is 16.5 [V]. Moreover, when the VBTI2 input of 2.7 [V] (Minimum allowable operating range), the VLCD is 13.5 [V]. The customer can select from step 20 (11.10 [V]) to step 63 (4.65 [V]) at the time of this setting state. When these are set from step 0 (14.10 [V]) to step 19 (11.25 [V]), the VLCD0 voltage is not guaranteed. VLCD0 [V] ≥ 2.4V 11.10 VLCD=13.5 [V] 4.65 0 20 63 Value from CT0 to CT5 Figure 29. Adjustment range of the LCD drive bias voltage (VLCD0) http://onsemi.com 32 LC450210PCH Application Note Table 11. Setting of settable contrast adjustment Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 VLCD0 voltage not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed not guaranteed 11.10 V 10.95 V 10.80 V 10.65 V 10.50 V 10.35 V 10.20 V 10.05 V 9.90 V 9.75 V 9.60 V 9.45 V Step 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 CT0 CT1 CT2 CT3 CT4 CT5 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 VLCD0 voltage 9.30 V 9.15 V 9.00 V 8.85 V 8.70 V 8.55 V 8.40 V 8.25 V 8.10 V 7.95 V 7.80 V 7.65 V 7.50 V 7.35 V 7.20 V 7.05 V 6.90 V 6.75 V 6.60 V 6.45 V 6.30 V 6.15 V 6.00 V 5.85 V 5.70 V 5.55 V 5.40 V 5.25 V 5.10 V 4.95 V 4.80 V 4.65 V The explanation mentioned above is used only to explain internal operation and how to use the LSI, and the characteristic of the products is uneven by a production variation and the terms of use of the LSI (Power supply voltage, temperature, etc.). Therefore, the customer should always evaluate and test devices mounted in the customer’s products or equipment. The setting method about the registers except the above is the same as “Explanation of the Clock Control”, “Explanation of the Internal Circuit Control”, “Explanation of the LCD Drive Control” and “Explanation of How to Write a Display Data RAM”. http://onsemi.com 33 LC450210PCH Application Note Caution of the ITO Wiring Design Caution of the ITO wiring design is provided as follows for the stable operation of this LSI. In reference to these, it is necessary to design an application or the set, in consideration of an LCD specification and condition. Design the ITO line of a power supply and the voltage booster signal as short and wide as possible, because it is necessary to minimize the parasitic resistance of the ITO line. Particularly, in the case of the COG (The LSI chip is mounted on glass substrate), minimize the resistance of ITO lines from the pad of the LSI to FPC/FFC. In addition, connect the PAD between the adjacent same signals (However, the DUMMY pad is excluded) at the outside of the LSI. The following figure shows the design example of the ITO wiring. CL OSCI TSIN1 TSIN2 TSIN3 TSIN4 VSS VSS VSS VSS REGE VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VBTI1 VBTI1 VBTI1 VBTI1 VBTI1 VBTI2 VBTI2 VBTI2 VBTI2 VBTI2 CP1P CP1P (1) Good wiring example IC chip Glass substrate This distance is as short and wide as possible. ITO wiring CL OSCI TSIN1 TSIN2 TSIN3 TSIN4 VSS VSS VSS VSS REGE VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VBTI1 VBTI1 VBTI1 VBTI1 VBTI1 VBTI2 VBTI2 VBTI2 VBTI2 VBTI2 CP1P CP1P FPC/FFC IC chip Glass substrate FPC/FFC When the system of the 3V power supply, it is alright if connect VBTI1 and VBTI2 on an FPC/FFC. When terms of use never change, it is alright if connect a setting signal on an FPC/FFC. CL OSCI TSIN1 TSIN2 TSIN3 TSIN4 VSS VSS VSS VSS REGE VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VBTI1 VBTI1 VBTI1 VBTI1 VBTI1 VBTI2 VBTI2 VBTI2 VBTI2 VBTI2 CP1P CP1P (2) Bad wiring example The PAD between the adjacent same signals must be connected outside an LSI. IC chip Glass substrate CL OSCI TSIN1 TSIN2 TSIN3 TSIN4 VSS VSS VSS VSS REGE VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VBTI1 VBTI1 VBTI1 VBTI1 VBTI1 VBTI2 VBTI2 VBTI2 VBTI2 VBTI2 CP1P CP1P FPC/FFC IC chip The ITO lines from the pad of the LSI to FPC/FFC wire it widely as short as possible. Glass substrate CL OSCI TSIN1 TSIN2 TSIN3 TSIN4 VSS VSS VSS VSS REGE VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VBTI1 VBTI1 VBTI1 VBTI1 VBTI1 VBTI2 VBTI2 VBTI2 VBTI2 VBTI2 CP1P CP1P FPC/FFC IC chip Don't connect to constitute a circuit on glass substrate. Glass substrate PCB Pin Pin 2.0 [mm] http://onsemi.com 34 LC450210PCH Application Note ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. http://onsemi.com 35