LC75838W D

LC75838W
CMOS LSI
1/8 to 1/10 Duty General-Purpose
LCD Driver
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Overview
The LC75838W is 1/8 to 1/10 duty general-purpose LCD display driver used
for character and graphics display. This product operates under the control of a
microcontroller and can directly drive an LCD with up to 380 segments. It can
also control up to 3 general-purpose output ports.
SPQFP64 10x10 / SQFP64
Features
 1/8duty–1/4bias, 1/9duty–1/4bias, and 1/10duty–1/4bias drive schemes can be controlled from serial data.
1/8duty–1/4bias: up to 320 segments
1/9duty–1/4bias: up to 351 segments
1/10duty–1/4bias: up to 380 segments
 Serial data input supports CCB format communication with the system controller.
 Serial data control of the power-saving mode based backup function and all the segments forced off function.
 Direct display of display data without the use of a decoder provides high generality.
 Built-in display contrast adjustment circuit.
 Up to 3 general-purpose output ports are included.
 Independent LCD driver block power supply VLCD.
 The INH pin is provided. This pin turns off the display and forces the general-purpose output ports to the low level.
 RC oscillator circuit

CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.

CCB is a registered trademark of Semiconductor Components Industries, LLC.
ORDERING INFORMATION
See detailed ordering and shipping information on page 36 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
January 2015 - Rev. 0
1
Publication Order Number :
LC75838W/D
LC75838W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
Unit
VDD max
VDD
-0.3 to +7.0
VLCD max
VLCD
-0.3 to +12.0
V
VIN1
CE, CL, DI, INH
VIN2
OSC
VIN3
VLCD1, VLCD2, VLCD3, VLCD4
VOUT1
OSC, P1 to P3
VOUT2
VLCD0, S1 to S40, COM1 to COM10
IOUT1
S1 to S40
IOUT2
COM1 to COM10
3
IOUT3
P1 to P3
5
Allowable power dissipation
Pd max
Ta=85C
Operating temperature
Topr
-40 to +85
C
Storage temperature
Tstg
-55 to +125
C
Input voltage
Output voltage
Output current
-0.3 to +7.0
V
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
-0.3 to VDD+0.3
V
-0.3 to VLCD+0.3
A
300
mA
200
mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
unit
min
Supply voltage
typ
max
VDD
VDD
2.7
6.0
VLCD
VLCD, When the display contrast adjustment
circuit is used
7.0
11.0
VLCD
VLCD, When the display contrast adjustment
circuit is not used
4.5
11.0
Output voltage
VLCD0
VLCD0
VLCD4
+4.5
VLCD
Input voltage
VLCD1
VLCD1
3/4(VLCD0
-VLCD4)
VLCD2
VLCD2
2/4(VLCD0
-VLCD4)
VLCD3
VLCD3
1/4(VLCD0
-VLCD4)
V
V
VLCD0
VLCD0
V
VLCD0
VLCD4
VLCD4
0
1.5
Input high level voltage
VIH
CE, CL, DI, INH
0.8VDD
6.0
V
Input low level voltage
VIL
CE, CL, DI, INH
0
0.2VDD
V
Recommended external resistance
ROSC
OSC
Recommended external
COSC
OSC
Guaranteed oscillation range
fOSC
OSC
Data setup time
tds
CL, DI
[Figure 2]
160
ns
Data hold time
tdh
CL, DI
[Figure 2]
160
ns
CE wait time
tcp
CE, CL
[Figure 2]
160
ns
CE setup time
tcs
CE, CL
[Figure 2]
160
ns
CE hold time
tch
CE, CL
[Figure 2]
160
ns
High level clock pulse width
tH
CL
[Figure 2]
160
ns
Low level clock pulse width
tL
CL
[Figure 2]
160
ns
INH switching time
tc
INH, CE
[Figure 3],[ Figure 4],[ Figure 5]
10
s
capacitance
25
43
k
680
pF
50
100
kHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC75838W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
Parameter
Symbol
Pins
Conditions
unit
min
typ
Hysteresis
VH
CE, CL, DI, INH
Input high level current
IIH
CE, CL, DI, INH
VI=6.0V
Input low level current
IIL
CE, CL, DI, INH
VI=0V
Output high level voltage
VOH1
S1 to S40
IO=-20A
VLCD0-0.6
VOH2
COM1 to COM10
IO=-100A
VLCD0-0.6
VOH3
P1 to P3
IO=-1mA
Output low level voltage
Output middle level
max
0.1VDD
V
5.0
A
A
-5.0
V
VDD-1.0
VOL1
S1 to S40
IO=20A
VLCD4+0.6
VOL2
COM1 to COM10
IO=100A
VLCD4+0.6
VOL3
P1 to P3
IO=1mA
VMID1
S1 to S40
IO=20A
2/4(VLCD0
-VLCD4)
-0.6
+0.6
VMID2
COM1 to COM10
IO=100A
3/4(VLCD0
-VLCD4)
3/4(VLCD0
-VLCD4)
-0.6
+0.6
1/4(VLCD0
-VLCD4)
1/4(VLCD0
-VLCD4)
V
1.0
voltage
*1
VMID3
COM1 to COM10
IO=100A
Oscillator frequency
fosc
OSC
Rosc=43k, Cosc=680pF
Current drain
IDD1
VDD
Power saving mode
IDD2
VDD
VDD=6.0V, outputs open,
fosc=50kHz
ILCD1
VLCD
Power saving mode
ILCD2
VLCD
VLCD=11.0V, outputs open,
fosc=50kHz
2/4(VLCD0
-VLCD4)
-0.6
40
V
+0.6
50
60
kHz
5
200
400
5
When the display contrast adjustment
500
1000
250
500
A
circuit is used.
ILCD3
VLCD
VLCD=11.0 V, outputs open,
fosc=50kHz
When the display contrast adjustment
circuit is not used.
Note: *1 Excluding the bias voltage generation divider resistor built into VLCD0, VLCD1, VLCD2, VLCD3, and
VLCD4. (See Figure 1.)
VLCD
CONTRAST
ADJUSTER
VLCD0
VLCD1
To the common and segment drivers
VLCD2
VLCD3
VLCD4
Excluding these resistors
Figure 1
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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LC75838W

1. When CL is stopped at the low level
VIH
CE

VIL

CL
tL

tH
VIH
50%
VIL
tch
 
VIH
DI
tcs
 
tcp
VIL
tds
tdh

2. When CL is stopped at the high level
VIH
VIL

CE
tH

tL
VIH
50%
VIL

CL
tcs
 
VIH
DI
VIL
tds
tch
 
tcp
tdh
Figure 2
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LC75838W
Package Dimensions
unit : mm
SPQFP64 10x10 / SQFP64
CASE 131AK
ISSUE A
0.5 0.2
12.0 0.2
64
10.0 0.1
12.0 0.2
10.0 0.1
1 2
0.5
0.15 0.05
0.18
0.10
1.7 MAX
(1.5)
(1.25)
0.1±0.1
0 to10°
0.10
GENERIC MARKING DIAGRAM*
SOLDERING FOOTPRINT*
11.40
XXXXXXXX
YMDDD
XXXXXXXX
YDD
(Unit: mm)
11.40
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.28
1.00
may or may not be present.
0.50
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
LC75838W
48
P1
S33
S34
S35
S36
S37
S38
S39/COM10
S40/COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
Pin Assignment
33
49
S32
32
P2
S31
P3
S30
S29
VDD
VLCD
VLCD0
S28
S27
VLCD1
S26
LC75838W
VLCD2
S25
VLCD3
VLCD4
S24
S23
VSS
OSC
S22
INH
CE
S20
S21
S19
CL
DI
64
S18
S17
17
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S16
16
1
Top view
GENERAL
PORT
OSC
COMMON
DRIVER
S1
S38
S39/COM10
S40/COM9
COM8
COM1
P3
P1
Block Diagram
SEGMENT DRIVER & LATCH
CLOCK
GENERATOR
CONTROL
REGISTER
VLCD
CONTRAST
ADJUSTER
SHIFT REGISTER
VLCD0
VLCD1
CCB
INTERFACE
VLCD2
VLCD3
VLCD4
VDD
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6
CE
CL
INH
DI
VSS
LC75838W
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
S1 to S38
1 to 38
S39/COM10
39
The S39/COM10 and S40/COM9 pins can be used as common driver outputs
S40/COM9
40
under the control data DT1, DT2.
COM1 to
COM8
P1 to P3
48 to 41
49 to 51
Segment driver outputs.
Common driver outputs.
General-purpose output ports.
-
O
OPEN
-
O
OPEN
-
O
OPEN
-
I/O
VDD
H
I
Oscillator connection.
OSC
60
An oscillator circuit is formed by connecting an external resistor and capacitor at
this pin.
CE
62
Serial data transfer inputs.
These pins are connected to the microcontroller.
CL
63
I
CE: Chip enable
GND
CL: Synchronization clock
DI
64
DI: Transfer data
-
I
L
I
GND
-
O
OPEN
-
I
OPEN
-
I
OPEN
-
I
OPEN
-
I
GND
-
-
-
-
-
-
-
-
-
Input that turns the display off and forces the general-purpose output ports low.
• When INH is low (VSS)
• Display off
S1 to S38 = “L” (VLCD4).
S39/COM10, S40/COM9 = “L” (VLCD4)
INH
61
COM1 to COM8 = “L” (VLCD4).
• General-purpose output ports P1 to P3 = low (VSS)
• When INH is high (VDD)
• Display on
• The states of the general-purpose output ports can be set by the PC1 to
PC3 control data.
However, serial data can be transferred when the INH pin is low.
LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be
changed by the display contrast adjustment circuit.
VLCD0
54
However, (VLCD0 - VLCD4) must be greater than or equal to 4.5V. Also, external
power must not be applied to this pin since the pin circuit includes the display
contrast adjustment circuit.
VLCD1
55
VLCD2
56
VLCD3
57
LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply
the 3/4 (VLCD0 - VLCD4) voltage level externally.
LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply
the 2/4 (VLCD0 - VLCD4) voltage level externally.
LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply
the 1/4 (VLCD0 - VLCD4) voltage level externally.
LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display
VLCD4
58
VDD
52
contrast can be implemented by connecting an external variable resistor to this pin.
However, (VLCD0 – VLCD4) must be greater than or equal to 4.5V, and VLCD4
must be in the range 0V to 1.5V, inclusive.
Logic block power supply connection. Provide a voltage of between 2.7 and 6.0V.
LCD driver block power supply connection. Provide a voltage of between 7.0 and
VLCD
53
11.0V when the display contrast adjustment circuit is used and provide a voltage of
between 4.5 and 11.0V when the circuit is not used.
VSS
59
Power supply connection. Connect to ground.
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7
DI
1
0
1
1
0
0
1
0
1
1
0
0
1
0
D81
D1
D82
D2
D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 0
Display data
80 bits
D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 0
0
0
0
0
0
Fixed data
5 bits
0
0
0
0
0
0
DD
3 bits
0
1
0
 
0
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3

CL
CE
1. 1/8 duty
(1) When CL is stopped at the low level
• When the display data is transferred.
Serial Data Transfer Format
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8
1
1
0
0
1
0
D161 D162
0
Fixed data
5 bits
0
0
0
DD
3 bits
1
0
 
Display data
80 bits
0

CCB address
8 bits
D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0
 
1

B0 B1 B2 B3 A0 A1 A2 A3
0
CCB address
8 bits
DD
3 bits
 
Fixed data
5 bits

Display data
80 bits
 
1

B0 B1 B2 B3 A0 A1 A2 A3
LC75838W

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9
0
1
1
0
0
1
0
0
1
1
0
0
1
0
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
1
Contorol data
13 bits
0
1
DD
3 bits
0
Display data
80 bits
0
D297 D298 D299 D300 D301 D302 D303 D304 D305 D306 D307 D308 D309 D310 D311 D312 D313 D314 D315 D316 D317 D318 D319 D320 0
PC1 PC2 PC3 CT0 CT1 CT2 CT3 CTC SC BU DT1 DT2
• When the control data is transferred.
CCB address
8 bits
D241 D242
Note: B0 to B3, A0 to A3 ...... CCB address
DD................................. Direction data
DI
CL
CE
1
 
B0 B1 B2 B3 A0 A1 A2 A3
0
0
Fixed data
5 bits
0
0
0
DD
3 bits
1
1
LC75838W
1
0
0
1
1
0
0
D81 D82
D1 D2
0
D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 0
Display data
80 bits
D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80
0
0
0
0
0
Fixed data
5 bits
0
0
0
0
0
0
DD
3 bits
0
1
0

0
CCB address
8 bits
0
1
A3
0
1
1
B0 B1 B2 B3 A0 A1 A2

DI
CL
CE
(2) When CL is stopped at the high level
• When the display data is transferred.
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CCB address
8 bits
0
D161 D162
Display data
80 bits
Fixed data
5 bits
0
0
DD
3 bits
0

A3

1

1

B0 B1 B2 B3 A0 A1 A2
CCB address
8 bits
0
0
A3
0
1
1
Display data
80 bits
D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0
0
0
Fixed data
5 bits
0
DD
3 bits
1

1

0

1

B0 B1 B2 B3 A0 A1 A2
LC75838W

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11
0
0
0
0
CCB address
8 bits
0
1
A3
1
1
0
B0 B1 B2 B3 A0 A1 A2
1
Control data
13 bits
1
DD
3 bits
0
Display data
80 bits
0
D297 D298 D299 D300 D301 D302 D303 D304 D305 D306 D307 D308 D309 D310 D311 D312 D313 D314 D315 D316 D317 D318 D319 D320 0
PC1 PC2 PC3 CT0 CT1 CT2 CT3 CTC SC BU DT1 DT2 0
• When the control data is transferred.
CCB address
8 bits
D241 D242
Note: B0 to B3, A0 to A3 ...... CCB address
DD ................................ Direction data
• CCB address: ...................... 4DH
• D1 to D320: …………........ Display data
• PC1 to PC3: ........................ General-purpose output port state setting data
• CT0 to CT3, CTC: ……….. Display contrast setting data
• SC: ...................................... Segment on/off control data
• BU: ..................................... Normal mode/power saving mode control data
• DT1, DT2: .......................... Display technique setting data
DI
CL
CE
1
0
1
A3
0
1
1

B0 B1 B2 B3 A0 A1 A2
0
0
Fixed data
5 bits
0
0
0
DD
3 bits
1
1
LC75838W
DI
1
0
1
1
0
0
1
0
0
1
1
0
0
1
0
D91
D1
D92
D2
0
0
0
0
Fixed data
3 bits
D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 0
Display data
90 bits
D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 0
0
0
0
DD
3 bits
0
1
0
 
1
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3

CL
CE
2. 1/9 duty
(1) When CL is stopped at the low level
• When the display data is transferred.
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CCB address
8 bits
0
1
0
D181 D182
0
0
 
DD
3 bits

Fixed data
3 bits
 
Display data
90 bits

B0 B1 B2 B3 A0 A1 A2 A3
1
0
CCB address
8 bits
Display data
90 bits
0
0
Fixed data
3 bits
D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 0
DD
3 bits
1
 
1

0
 
1

B0 B1 B2 B3 A0 A1 A2 A3
LC75838W

1
 
0
1
1
0
0
1
0
D271 D272
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13
1
0
1
1
0
0
1
0
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
81 bits
Contorol data
13 bits
1
DD
3 bits
0
0
D335 D336 D337 D338 D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 0
PC1 PC2 PC3 CT0 CT1 CT2 CT3 CTC SC BU DT1 DT2 0
Note: B0 to B3, A0 to A3 ...... CCB address
DD................................. Direction data
DI
CL
CE
• When the control data is transferred.
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
0
0
0
0
0
Fixed data
12 bits
0
0
0
0
0
0
0
DD
3 bits
1
1
LC75838W
1
0
0
1
1
0
0
D91 D92
D1 D2
0
0
0
0
Fixed data
3 bits
D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 0
Display data
90 bits
D65 D66 D67 D68 D69 D70 D71 D72 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 0
0
0
0
DD
3 bits
0
1
0

0
CCB address
8 bits
0
1
A3
0
1
1
B0 B1 B2 B3 A0 A1 A2

DI
CL
CE
(2) When CL is stopped at the high level
• When the display data is transferred.
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CCB address
8 bits
0
D181 D182
Display data
90 bits
Fixed data
3 bits
0
DD
3 bits
0

A3

1

1

B0 B1 B2 B3 A0 A1 A2
CCB address
8 bits
0
0
A3
0
1
1
Display data
90 bits
0
0
Fixed data
3 bits
D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 0
DD
3 bits
1

1

0

1

B0 B1 B2 B3 A0 A1 A2
LC75838W

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15
0
CCB address
8 bits
D271 D272
1
0
0
CCB address
8 bits
0
1
A3
0
1
1
B0 B1 B2 B3 A0 A1 A2
Contorol data
13 bits
PC1 PC2 PC3 CT0 CT1 CT2 CT3 CTC SC BU DT1 DT2 0
Display data
81 bits
1
DD
3 bits
0
0
D335 D336 D337 D338 D339 D340 D341 D342 D343 D344 D345 D346 D347 D348 D349 D350 D351 0
Note: B0 to B3, A0 to A3 ...... CCB address
DD ................................ Direction data
• CCB address: ...................... 4DH
• D1 to D351: …………........ Display data
• PC1 to PC3: ........................ General-purpose output port state setting data
• CT0 to CT3, CTC: ……….. Display contrast setting data
• SC: ...................................... Segment on/off control data
• BU: ..................................... Normal mode/power saving mode control data
• DT1, DT2: .......................... Display technique setting data
DI
0
• When the control data is transferred.
CE
CL
1
0
1
A3
0
1
1

B0 B1 B2 B3 A0 A1 A2
0
0
0
0
0
Fixed data
12 bits
0
0
0
0
0
0
0
DD
3 bits
1
1
LC75838W
DI
1
0
1
1
0
0
1
0
1
1
0
0
1
0
D2
D101 D102
D1
Fixed data
1 bits
D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 0
Display data
100 bits
D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 0
0
0
0
DD
3 bits
0
1
0
 
0
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3

CL
CE
3. 1/10 duty
(1) When CL is stopped at the low level
• When the display data is transferred.
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16
0
1
1
0
0
1
0
D201 D202
0
0
DD
3 bits
 
Fixed data
1 bits

Display data
100 bits
1
 
CCB address
8 bits
D273 D274 D275 D276 D277 D278 D279 D280 D281 D282 D283 D284 D285 D286 D287 D288 D289 D290 D291 D292 D293 D294 D295 D296 D297 D298 D299 D300 0

B0 B1 B2 B3 A0 A1 A2 A3
1
CCB address
8 bits
DD
3 bits
 
Fixed data
1 bits

Display data
100 bits
 
1

B0 B1 B2 B3 A0 A1 A2 A3
LC75838W

1
 
0
1
1
0
0
1
0
D301 D302
17
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1
0
1
1
0
0
1
0
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
Display data
80 bits
D373 D374 D375 D376 D377 D378 D379 D380 0
Contorol data
13 bits
PC1 PC2 PC3 CT0 CT1 CT2 CT3 CTC SC BU DT1 DT2 0
Note: B0 to B3, A0 to A3 ...... CCB address
DD................................. Direction data
DI
CL
CE
• When the control data is transferred.
CCB address
8 bits
B0 B1 B2 B3 A0 A1 A2 A3
0
1
0
0
DD
3 bits
0
0
0
0
0
0
0
0
0
Fixed data
21 bits
0
0
0
0
0
0
0
0
0
0
0
DD
3 bits
1
1
LC75838W
1
0
0
0
1
1
0
0
D101 D102
D1 D2
Fixed data
1 bits
D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 D193 D194 D195 D196 D197 D198 D199 D200 0
Display data
100 bits
D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 0
0
0
0
DD
3 bits
0
1
0

1
CCB address
8 bits
0
1
A3
0
1
1
B0 B1 B2 B3 A0 A1 A2

DI
CL
CE
(2) When CL is stopped at the high level
• When the display data is transferred.
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18
CCB address
8 bits
D201 D202
Display data
100 bits
Fixed data
1 bits
0
DD
3 bits
0

0

A3

1

B0 B1 B2 B3 A0 A1 A2
CCB address
8 bits
0
0
A3
0
1
1
Display data
100 bits
Fixed data
1 bits
D273 D274 D275 D276 D277 D278 D279 D280 D281 D282 D283 D284 D285 D286 D287 D288 D289 D290 D291 D292 D293 D294 D295 D296 D297 D298 D299 D300 0
DD
3 bits
1

1

0

1

B0 B1 B2 B3 A0 A1 A2
LC75838W

19
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0
0
0
0
CCB address
8 bits
0
1
A3
1
1
0
B0 B1 B2 B3 A0 A1 A2
1
Display data
80 bits
D373 D374 D375 D376 D377 D378 D379 D380 0
Contorol data
13 bits
PC1 PC2 PC3 CT0 CT1 CT2 CT3 CTC SC BU DT1 DT2 0
• When the control data is transferred.
CCB address
8 bits
D301 D302
Note: B0 to B3, A0 to A3 ...... CCB address
DD ................................ Direction data
• CCB address: ...................... 4DH
• D1 to D380: …………........ Display data
• PC1 to PC3: ........................ General-purpose output port state setting data
• CT0 to CT3, CTC: ……….. Display contrast setting data
• SC: ...................................... Segment on/off control data
• BU: ..................................... Normal mode/power saving mode control data
• DT1, DT2: .......................... Display technique setting data
DI
CL
CE
1
0
1
A3
0
1
1

B0 B1 B2 B3 A0 A1 A2
1
0
DD
3 bits
0
0
0
0
0
0
0
0
0
0
0
Fixed data
21 bits
0
0
0
0
0
0
0
0
0
0
0
DD
3 bits
1
1
LC75838W
LC75838W
Control Data Functions
1. PC1 to PC3: General-purpose output port state setting data
These control data bits set the states of the general-purpose output ports P1 to P3.
Output pin
P1
P2
P3
General-purpose output port state setting data
PC1
PC2
PC3
For example, if PC1 and PC2 are set to 1, and PC3 is set to 0, then the output pins P1 and P2 will output high levels
(VDD) and the output pin P3 will output low level (VSS).
2. CT0 to CT3, CTC: Display contrast setting data
These control data bits set the display contrast.
CT0 to CT3: Display contrast setting (11 steps)
CT0
CT1
CT2
CT3
0
0
0
0
0.94VLCD=VLCD-(0.03VLCD2)
LCD drive 4/4 bias voltage supply VLCD0 level
1
0
0
0
0.91VLCD=VLCD-(0.03VLCD3)
0
1
0
0
0.88VLCD=VLCD-(0.03VLCD4)
1
1
0
0
0.85VLCD=VLCD-(0.03VLCD5)
0
0
1
0
0.82VLCD=VLCD-(0.03VLCD6)
1
0
1
0
0.79VLCD=VLCD-(0.03VLCD7)
0
1
1
0
0.76VLCD=VLCD-(0.03VLCD8)
1
1
1
0
0.73VLCD=VLCD-(0.03VLCD9)
0
0
0
1
0.70VLCD=VLCD-(0.03VLCD10)
1
0
0
1
0.67VLCD=VLCD-(0.03VLCD11)
0
1
0
1
0.64VLCD=VLCD-(0.03VLCD12)
CTC: Display contrast adjustment circuit state setting
CTC
Display contrast adjustment circuit state
0
The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level.
1
The display contrast adjustment circuit operates and the display contrast is adjusted.
Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it
is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin
and modifying the VLCD4 pin voltage. However, the following conditions must be met: (VLCD0 - VLCD4)  4.5V,
and 1.5V  VLCD4  0V.
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20
LC75838W
3. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting
segment off waveforms from the segment output pins.
4. BU: Normal mode/power saving mode control data
This control data bit controls the normal mode and power saving mode.
BU
Mode
0
Normal mode
Power-saving mode.
The common and segment pins go to the VLCD4 level and the oscillator on the OSC pin is stopped. Note that the
states of the general-purpose output ports P1 to P3 are set by PC1 to PC3 in the control data during power saving
1
mode as well as normal mode.
5. DT1, DT2: Display technique setting data
This control data bits set the display technique.
Output pins
DT1
DT2
Display technique
S40/COM9
S39/COM10
0
0
1/8 duty 1/4 bias drive
S40
S39
1
0
1/9 duty 1/4 bias drive
COM9
S39
0
1
1/10 duty 1/4 bias drive
COM9
COM10
Notes: Sn (n = 39, 40): Segment outputs
COMn (n = 9 or 10): Common outputs
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21
LC75838W
Display Data and Output Pin Correspondence
 1/8 duty
Output Pin
COM1
COM2
COM3
COM4
COM5
COM6
COM7
S1
D1
D2
D3
D4
D5
D6
D7
COM8
D8
S2
D9
D10
D11
D12
D13
D14
D15
D16
S3
D17
D18
D19
D20
D21
D22
D23
D24
S4
D25
D26
D27
D28
D29
D30
D31
D32
S5
D33
D34
D35
D36
D37
D38
D39
D40
S6
D41
D42
D43
D44
D45
D46
D47
D48
S7
D49
D50
D51
D52
D53
D54
D55
D56
S8
D57
D58
D59
D60
D61
D62
D63
D64
S9
D65
D66
D67
D68
D69
D70
D71
D72
S10
D73
D74
D75
D76
D77
D78
D79
D80
S11
D81
D82
D83
D84
D85
D86
D87
D88
S12
D89
D90
D91
D92
D93
D94
D95
D96
S13
D97
D98
D99
D100
D101
D102
D103
D104
S14
D105
D106
D107
D108
D109
D110
D111
D112
S15
D113
D114
D115
D116
D117
D118
D119
D120
S16
D121
D122
D123
D124
D125
D126
D127
D128
S17
D129
D130
D131
D132
D133
D134
D135
D136
S18
D137
D138
D139
D140
D141
D142
D143
D144
S19
D145
D146
D147
D148
D149
D150
D151
D152
S20
D153
D154
D155
D156
D157
D158
D159
D160
S21
D161
D162
D163
D164
D165
D166
D167
D168
S22
D169
D170
D171
D172
D173
D174
D175
D176
S23
D177
D178
D179
D180
D181
D182
D183
D184
S24
D185
D186
D187
D188
D189
D190
D191
D192
S25
D193
D194
D195
D196
D197
D198
D199
D200
S26
D201
D202
D203
D204
D205
D206
D207
D208
S27
D209
D210
D211
D212
D213
D214
D215
D216
S28
D217
D218
D219
D220
D221
D222
D223
D224
S29
D225
D226
D227
D228
D229
D230
D231
D232
S30
D233
D234
D235
D236
D237
D238
D239
D240
S31
D241
D242
D243
D244
D245
D246
D247
D248
S32
D249
D250
D251
D252
D253
D254
D255
D256
S33
D257
D258
D259
D260
D261
D262
D263
D264
S34
D265
D266
D267
D268
D269
D270
D271
D272
S35
D273
D274
D275
D276
D277
D278
D279
D280
S36
D281
D282
D283
D284
D285
D286
D287
D288
S37
D289
D290
D291
D292
D293
D294
D295
D296
S38
D297
D298
D299
D300
D301
D302
D303
D304
S39/COM10
D305
D306
D307
D308
D309
D310
D311
D312
S40/COM9
D313
D314
D315
D316
D317
D318
D319
D320
Note: Applies when the S39/COM10 and S40/COM9 output pins are set to their segment output function.
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22
LC75838W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D81
D82
D83
D84
D85
D86
D87
D88
0
0
0
0
0
0
0
0
The LCD segments for COM1 to COM8 are off
1
0
0
0
0
0
0
0
The LCD segment for COM1 is on
0
1
0
0
0
0
0
0
The LCD segment for COM2 is on
0
0
1
0
0
0
0
0
The LCD segment for COM3 is on
0
0
0
1
0
0
0
0
The LCD segment for COM4 is on
0
0
0
0
1
0
0
0
The LCD segment for COM5 is on
0
0
0
0
0
1
0
0
The LCD segment for COM6 is on
0
0
0
0
0
0
1
0
The LCD segment for COM7 is on
0
0
0
0
0
0
0
1
The LCD segment for COM8 is on
1
1
1
1
1
1
1
1
The LCD segments for COM1 to COM8 are on
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23
LC75838W
 1/9 duty
Output Pin
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
S1
D1
D2
D3
D4
D5
D6
D7
D8
D9
S2
D10
D11
D12
D13
D14
D15
D16
D17
D18
S3
D19
D20
D21
D22
D23
D24
D25
D26
D27
S4
D28
D29
D30
D31
D32
D33
D34
D35
D36
S5
D37
D38
D39
D40
D41
D42
D43
D44
D45
S6
D46
D47
D48
D49
D50
D51
D52
D53
D54
S7
D55
D56
D57
D58
D59
D60
D61
D62
D63
S8
D64
D65
D66
D67
D68
D69
D70
D71
D72
S9
D73
D74
D75
D76
D77
D78
D79
D80
D81
S10
D82
D83
D84
D85
D86
D87
D88
D89
D90
S11
D91
D92
D93
D94
D95
D96
D97
D98
D99
S12
D100
D101
D102
D103
D104
D105
D106
D107
D108
S13
D109
D110
D111
D112
D113
D114
D115
D116
D117
S14
D118
D119
D120
D121
D122
D123
D124
D125
D126
S15
D127
D128
D129
D130
D131
D132
D133
D134
D135
S16
D136
D137
D138
D139
D140
D141
D142
D143
D144
S17
D145
D146
D147
D148
D149
D150
D151
D152
D153
S18
D154
D155
D156
D157
D158
D159
D160
D161
D162
S19
D163
D164
D165
D166
D167
D168
D169
D170
D171
S20
D172
D173
D174
D175
D176
D177
D178
D179
D180
S21
D181
D182
D183
D184
D185
D186
D187
D188
D189
S22
D190
D191
D192
D193
D194
D195
D196
D197
D198
S23
D199
D200
D201
D202
D203
D204
D205
D206
D207
S24
D208
D209
D210
D211
D212
D213
D214
D215
D216
S25
D217
D218
D219
D220
D221
D222
D223
D224
D225
S26
D226
D227
D228
D229
D230
D231
D232
D233
D234
S27
D235
D236
D237
D238
D239
D240
D241
D242
D243
S28
D244
D245
D246
D247
D248
D249
D250
D251
D252
S29
D253
D254
D255
D256
D257
D258
D259
D260
D261
S30
D262
D263
D264
D265
D266
D267
D268
D269
D270
S31
D271
D272
D273
D274
D275
D276
D277
D278
D279
S32
D280
D281
D282
D283
D284
D285
D286
D287
D288
S33
D289
D290
D291
D292
D293
D294
D295
D296
D297
S34
D298
D299
D300
D301
D302
D303
D304
D305
D306
S35
D307
D308
D309
D310
D311
D312
D313
D314
D315
S36
D316
D317
D318
D319
D320
D321
D322
D323
D324
S37
D325
D326
D327
D328
D329
D330
D331
D332
D333
S38
D334
D335
D336
D337
D338
D339
D340
D341
D342
S39/COM10
D343
D344
D345
D346
D347
D348
D349
D350
D351
Note: Applies when the S39/COM10 output pin is set to its segment output function.
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24
LC75838W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D91
D92
D93
D94
D95
D96
D97
D98
D99
0
0
0
0
0
0
0
0
0
The LCD segments for COM1 to COM9 are off
1
0
0
0
0
0
0
0
0
The LCD segment for COM1 is on
0
1
0
0
0
0
0
0
0
The LCD segment for COM2 is on
0
0
1
0
0
0
0
0
0
The LCD segment for COM3 is on
0
0
0
1
0
0
0
0
0
The LCD segment for COM4 is on
0
0
0
0
1
0
0
0
0
The LCD segment for COM5 is on
0
0
0
0
0
1
0
0
0
The LCD segment for COM6 is on
0
0
0
0
0
0
1
0
0
The LCD segment for COM7 is on
0
0
0
0
0
0
0
1
0
The LCD segment for COM8 is on
0
0
0
0
0
0
0
0
1
The LCD segment for COM9 is on
1
1
1
1
1
1
1
1
1
The LCD segments for COM1 to COM9 are on
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25
LC75838W
 1/10 duty
Output Pin
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
S1
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
S2
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
S3
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
S4
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
S5
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
S6
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
S7
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
S8
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
S9
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
S10
D91
D92
D93
D94
D95
D96
D97
D98
D99
D100
S11
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
S12
D111
D112
D113
D114
D115
D116
D117
D118
D119
D120
S13
D121
D122
D123
D124
D125
D126
D127
D128
D129
D130
S14
D131
D132
D133
D134
D135
D136
D137
D138
D139
D140
S15
D141
D142
D143
D144
D145
D146
D147
D148
D149
D150
S16
D151
D152
D153
D154
D155
D156
D157
D158
D159
D160
S17
D161
D162
D163
D164
D165
D166
D167
D168
D169
D170
S18
D171
D172
D173
D174
D175
D176
D177
D178
D179
D180
S19
D181
D182
D183
D184
D185
D186
D187
D188
D189
D190
S20
D191
D192
D193
D194
D195
D196
D197
D198
D199
D200
S21
D201
D202
D203
D204
D205
D206
D207
D208
D209
D210
S22
D211
D212
D213
D214
D215
D216
D217
D218
D219
D220
S23
D221
D222
D223
D224
D225
D226
D227
D228
D229
D230
S24
D231
D232
D233
D234
D235
D236
D237
D238
D239
D240
S25
D241
D242
D243
D244
D245
D246
D247
D248
D249
D250
S26
D251
D252
D253
D254
D255
D256
D257
D258
D259
D260
S27
D261
D262
D263
D264
D265
D266
D267
D268
D269
D270
S28
D271
D272
D273
D274
D275
D276
D277
D278
D279
D280
S29
D281
D282
D283
D284
D285
D286
D287
D288
D289
D290
S30
D291
D292
D293
D294
D295
D296
D297
D298
D299
D300
S31
D301
D302
D303
D304
D305
D306
D307
D308
D309
D310
S32
D311
D312
D313
D314
D315
D316
D317
D318
D319
D320
S33
D321
D322
D323
D324
D325
D326
D327
D328
D329
D330
S34
D331
D332
D333
D334
D335
D336
D337
D338
D339
D340
S35
D341
D342
D343
D344
D345
D346
D347
D348
D349
D350
S36
D351
D352
D353
D354
D355
D356
D357
D358
D359
D360
S37
D361
D362
D363
D364
D365
D366
D367
D368
D369
D370
S38
D371
D372
D373
D374
D375
D376
D377
D378
D379
D380
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26
LC75838W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Output pin state (S11)
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
0
0
0
0
0
0
0
0
0
0
The LCD segments for COM1 to COM10 are off
1
0
0
0
0
0
0
0
0
0
The LCD segment for COM1 is on
0
1
0
0
0
0
0
0
0
0
The LCD segment for COM2 is on
0
0
1
0
0
0
0
0
0
0
The LCD segment for COM3 is on
0
0
0
1
0
0
0
0
0
0
The LCD segment for COM4 is on
0
0
0
0
1
0
0
0
0
0
The LCD segment for COM5 is on
0
0
0
0
0
1
0
0
0
0
The LCD segment for COM6 is on
0
0
0
0
0
0
1
0
0
0
The LCD segment for COM7 is on
0
0
0
0
0
0
0
1
0
0
The LCD segment for COM8 is on
0
0
0
0
0
0
0
0
1
0
The LCD segment for COM9 is on
0
0
0
0
0
0
0
0
0
1
The LCD segment for COM10 is on
1
1
1
1
1
1
1
1
1
1
The LCD segments for COM1 to COM10 are on
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27
LC75838W
1/8 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
COM1
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM8
VLCD3
VLCD4
VLCD0
LCD driver output when all LCD
segments corresponding to
COM1 to COM8 are turned off
VLCD1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when only
LCD segments corresponding
to COM1 are turned on
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when only
LCD segments corresponding
to COM2 are turned on
VLCD2
VLCD3
VLCD4
VLCD0
LCD driver output when all LCD
segments corresponding to
COM1 to COM8 are turned on
VLCD1
VLCD2
VLCD3
VLCD4
64T
512T
T=
1
fosc
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28
LC75838W
1/9 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
VLCD2
COM1
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM9
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when all LCD
segments corresponding to
COM1 to COM9 are turned off
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when only
LCD segments corresponding
to COM1 are turned on
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when only
LCD segments corresponding
to COM2 are turned on
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when all LCD
segments corresponding to
COM1 to COM9 are turned on
VLCD2
VLCD3
VLCD4
64T
576T
1
T= fosc
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29
LC75838W
1/10 Duty, 1/4 Bias Drive Technique
VLCD0
VLCD1
COM1
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM2
VLCD3
VLCD4
VLCD0
VLCD1
VLCD2
COM10
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when all LCD
segments corresponding to
COM1 to COM10 are turned off
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when only
LCD segments corresponding
to COM1 are turned on
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when only
LCD segments corresponding
to COM2 are turned on
VLCD2
VLCD3
VLCD4
VLCD0
VLCD1
LCD driver output when all LCD
segments corresponding to
COM1 to COM10 are turned on
VLCD2
VLCD3
VLCD4
64T
640T
T=
1
fosc
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30
LC75838W
The INH Pin and Display Control
Since the IC internal data (the display data and the control data) is undefined when power is first applied, applications
should set the INH pin low at the same time as power is applied to turn off the display (This sets the S1 to S38,
S39/COM10, S40/COM9, and COM1 to COM8 to the VLCD4 level and the P1 to P3 to the VSS level.) and during this
period send serial data from the controller. The controller should then set the INH pin high after the data transfer has
completed. This procedure prevents meaningless displays at power on. (See figures 3, 4, and 5.)
Power Supply Sequence
The following sequences must be observed when power is turned on and off. (See figures 3, 4, and 5.)
• Power on: Logic block power supply (VDD) on  LCD driver block power supply (VLCD) on
• Power off: LCD driver block power supply (VLCD) off  Logic block power supply (VDD) off
However, if the logic and LCD driver blocks use a shared power supply, then the power supplies can be turned on and
off at the same time.
• 1/8 duty
t2

t1
t3

VDD

VLCD
INH
CE
Display and control data transfer

VIL
tc
VIL
Internal data (D1 to D80)
Undefined
Defined
Undefined
Internal data (D81 to D160)
Undefined
Defined
Undefined
Internal data (D161 to D240)
Undefined
Defined
Undefined
Internal data (D241 to D320)
Undefined
Defined
Undefined
PC1 to PC3
Internal data CT0 to CT3, CTC
SC, BU, DT1, DT2
Undefined
Defined
Undefined
• t1  0
• t2 > 0
• t3  0 (t2 > t3)
• tc .... 10s min
Figure 3
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31
LC75838W
• 1/9 duty
t2
t1

t3

VDD

VLCD
INH
CE
Display and control data transfer

VIL
tc
VIL
Internal data (D1 to D90)
Undefined
Defined
Undefined
Internal data (D91 to D180)
Undefined
Defined
Undefined
Internal data (D181 to D270)
Undefined
Defined
Undefined
Internal data (D271 to D351)
Undefined
Defined
Undefined
PC1 to PC3
Internal data CT0 to CT3, CTC
SC, BU, DT1, DT2
Undefined
Defined
Undefined
• t1  0
• t2 > 0
• t3  0 (t2 > t3)
• tc .... 10s min
Figure 4
• 1/10 duty
t2

t1
t3

VDD

VLCD
INH
CE
Display and control data transfer

VIL
tc
VIL
Internal data (D1 to D100)
Undefined
Defined
Undefined
Internal data (D101 to D200)
Undefined
Defined
Undefined
Internal data (D201 to D300)
Undefined
Defined
Undefined
Internal data (D301 to D380)
Undefined
Defined
Undefined
PC1 to PC3
Internal data CT0 to CT3, CTC
SC, BU, DT1, DT2
Undefined
Defined
Undefined
• t1  0
• t2 > 0
• t3  0 (t2 > t3)
• tc .... 10s min
Figure 5
Notes on Transferring Display Data from the Controller
The display data is transferred to the LC75838W in four operations. All of the display data should be transferred within
30ms to maintain the quality of the displayed image.
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32
LC75838W
Sample Application Circuit 1
1/8 duty, 1/4 bias drive technique (for use with normal panels)
+5V
COM1
VDD
COM2
COM3
COM4
COM5
COM6
COM7
COM8
VSS
+8V
VLCD
OPEN
LCD panel
VLCD0
VLCD1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD2
VLCD3
C
C
C
VLCD4 *2
C0.047F
OSC
S36
S37
S38
COM10/S39
COM9/S40
INH
CE
CL
DI
From
the controller
P1
P2
P3
General-purpose output ports
Used with the backlight
controller or other circuit.
Note: *2. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
Sample Application Circuit 2
1/8 duty, 1/4 bias drive technique (for use with large panels)
+5V
COM1
VDD
COM2
COM3
COM4
COM5
COM6
COM7
COM8
VSS
+8V
LCD panel
VLCD
VLCD0
R
VLCD1
R
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD2
R
VLCD3
C
C
C
R
VLCD4 *2
C0.047F
10kR2.2k
OSC
From
the controller
S36
S37
S38
COM10/S39
COM9/S40
INH
CE
CL
DI
P1
P2
P3
General-purpose output ports
Used with the backlight
controller or other circuit.
Note: *2. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
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33
LC75838W
Sample Application Circuit 3
1/9 duty, 1/4 bias drive technique (for use with normal panels)
+5V
COM1
VDD
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S40/COM9
VSS
+8V
VLCD
OPEN
LCD panel
VLCD0
VLCD1
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
C
C
C
VLCD4 *2
C0.047F
OSC
S36
S37
S38
COM10/S39
INH
CE
CL
DI
From
the controller
P1
P2
P3
General-purpose output ports
Used with the backlight
controller or other circuit.
Note: *2. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
Sample Application Circuit 4
1/9 duty, 1/4 bias drive technique (for use with large panels)
+5V
COM1
VDD
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S40/COM9
VSS
+8V
LCD panel
VLCD
VLCD0
R
VLCD1
R
VLCD2
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
R
VLCD3
C
C
C
R
VLCD4 *2
C0.047F
10kR2.2k
OSC
S36
S37
S38
COM10/S39
From
the controller
INH
CE
CL
DI
P1
P2
P3
General-purpose output ports
Used with the backlight
controller or other circuit.
Note: *2. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
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34
LC75838W
Sample Application Circuit 5
1/10 duty, 1/4 bias drive technique (for use with normal panels)
+5V
COM1
VDD
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S40/COM9
S39/COM10
VSS
+8V
VLCD
OPEN
LCD panel
VLCD0
VLCD1
VLCD2
VLCD3
C
C
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
C
VLCD4 *2
C0.047F
OSC
S36
S37
S38
INH
CE
CL
DI
From
the controller
P1
P2
P3
General-purpose output ports
Used with the backlight
controller or other circuit.
Note: *2. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
Sample Application Circuit 6
1/10 duty, 1/4 bias drive technique (for use with large panels)
+5V
COM1
VDD
COM2
COM3
COM4
COM5
COM6
COM7
COM8
S40/COM9
S39/COM10
VSS
+8V
LCD panel
VLCD
VLCD0
R
VLCD1
R
VLCD2
R
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
VLCD3
C
C
C
R
VLCD4 *2
C0.047F
10kR2.2k
OSC
S36
S37
S38
From
the controller
INH
CE
CL
DI
P1
P2
P3
General-purpose output ports
Used with the backlight
controller or other circuit.
Note: *2. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to
ground.
www.onsemi.com
35
LC75838W
ORDERING INFORMATION
Device
LC75838W-E
Package
SPQFP64 10x10 / SQFP64
(Pb-Free)
LC75838WS-E
SPQFP64 10x10 / SQFP64
(Pb-Free)
Shipping (Qty / Packing)
500 / Tray Foam
500 / Tray Foam
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and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
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further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
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directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
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