NCS2302 Headset Detection Interface with Send/End Detect The NCS2302 is a compact and cost effective headset detection interface IC. It integrates several circuit blocks to detect the presence of a stereo headset with a microphone and whether the send/end button has been pressed. The NMOS transistor on the MIC pin mutes the signal when the headset is not present. The built in resistor divider provides the reference voltage for detecting the left audio channel. When L_DET and GND_DET are pulled low, the logic low output of the OR gate indicates the headset has been connected properly and the MIC pull−down is disabled. A comparator is integrated for detecting the send/end button press. The NCS2302 comes in a space−saving UQFN10 package (1.4 x 1.8 mm). http://onsemi.com 1 UQFN10 MU SUFFIX CASE 488AT MARKING DIAGRAM Features • Wide Supply Voltage Ranges: • • • • For Headset Detection Circuit: VDD = 1.6 V to 2.5 V For S/E Comparator Circuit: VDD2 = 1.6 V to 2.8 V Low Quiescent Supply Current: 17 mA typical Low Impedance MIC Pull−Down Reduces Pop & Click Noise: RDS(ON) = 0.45 W Typical Space Saving UQFN10 Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Cell Phones, Smartphones • Tablets • Notebooks AQMG G AQ = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) PIN DIAGRAM S/E_DET 8 S/E_REF 9 VDD2 10 S/E DET 7 6 1 5 GND_DET 4 L_DET 3 VDD 2 GND MIC Top View ORDERING INFORMATION Device NCS2302MUTAG Package Shipping† UQFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 3 1 Publication Order Number: NCS2302/D NCS2302 Baseband Processor GPIO GPIO VDD 2 S/E 7 S/E detection 6 DET GND_DET 5 8 S/E_DET NCS2302 L_DET 4 9 S/E_REF VDD2 Audio Codec VDD VDD 10 VDD 2 MIC bias voltage GND 1 3 2 MIC 2.2 k MIC GND_DET L_DET MIC L R GND Output to speakers L R G M Figure 1. Simplified Application Schematic NCS2302 S/E_REF S/E_DET VDD2 S/E 9 8 10 7 + − VDD MIC 6 DET 1 GND VDD VDD 270k 2 − + 1M VDD VDD 1M 1M VDD 4 5 3 L_DET GND_DET VDD Figure 2. Block Diagram http://onsemi.com 2 NCS2302 Table 1. OUTPUT LOGIC Inputs Outputs L_detect GND_detect DET MIC Headset 0 0 0 1 (external pull−up) Detected 0 1 1 0 1 0 1 0 1 1 1 0 Not Detected Table 2. PIN DESCRIPTION Pin Name Type Description 1 GND Power Connects to system ground. 2 MIC Output The open drain MIC pin is connected to the audio jack MIC pin. The MIC pin will pull low when the headset is not connected. When the headset is detected, the internal pull−down is disabled and the external pull−up biases the microphone. 3 VDD Power Supply voltage pin for headset detection circuit. A bypass capacitor of 0.1 mF is recommended as close as possible to this pin. 4 L_DET Input Connect to audio jack L_DET. This pin is pulled low when the headset is present. 5 GND_DET Input Connect to audio jack GND_DET. This pin is pulled low when the headset is present. 6 DET Output Indicates whether headset has been detected. Headset is detected when DET is low. 7 S/E Output Indicates whether send/end button press has been detected. Button press is detected when S/E is low. 8 S/E_DET Input Non−inverting input of the comparator detects whether the send/end button has been pressed. 9 S/E_REF Input Inverting input of the comparator sets a voltage reference with an external resistor divider 10 VDD2 Power Supply voltage pin for S/E detection comparator. A bypass capacitor of 0.1 mF is recommended as close as possible to this pin. Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Supply Voltage Range of Headset Detection Circuit VDD 0 to 2.75 V Supply Voltage Range of S/E Detection Comparator VDD2 0 to 2.95 V Input Pin Voltage Range (L_DET, GND_DET) VIN −0.1 to VDD + 0.1 V Input Pin Voltage Range (S/E_REF, S/E_DET) (Note 4) VIN −0.1 to min(VDD2 + 0.6, 3.3) V MIC Output Pin Voltage Range VMIC 0 to 6.0 V Max Current on MIC Pin IMIC 2 mA TJ(max) +125 °C Tstg −65 to +150 °C ILU 800 mA MSL Level 1 Maximum Junction Temperature Storage Temperature Range Latch−up Current (Note 2) Moisture Sensitivity Level (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. Latch−up Current tested per JEDEC standard: JESD78 3. Moisture Sensitivity Level tested per IPC/JEDEC standard: J−STD−020A 4. The maximum voltage on the S/E_REF and S/E_DET pins must be the lesser of VDD2 + 0.6 and 3.3 V. http://onsemi.com 3 NCS2302 Table 4. RECOMMENDED OPERATING RANGES Rating Conditions Power Supply Voltage Input Voltage Symbol Min Typ Max Unit Headset Detection Circuit VDD 1.6 1.8 2.5 V S/E Detection Comparator VDD2 1.6 2.8 V VIN 0 VDD V 0 VDD2 V 0 10 ns/V L_DET, GND_DET S/E_DET, S/E_REF Input Transition Rise or Fall Rate Dt / DV GND_DET pin MIC Bias Voltage VMIC 0 2.95 V Ambient Temperature TA −40 85 °C Junction Temperature TJ −40 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 5. ELECTRICAL CHARACTERISTICS Typical values are referenced to TA = 25°C, VDD = 1.8 V, VDD2 = 2.1 V, unless otherwise noted. Min/max values apply from TA = −40°C to 85°C, unless otherwise noted. (Notes 5, 6) Test Conditions Parameter Symbol Min Typ Max Units SUPPLY CHARACTERISTICS Quiescent Supply Current Headset Detection Circuit, VGND_DET = 1.8 V, VL_DET = 1.8 V IDD 7 8.5 mA S/E Detection Comparator, VSE_REF = 0 V, VSE_DET = 2.1 V IDD2 10 12.5 mA 1.33 V INPUT CHARACTERISTICS OF L_DET Voltage Input Low VIL Voltage Input High VIH 1.5 V Propagation Delay to DET Cout = 15 pF, GND_DET = 0 V, L_DET = 1.31 V to 1.52 V tpLH, tpHL 45 ns Low to High Propagation Delay to MIC Cout = 15 pF, GND_DET = 0 V, L_DET = 1.31 V to 1.52 V, RPU = 2.2 kW, MIC bias = 2.3 V tpLH 230 ns High to Low Propagation Delay to MIC Cout = 15 pF, GND_DET = 0 V, L_DET = 1.31 V to 1.52 V, RPU = 2.2 kW, MIC bias = 2.3 V tpHL 30 ns Low Voltage Input Bias Current VL_DET = 0 V IIL 1.8 mA High Voltage Input Leakage VL_DET = 1.8 V IIH 2.4 nA Input Capacitance f = 1 MHz CIN 3 pF INPUT CHARACTERISTICS OF GND_DET Voltage Input Low VIL 0.63 Voltage Input High VIH Low to High Propagation Delay to DET Cout = 15 pF, RL = 1 MW, L_detect = 0 V, GND_detect = 1.8 to 0 V tpLH 30 ns High to Low Propagation Delay to DET Cout = 15 pF, RL = 1 MW, L_detect = 0 V, GND_detect = 0 to 1.8 V tpHL 16 ns 1.17 V V Low Voltage Input Bias Current VGND_detect = 0 V IIL 1.8 mA High Voltage Input Leakage VGND_detect = 1.8 V IIH 2.7 nA Input Capacitance f = 1 MHz CIN 3 pF 5. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. http://onsemi.com 4 NCS2302 Table 5. ELECTRICAL CHARACTERISTICS Typical values are referenced to TA = 25°C, VDD = 1.8 V, VDD2 = 2.1 V, unless otherwise noted. Min/max values apply from TA = −40°C to 85°C, unless otherwise noted. (Notes 5, 6) Parameter Test Conditions Symbol Min Typ Max Units 0.1 V OUTPUT CHARACTERISTICS OF DET Voltage Output Low IOH = 0.1 mA VOL Voltage Output High IOH = −0.1 mA VOH Rise Time COUT = 15 pF, RL = 1 MW trise 50 ns Fall Time COUT = 15 pF, RL = 1 MW tfall 28 ns tpLH, tpHL 50 ns 150 pA 3 pF 1.6 V INPUT CHARACTERISTICS OF S/E_REF AND S/E_DET Propagation Delay to S/E Cout = 15 pF, VCM = mid−supply, 100 mV overdrive Input Leakage VCM = 0.9 V IIL Input Capacitance S/E_DET, f = 1 MHz CIN S/E_REF, f = 1 MHz 11 OUTPUT CHARACTERISTICS OF S/E Voltage Output Low IOH = 0.1 mA VOL 0.1 V Voltage Output High IOH = −0.1 mA VOH Rise Time COUT = 15 pF, RL = 1 MW trise 30 ns Fall Time COUT = 15 pF, RL = 1 MW tfall 18 ns RDS(ON) 0.45 1.9 V CHARACTERISTICS OF MIC Drain−Source On Resistance of NMOS IMIC = 1 mA W 1.2 5. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area. 6. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. TYPICAL CHARACTERISTICS 0.8 VDD = 1.6 V MIC RDS(on) RESISTANCE (W) MIC RDS(on) RESISTANCE (W) 0.8 0.7 0.6 T = 85°C 0.5 T = 25°C T = −40°C 0.4 0.3 VDD = 1.8 V 0.7 0.6 T = 85°C 0.5 T = 25°C 0.4 T = −40°C 0.3 0.2 0.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.5 1.0 5.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 MIC DRAIN CURRENT (mA) MIC DRAIN CURRENT (mA) Figure 3. MIC On Resistance vs. Drain Current at VDD = 1.6 V Figure 4. MIC On Resistance vs. Drain Current at VDD = 1.8 V http://onsemi.com 5 NCS2302 TYPICAL CHARACTERISTICS VDD = 2.0 V 1.6 4.0 1.5 INPUT 3.5 INPUT VOLTAGE (V) 0.7 0.6 T = 85°C 0.5 T = 25°C 0.4 T = −40°C 1.4 VDD = 1.8 V VDD2 = 2.1 V 1.3 RL = 1 MW CL = 15 pF TA = 25°C 1.1 1.5 100 mV 50 mV 20 mV 10 mV OUTPUT 1.0 0.9 1.0 0.5 0 0.8 0.5 1.0 1.5 2.0 3.0 2.5 3.5 4.0 0.7 −100 5.0 4.5 0 MIC DRAIN CURRENT (mA) 100 200 4.0 VDD = 1.8 V VDD2 = 2.1 V INPUT VOLTAGE (V) RL = 1 MW CL = 15 pF TA = 25°C 3.5 3.0 1.3 2.5 1.2 2.0 1.1 1.5 100 mV 50 mV 20 mV 10 mV OUTPUT 1.0 0.9 1.0 0.5 0.8 OUTPUT VOLTAGE (V) 1.4 0 0.7 −100 0 100 200 300 400 −0.5 500 PROPAGATION DELAY (ns) Figure 7. High to Low Propagation to DET with Changing Input Overdrive of L_DET 4.0 0.8 3.5 VDD = 1.8 V VDD2 = 2.1 V 0.5 RL = 1 MW CL = 15 pF TA = 25°C 3.0 2.5 2.0 0.4 0.3 1.5 100 mV 50 mV 20 mV 10 mV 0.2 0.1 OUTPUT 1.0 0.5 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) 0.7 INPUT 0.6 0 0 −0.1 −100 0 400 −0.5 500 Figure 6. Low to High Propagation to DET with Changing Input Overdrive of L_DET 1.6 INPUT 300 PROPAGATION DELAY (ns) Figure 5. MIC On Resistance vs. Drain Current at VDD = 2.0 V 1.5 2.5 2.0 1.2 0.3 0.2 3.0 100 200 300 400 −0.5 500 PROPAGATION DELAY (ns) Figure 8. Low to High Propagation to SE with Changing Input Overdrive of SE_DET http://onsemi.com 6 OUTPUT VOLTAGE (V) MIC RDS(on) RESISTANCE (W) 0.8 NCS2302 TYPICAL CHARACTERISTICS 0.8 4.0 VDD = 1.8 V VDD2 = 2.1 V 0.7 0.6 3.5 3.0 0.5 2.5 0.4 2.0 100 mV 50 mV 20 mV 10 mV 0.3 0.2 0.1 0 1.5 1.0 0.5 OUTPUT −0.1 −100 0 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT RL = 1 MW CL = 15 pF TA = 25°C 0 100 200 300 400 500 600 −0.5 700 PROPAGATION DELAY (ns) Figure 9. High to Low Propagation to SE with Changing Input Overdrive of SE_DET APPLICATIONS INFORMATION Supply Voltages The NCS2302 can work with either the CTIA or OMTP standard. In order to support both standards simultaneously, a cross point switch and additional circuitry is necessary to detect and swap the ground and microphone pins. The NCS2302 works with a wide range of supply voltages. The main headset detection circuitry power supply can range from VDD = 1.6 V to 2.5 V. The send/end button press detection circuit can be powered from VDD2 = 1.6 to 2.8 V. VDD should be powered up before VDD2. The send/end detection comparator will not be functional unless VDD and VDD2 are both applied. VDD2 can be connected to VDD or to a separate supply voltage, such as the MIC bias voltage. Decoupling capacitors of 0.1 mF should be placed as close as possible to each power supply pin. Since the NCS2302 has built in latch−up immunity up to 800 mA, series resistors are not recommended on VDD or VDD2. Send/End Button Press Detection A second integrated comparator allows the send/end signal to be compared with a reference voltage to detect whether the send/end button has been pressed. MIC Pin Biasing The typical application schematic in Figure 1 shows the recommended 2.2 kW pull−up resistor to the MIC bias voltage. The MIC bias voltage can exceed VDD and can go as high as 2.95 V. When the headset is not detected, the internal NMOS transistor is enabled to mute the MIC signal. In the typical application scenario with a 2.2 kW pull−up to a 2.1 V MIC bias voltage, the MIC pin is pulled to 1 mV when the headset is not present. The internal NMOS transistor is optimized to sink up to 2 mA of current, allowing some flexibility in the selection of the pull−up resistor and MIC bias voltage. Audio Jack Detection The NCS2302 is designed to simplify the detection of a stereo audio connector with a microphone contact. When the headset is not connected, the internal pull−up resistors on L_DET and GND_DET pull those pins high. When the headset is connected to the switched audio jack, the headset ground and left audio channel trigger L_DET and GND_DET to logic low. http://onsemi.com 7 NCS2302 PACKAGE DIMENSIONS UQFN10 1.4x1.8, 0.4P CASE 488AT ISSUE A EDGE OF PACKAGE D ÉÉÉ ÉÉÉ ÉÉÉ PIN 1 REFERENCE 2X 2X 0.10 C L1 E DETAIL A Bottom View (Optional) 0.10 C B TOP VIEW A1 0.05 C A1 3 DIM A A1 A3 b D E e L L1 L3 MOLD CMPD A3 MOUNTING FOOTPRINT 5 e/2 L 1.700 0.0669 6 e 1 10 MILLIMETERS MIN MAX 0.45 0.60 0.00 0.05 0.127 REF 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.00 0.15 0.40 0.60 DETAIL B Side View (Optional) SEATING PLANE C SIDE VIEW 9X ÉÉÉ ÉÉÉ EXPOSED Cu A 0.05 C 10X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A 10 X L3 b 0.663 0.0261 0.200 0.0079 0.10 C A B 0.05 C 9X 0.563 0.0221 1 NOTE 3 BOTTOM VIEW 2.100 0.0827 0.400 0.0157 PITCH 10 X 0.225 0.0089 SCALE 20:1 mm Ǔ ǒinches ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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