TPS65133 www.ti.com SLVSC01 – JUNE 2013 ±5 V, 250 mA Dual Output Power Supply FEATURES DESCRIPTION • • The TPS65133 is designed to drive LCD displays requiring a positive and negative supply rail. It may also be used as a general ±5 V supply for operational amplifiers or other devices requiring similar positive and negative supplies. The device integrates a boost converter and an inverting buck-boost converter suitable for battery operated products. 1 • • • • • • • • • 2.9 V to 5.0 V Input Voltage Range Fixed 5.0 V VPOS Output Voltage – 1% Output Voltage Accuracy Fixed 5.0 V VNEG Output Voltage – 1% Output Voltage Accuracy Up to 250 mA Output Current from VPOS and VNEG Excellent Line and Load Transient Response Operates in CCM Mode for Noise Free Output Voltage Boost Converter Able to Operate in "Down Mode" (VIN close to or above VPOS) High Converter Efficiency Short Circuit Protection Thermal Shutdown 3×3 mm 12 Pin QFN Package APPLICATIONS • • • • LCD Bias Active Matrix OLED Operational Amplifier Supply General ±5 V Power Supply TYPICAL APPLICATION L1, 4.7μH VIN 2.9V...5V C1 10μF C4 100nF EN TPS65133 PVIN SWP AVIN VPOS VPOS 5V / 250mA C2 10μF PGND AGND VNEG EN SWN VNEG -5V / 250mA C3 10μF L2, 4.7μH 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS65133 SLVSC01 – JUNE 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) (2) TA PACKAGE ORDERING P/N TOP-SIDE MARKING –40°C to 85°C 12-Pin 3x3 QFN TPS65133DPDR SHY For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Input voltage range (2) MIN MAX SWP, VPOS, PVIN, AVIN, EN -0.3 6.0 VNEG -6.5 0.3 SWN -6.5 5.5 HBM ESD rating UNIT V 2 kV MM 200 V CDM 500 V Operating junction temperature range TJ -40 150 °C Operating ambient temperature range TA -40 85 °C Storage temperature range Tstg -65 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. With respect to GND pin. THERMAL INFORMATION THERMAL METRIC (1) QFN (12 PINS) UNIT θJA Junction-to-ambient thermal resistance 51.5 °C/W θJB Junction-to-board thermal resistance 25.0 °C/W ΨJT Junction-to-top characterization parameter 0.5 °C/W ΨJB Junction-to-board characterization parameter 25.2 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS (1) MIN NOM MAX VIN Input voltage range 2.9 3.7 5 V TA Operating ambient temperature -40 85 °C TJ Operating junction temperature -40 125 °C (1) 2 UNIT Refer to application section for further information. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS65133 www.ti.com SLVSC01 – JUNE 2013 ELECTRICAL CHARACTERISTICS VIN = 3.7V, EN = VIN, VPOS = 5V, VNEG = -5V, TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5 V 0.1 15 μA SUPPLY CURRENT AND THERMAL PROTECTION VIN Input voltage range ISD Shutdown current into VIN UVLO Under-voltage lockout threshold TSD Thermal shutdown temperature 2.9 EN = GND VIN falling 2.1 VIN rising 2.5 135 V °C LOGIC SIGNALS VH Logic high-level voltage VL Logic low-level voltage 1.2 V 0.4 V 5.05 V BOOST CONVERTER (VPOS) VPOS RDS(ON) Positive output voltage SWP MOSFET on-resistance SWP MOSFET rectifier on-resistance 4.95 5 250 ISWP = 200mA mΩ 350 fSWP SWP switching frequency IPOS = 200mA 1.2 1.7 2.2 ISWP SWP switch current limit Inductor valley current 0.8 1.1 VP(SCP) Short circuit threshold in operation VPOS falling tP(SCP) Short circuit detection time in operation RP(DCG) VPOS Discharge resistance EN = GND, IPOS = 1mA Line regulation IPOS = 100 mA .02 %/V Load regulation VIN = 3.7 V .24 %/A A 4.1 1 15 MHz V 3 5 30 60 ms Ω BUCK-BOOST CONVERTER (VNEG) VNEG RDS(ON) Negative output voltage default SWN MOSFET on-resistance SWN MOSFET rectifier on-resistance -5.05 ISWN = 200mA fSWN SWN switching frequency INEG = 200mA ISWN SWN switch current limit Inductor valley current VN(SCP) Short circuit threshold in operation tN(SCP) Short circuit detection time in operation RN(DCG) VNEG Discharge resistance tN(DLY) Start-up delay time after VPOS reaches target output to when VNEG will begin startup EN = GND, INEG = 1mA -5 -4.95 250 V mΩ 350 1 1.7 1.5 2.2 2.4 A -4.5 V 1 3 5 100 150 200 MHz ms Ω 2 ms Line regulation INEG = 100 mA .01 %/V Load regulation VIN = 3.7 V .16 %/A Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS65133 SLVSC01 – JUNE 2013 www.ti.com DEVICE INFORMATION 10 PIN TQFN PACKAGE (TOP VIEW) SWP 1 12 PVIN PGND 2 11 AVIN VPOS 3 10 SWN GND 4 9 VNEG AGND 5 8 GND GND 6 7 EN Exposed Thermal Pad Table 1. Pin Functions (1) 4 TYPE (1) NO. NAME 1 SWP I DESCRIPTION Switch pin of the boost converter 2 PGND G Power ground of the boost converter 3 VPOS O Output of the boost converter (VPOS), place a capacitor close to this pin. 4 GND G Ground 5 AGND G Analog ground 6 GND G Ground 7 EN I Enable of boost and buck boost converter 8 GND G Ground 9 VNEG O Output of the negative buck boost converter (VNEG), place a capacitor close to this pin 10 SWN I Switch pin of the negative buck boost converter 11 AVIN I Internal logic supply pin 12 PVIN I Supply pin for the negative buck boost converter. Place a capacitor close to this pin — Exposed thermal pad G Connect this pad to all GND pins G = Ground, I = Input, O = Output Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS65133 www.ti.com SLVSC01 – JUNE 2013 FUNCTIONAL BLOCK DIAGRAM AVIN Thermal Shutdown Bandgap (typ. 135°C) VREF Unvdervoltage Lockout (max 2.5 V) AGND Start Boost EN Power Good Start Timer 2 ms Start Buck-Boost SWP VPOS PGND Short Circuit Protection Discharge Current Limit Boost Control Logic VREF Oscillator Constant Off-time Control VREF Buck-Boost Control Logic Current Limit PVIN Short Circuit Protection Discharge VNEG SWN Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS65133 SLVSC01 – JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS Table 2. Table of Graphs FIGURE Efficiency vs. Output current Line Regulation Startup Switch pin, inductor current and output waveform Load Transient VPOS = 5 V, VNEG = -5 V IOUT = IPOS + INEG, IPOS = INEG Figure 1 VPOS = 5 V, VIN = 2.9 V to 5.0 V Figure 2 VNEG = -5 V, VIN = 2.9 V to 5.0 V Figure 3 VPOS Boost and VNEG Buck-Boost Figure 4 VPOS Boost, VPOS = 5 V, IOUT = 100 mA Figure 5 VPOS Boost, VPOS = 5 V, IOUT = 250 mA Figure 6 VNEG Buck-Boost, VNEG = -5 V, IOUT = 100 mA Figure 7 VNEG Buck-Boost, VNEG = -5 V, IOUT = 250 mA Figure 8 VIN = 3.7 V, IPOS = 50 mA to 200 mA Figure 9 VIN = 3.7 V, INEG = 50 mA to 200 mA Figure 10 5.20 100 90 80 5.10 VPOS Output Voltage (V) Efficiency - % 70 60 50 40 5.00 30 VIN = 2.9 V 20 4.90 VIN = 3.3 V VIN = 3.7 V 10 IPOS = 50 mA VIN = 4.2 V IPOS = 125 mA VIN = 4.5 V 0 0 50 100 150 200 250 300 350 Total Output Current (mA); IOUT = IPOS + INEG 400 450 500 IPOS = 250 mA 4.80 2.9 3.6 4.3 5.0 VIN Input Voltage (V) Figure 1. EFFICIENCY vs. OUTPUT CURRENT VPOS = 5 V, VNEG = -5 V IOUT = IPOS + INEG, IPOS = INEG Figure 2. VPOS OUTPUT VOLTAGE vs. INPUT VOLTAGE VPOS = 5 V, VIN = 2.9 V to 5.0 V -4.80 EN 5 V/div VNEG Output Voltage (V) -4.90 VPOS 2.5 V/div -5.00 VNEG 2.5 V/div -5.10 INEG = 50 mA INEG = 125 mA INEG = 250 mA -5.20 2.9 3.6 4.3 5.0 IIN 200 mA/div VIN Input Voltage (V) Time = 400 Ps/div Figure 3. VNEG OUTPUT VOLTAGE vs. INPUT VOLTAGE VNEG = -5 V, VIN = 2.9 V to 5.0 V 6 Submit Documentation Feedback Figure 4. START UP VPOS BOOST and VNEG BUCK-BOOST Copyright © 2013, Texas Instruments Incorporated TPS65133 www.ti.com SLVSC01 – JUNE 2013 VPOS 10 mV/div VPOS 10 mV/div VSWP 5 mV/div VSWP 5 mV/div IINDUCTOR 200 mA/div IINDUCTOR 200 mA/div Time = 400 ns/div Figure 5. SWITCH PIN, INDUCTOR CURRENT and OUTPUT VPOS BOOST, VPOS = 5 V, IOUT = 100 mA Time = 400 ns/div Figure 6. SWITCH PIN, INDUCTOR CURRENT and OUTPUT VPOS BOOST, VPOS = 5 V, IOUT = 250 mA VNEG 10 mV/div VNEG 10 mV/div VSWN 5 V/div VSWN 5 V/div IINDUCTOR 200 mA/div IINDUCTOR 200 mA/div Time = 400 ns/div Time = 400 ns/div Figure 7. SWITCH PIN, INDUCTOR CURRENT and OUTPUT VNEG BOOST, VNEG = –5 V, IOUT = 100 mA Figure 8. SWITCH PIN, INDUCTOR CURRENT and OUTPUT VNEG BOOST, VNEG = –5 V, IOUT = 250 mA Figure 9. VPOS LOAD TRANSIENT VIN = 3.7 V, IPOS = 50 mA to 200 mA Figure 10. VNEG LOAD TRANSIENT VIN = 3.7 V, INEG = 50 mA to 200 mA Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS65133 SLVSC01 – JUNE 2013 www.ti.com L1, 4.7μH VIN 2.9V...5V C1 10μF EN C4 100nF TPS65133 PVIN SWP AVIN VPOS VPOS 5V / 250mA C2 10μF PGND AGND VNEG EN VNEG -5V / 250mA C3 10μF SWN L2, 4.7μH Figure 11. Application for Typical Characteristics Table 3. Bill of Materials for Typical Characteristics 8 COMPONENT VALUE PART NUMBER MANUFACTURER C1, C2, C3 10µF GRM219R61A106KE44 Murata L1, L2 4.7µH 1239AS-H-4R7M (DFE 252012C) TOKO Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS65133 www.ti.com SLVSC01 – JUNE 2013 DETAILED DESCRIPTION The TPS65133 integrates a boost converter and an inverting buck-boost converter. The positive output is fixed at 5 V and negative output is fixed at –5 V. ENABLE (EN PIN) The EN pin enables the boost and buck-boost converters. When EN is pulled high the device is enabled and both rails will startup according to the start-up sequence. When EN is pulled low the device is disabled and both outputs are discharged to ground. START-UP AND SHUT-DOWN SEQUENCE The device is enabled by EN pin going high, the boost converter (VPOS) will first start. Typically 2 ms after VPOS is in regulation, the buck-boost converter (VNEG) starts. To reduce the inrush current, the switch current limit during start-up is reduced (soft-start). The start-up times depend on the output capacitances and the load currents. During shut-down (EN = low) the outputs are actively discharged to GND, as long as VIN > 1.5 V (typ). The discharge time depends on the output capacitance and the load current. The VPOS discharge circuit is stronger than the VNEG discharge circuit, that means for the same output capacitance and load VPOS is discharged faster. The start-up and shut-down sequence for the typical application with 10 µF output capacitance is shown in Figure 12. Figure 12. Start-up Sequence INPUT VOLTAGE OPERATING RANGE The TPS65133 is designed to work optimally over an input voltage range of 2.9V to 5V. However, as the input voltage drops below 2.9V and approaches the UVLO falling threshold (typically 2.1V), the device will continue to operate. The device is also able to function as the input voltage approaches the target output voltage of the switching converters; that is to say, as VIN approaches and reaches 5V, the VPOS and VNEG rails will continue to output +5V and -5V. The device is able to operate in a 'down' mode similar to an LDO in this condition as VIN approaches and reaches 5V. OUTPUT DISCHARGE The device actively discharges VPOS and VNEG to GND when the device is disabled (see Figure 12 shaded area). SHORT CIRCUIT PROTECTION The device is protected against short circuits of VPOS and VNEG to GND. Short Before Power-up: When a short-circuit is present before power-up, the output current is limited until the short is removed. Short During Operation: A short-circuit is detected if VPOS falls below 4.1 V for longer than 3 ms or VNEG is pulled above –4.5V longer than 3 ms. In either case, the device goes into shutdown and this state is latched. Input and outputs are disconnected. To resume normal operation, VIN must cycle below UVLO or EN has to toggle from low to high. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS65133 SLVSC01 – JUNE 2013 www.ti.com THERMAL SHUTDOWN A thermal shutdown is implemented to prevent damage because of excessive heat and power dissipation. Once a temperature of typically 135°C is exceeded the device goes into shutdown. To resume normal operation, VIN must cycle below UVLO or EN has to toggle from low to high. L1, 4.7μH VPOS 5V SWP 1 12 PVIN PGND 2 11 AVIN VPOS 3 10 SWN 9 VNEG C2 10μF GND 4 Thermal PAD GND VIN 2.9V...5V C1 10μF C4 100nF L2, 4.7μH VNEG -5V C3 10μF AGND 5 8 GND GND 6 7 EN EN Figure 13. Typical Application Circuit PCB LAYOUT 1. Place the input capacitor on PVIN and the output capacitor on VNEG as close as possible to device. Use short and wide traces to connect the input capacitor on PVIN and the output capacitor on VNEG. 2. Place the output capacitor on VPOS as close as possible to the device. Use short and wide traces to connect the output capacitor on VPOS. 3. Connect the ground of AVIN capacitor with AGND. 4. Connect input ground and output ground on the same board layer, not through via hole. 5. Connect AGND, PGND and GND with exposed thermal pad. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS65133 www.ti.com SLVSC01 – JUNE 2013 Figure 14. TPS65133 EVM Schematic Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS65133 SLVSC01 – JUNE 2013 www.ti.com Figure 15. TPS65133 EVM Layout, Top Layer 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated TPS65133 www.ti.com SLVSC01 – JUNE 2013 Figure 16. TPS65133 EVM Layout, Bottom Layer Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS65133DPDR ACTIVE Package Type Package Pins Package Drawing Qty WSON DPD 12 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-2-260C-1 YEAR (4/5) -40 to 85 SHY (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS65133DPDR Package Package Pins Type Drawing WSON DPD 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65133DPDR WSON DPD 12 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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