ONSEMI NCP5222MNR2G

NCP5222
High Performance
Dual-Channel / Two-Phase
Synchronous Buck
Controller for Notebook
Power System
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MARKING
DIAGRAM
The NCP5222, a fast−transient−response and high−efficiency
dual−channel / two−phase buck controller with built−in gate drivers,
provides multifunctional power solutions for notebook power system.
180° interleaved operation between the two channels / phases has a
capability of reducing cost of the common input capacitors and
improving noise immunity. The interleaved operation also can reduce
cost of the output capacitors with the two−phase configuration. Input
supply voltage feedforward control is employed to deal with wide
input voltage range. On−line programmable and automatic
power−saving control ensures high efficiency over entire load range.
Fast transient response reduces requirement on the output filters. In the
dual−channel operation mode, the two output power rails are regulated
individually. In the two−phase operation mode, the two output power
rails are connected together by an external switch and current−sharing
control is enabled to balance power delivery between phases.
QFN28
CASE 485AR
A
L
Y
W
G
5
4
3
2
1
FB2
COMP2
VIN
COMP1
FB1
ICS1
8
CS2−/
Vo2
CS1−/ 28
Vo1
9
CS2+
CS1+ 27
10 EN2/
SKIP2
NCP5222
11 BST2
AGND
29
EN1/ 26
S KIP1
BST1 25
DH1 24
13 SWN2
SWN1 23
V CC
DRV S /
2CH
V CCP
P GOOD1
P GND1
DL1 22
P GOOD2
14 DL2
15
16
17
18
19
20
21
(Top View)
ORDERING INFORMATION
Device
NCP5222MNR2G
Package
Shipping†
QFN28
(Pb−Free)
4000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• CPU Chipsets Power Supplies
• Notebook Applications
February, 2010 − Rev. 0
6
12 DH2
Typical Applications
© Semiconductor Components Industries, LLC, 2010
7
ICS2
PIN CONNECTIONS
Wide Input Voltage Range: 4.5 V to 27 V
Adjustable Output Voltage Range: 0.8 V to 3.3 V
Option for Dual−Channel and Two−Phase Modes
Fixed Nominal Switching Frequency: 300 kHz
180° Interleaved Operation Between the Two Channels in
Continue−Conduction−Mode (CCM)
Adaptive Power Control
Input Supply Voltage Feedforward Control
Transient−Response−Enhancement (TRE) Control
Resistive or Inductor’s DCR Current Sensing
0.8% Internal 0.8 V Reference
Internal 1 ms Soft−Start
Output Discharge Operation
Built−in Adaptive Gate Drivers
Input Supplies Undervoltage Lockout (UVLO)
Output Overvoltage and Undervoltage Protections
Accurate Over Current Protection
Thermal Shutdown Protection
QFN−28 Package
This is a Pb−Free Device
P GND2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
•
•
•
•
•
N5222
ALYWG
G
1
1
Publication Order Number:
NCP5222/D
Vo1
NCP5222
Vin
CS1− / Vo1
5V
2 FB1
PGO OD1 20
6 FB2
AGND
5 CO MP2
PGOO D1
DRVS / 18
2CH
VCC 17
29
4 VIN
VCCP 19
AGND
NCP5222
3 CO MP1
PGOO D2
14 DL2
13 SWN2
12 DN2
10 EN2/
SKIP2
11
BST2
PGND2 15
EN2/Ski p2
CS2+
CS2− / Vo2
8 CS2−/
Vo2
9 CS2+
PGO OD2 16
7 ICS2
Vin
CS2+
Vo2
CS2− / Vo2
Figure 1. Typical Application Diagram for A Dual−Channel Application
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2
PGND
PGND1 21
1 ICS1
Vi n
DL1 22
SWN1 23
DH1 24
CS1− / Vo1
CS1− / 28
Vo1
CS1+
CS1+ 27
EN1/Skip1
EN1/ 26
SKIP1
25
BST1
CS1+
Vo1
NCP5222
Vin
CS1− / Vo1
5V
2 FB1
PGOO D1 20
AGND
5 CO MP2
PG OO D1
DRVS/ 18
2CH
29
4 VIN
VCCP 19
AGND
NCP5222
3 CO MP1
VCC 17
PGOO D2 16
PG OO D2
14 DL2
12 DH2
11 BST2
10 EN2/
SKIP2
9 CS2+
CS2+
PGND2 15
EN2/Ski p2
8 CS2−/
Vo2
7 ICS2
13 SWN2
6 FB2
CS2− / Vo2
PGND
PGND1 21
1 ICS1
Vi n
DL1 22
SWN1 23
DH1 24
CS1− / Vo1
CS1−/ 28
Vo1
CS1+
27
CS1+
EN1/Skip1
EN1/ 26
SKIP1
25
BST1
CS1+
Vin
CS2+
Vo2
CS2− / Vo2
Figure 2. An Application Diagram for A Two−Phase Application
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3
NCP5222
28
CS1+
CS1−/Vo1
Gi
20
PGOOD1
27
EN1/SKIP1
26
OC1
BST1
DISCHG1
DH_Pre1
DH1
OV1
18
DRVS /
2CH
Driver for
Sharing−FET
SWN1
Share
PWM Control 1
2
3
VCCP
2PH
DL_Pre1
DL1
FB1
P GND1
Skip1
SS1
CLK_H
ICS1
20k
20k
8
I CS2
1.25V
Reference
Generator
Divider & 180°
Phase Shifter
OSC
Digital
Soft−Start
800mV
21
4
SS2
CLK2
POR
VCC
17
CS2+
CS2−/Vo2
Gi
OC2
BST2
DH_Pre2
DH2
OV2
SWN2
CS1−
CS2−
2PH
PGOOD1
Sharing
Control
PWM Control 2
Share
11
12
13
Gate Driver 2
UV2
VCCP
DL_Pre2
PGOOD2
FB2
Skip2
SS2
DL2
P GND2
14
15
10
Figure 3. Functional Block Diagram
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4
PGOOD2
COMP2
EN2/SKIP2
5
22
Thermal
Shut Down
DISCHG2
6
19
SS1
640mV
9
VIN
CLK1
920mV
Gm
7
23
COMP1
30mV
1
24
Gate Driver 1
UV1
Configur ation
Detection
25
16
AGND
29
NCP5222
PIN DESCRIPTION
Pin
No.
Symbol
1
ICS1
Current−Sense Output 1. Output of the current−sense amplifier of channel 1.
2
FB1
Feedback 1. Output voltage feedback of channel 1.
3
COMP1
COMP1. Output of the error amplifier of channel 1.
Descriptions
4
VIN
5
COMP2
Vin. Input supply voltage monitor input.
COMP2. Output of the error amplifier of channel 2.
6
FB2
Feedback 2. Output voltage feedback of channel 2.
7
ICS2
Current−Sense Output 2. Output of the current−sense amplifier of channel 2.
8
CS2−/
Vo2
Current Sense 2−. Inductor current differential sense inverting input of Channel 2. Output Voltage 2. Connection
to output of Channel 2.
9
CS2+
Current Sense 2+. Inductor current differential sense non−inverting input of Channel 2.
10
EN2 /
Skip2
Enable 2. Enable logic input of Channel 2. Skip 2. Power−saving operation (FPWM and Skip) programming pin
of Channel 2.
11
BST2
BOOTSTRAP Connection 2.Channel 2 high−side gate driver input supply, a bootstrap capacitor connection
between SWN2 and this pin.
12
DH2
High−Side Gate Drive 2. Gate driver output of the high−side N−Channel MOSFET for channel 2.
13
SWN2
14
DL2
15
PGND2
16
PGOOD2
Switch Node 2. Switch node between the high−side MOSFET and low−side MOSFET of Channel 2.
Low−Side Gate Drive 2. Gate driver output of the low−side N−Channel MOSFET for channel 2.
Power Ground 2. Ground reference and high−current return path for the low−side gate driver of channel 2.
Power GOOD 2. Power good indicator of the output voltage of channel 2. (Open drained)
17
VCC
18
DRVS /
2CH
VCC. This pin powers the control section of IC.
Gate Driver for Switch. Gate driver output for the external switch in dual−phase configuration. Dual−Channel.
Dual−channel configuration programming pin.
19
VCCP
VCC Power. This pin powers internal gate drivers.
20
PGOOD1
21
PGND1
22
DL1
23
SWN1
24
DH1
High−Side Gate Drive 1. Gate driver output of the high−side N−Channel MOSFET for channel 1.
25
BST1
BOOTSTRAP Connection 1. Channel 1 high−side gate driver input supply, a bootstrap capacitor connection
between SWN1 and this pin.
26
EN1 /
Skip1
Enable 1. Enable logic input of Channel 1. Skip 1. Power−saving operation (FPWM and Skip) programming pin
of Channel 1.
27
CS1+
Current Sense 1+. Inductor current differential sense non−inverting input of Channel 1.
28
CS1−/
Vo1
Current Sense 1−. Inductor current differential sense inverting input of Channel 1. Output Voltage 1. Connection
to output of Channel 1.
29
AGND
Analog Ground. Low noise ground for control section of IC.
Power GOOD 1. Power good indicator of the output voltage of channel 1. (Open drained)
Power Ground 1. Ground reference and high−current return path for the low−side gate driver of channel 1.
Low−Side Gate Drive 1. Gate driver output of the low−side N−Channel MOSFET for channel 1.
Switch Node 1. Switch node between the high−side MOSFET and low−side MOSFET of Channel 1.
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5
NCP5222
MAXIMUM RATINGS
Value
Symbol
MIN
MAX
Unit
VCC, VCCP
−0.3
6.0
V
VBST1 −VSWN1,
VBST2 −VSWN2,
VDH1 −VSWN1,
VDH2 −VSWN2
−0.3
6.0
V
VIN
−0.3
30
V
VSWN1, VSWN2
−0.3,
30
V
Rating
Power Supply Voltages to AGND
High−Side Gate Driver Supplies: BST1 to SWN1, BST2 to SWN2
High−Side Gate Driver Voltages: DH1 to SWN1, DH2 to SWN2
Input Supply Voltage Sense Input to AGND
Switch Nodes
−5(<100 ns)
High−Side Gate Drive Outputs
VDH1, VDH2
−0.3,
−5(<100 ns)
36
V
Low−Side Gate Drive Outputs
VDL1, VDL2
−0.3,
−5(<100 ns)
6.0
V
VFB1, VFB2
−0.3
6.0
V
VCOMP1, VCOMP2
−0.3
6.0
V
VICS1, VICS2
−0.3
6.0
V
Current Sense Input to AGND
VCS1+, VCS1−, VCS2+,
VCS2−
−0.3
6.0
V
Mode Program I/O to PGND1
VDRVS
−0.3
6.0
V
VEN1, VEN2
−0.3
6.0
V
Power Good Output to AGND
VPGOOD1, VPGOOD2
−0.3
6.0
V
PGND1, PGND2 to AGND
VGND
−0.3
0.3
V
Operating Junction Temperature Range
TJ
−40
150
°C
Operating Ambient Temperature Range
TA
−40
85
°C
Storage Temperature Range
TSTG
−55
150
°C
Thermal Characteristics Thermal Resistance Junction to Air (Pad
soldered to PCB)
RqJA
45 (Note 1)
°C/W
Moisture Sensitivity Level
MSL
1
−
Feedback Input to AGND
Error Amplifier Output to AGND
Current Sharing Output to AGND
Enable Input to AGND
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Directly soldered on 4 layer PCB with thermal vias, thermal resistance from junction to ambient with no airflow is around 40~45°C/W (depends
on filled vias or not). Directly soldered on 4 layer PCB without thermal vias, thermal resistance from junction to ambient with no air flow is
around 56°C/W.
2. This device is sensitive to electrostatic discharge. Follow proper handing procedures.
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VIN = 12 V, TA = −40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE
Input Voltage
VIN
4.5
−
27
V
VCC Operating Voltage
VCC
4.5
5.0
5.5
V
VCCP Operating Voltage
VCCP
4.5
5.0
5.5
V
2.5
5
mA
SUPPLY CURRENT
VCC Quiescent Supply Current in
FPWM operation
IVCC_FPWM
EN1 = EN2 = 1.95 V, FB1
and FB2 forced above
regulation point, DH1, DL1,
DH2, and DL2 are open
3. Guaranteed by design, not tested in production.
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NCP5222
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VIN = 12 V, TA = −40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
VCC Quiescent Supply Current in
power−saving operation
IVCC_PS
EN1 = EN2 = 5 V, FB1 and
FB2 forced above regulation
point, DH1, DL1, DH2, and
DL2 are open
VCC Shutdown Current
IVCC_SD
EN1 = EN2 = 0 V
Min
Typ
Max
Unit
2.5
5
mA
1
mA
SUPPLY CURRENT
VCCP Quiescent Supply Current in
FPWM operation
IVCCP_FPWM
EN1 = EN2 = 1.95 V, FB1
and FB2 forced above
regulation point, DH1, DL1,
DH2, and DL2 are open
0.3
mA
VCCP Quiescent Supply Current in
power−saving operation
IVCCP_PS
EN1 = EN2 = 5 V, FB1 and
FB2 forced above regulation
point, DH1, DL1, DH2, and
DL2 are open
0.3
mA
VCCP Shutdown Current
IVCCP_SD
EN1 = EN2 = 0 V
1
mA
BST Quiescent Supply Current in
FPWM operation
IBST_FPWM
EN1 = EN2 = 1.95 V, FB1
and FB2 forced above
regulation point, DH1, DL1,
DH2, and DL2 are open
0.3
mA
BST Quiescent Supply Current in
power−saving operation
IBST_PS
EN1 = EN2 = 5 V, FB1 and
FB2 forced above regulation
point, DH1, DL1, DH2, and
DL2 are open
0.3
mA
BST Shutdown Current
IBST_SD
EN1 = EN2 = 0 V, BST1 =
BST2 = 5 V, SWN1 = SWN2
=0V
1
mA
IVIN
EN1 = EN2 = 5 V
35
mA
IVIN_SD
EN1 = EN2 = 0 V
1
mA
VCC Start Threshold
VCCUV+
VCC and VCCP are connected
to the same voltage source
VCC UVLO Hysteresis
VIN Start Threshold
VIN UVLO Hysteresis
VINHYS
VIN Supply Current (Sink)
VIN Shutdown Current
VOLTAGE MONITOR
Power Good High Threshold
4.05
4.25
4.48
V
VCCHYS
−400
−300
−200
mV
VINUV+
3.2
3.6
4.0
V
−700
−500
−300
mV
105
110
115
%
VPGH
PGOOD goes high from
higher Vo
Hystersis
Power Good Low Threshold
VPGL
PGOOD goes high from
lower Vo
5
85
Hystersis
90
Td_PGH
150
Power Good Low Delay
Td_PGL
1.5
Output Overvoltage Trip Threshold
FBOVPth
110
Hystersis
Output Overvoltage Fault Latch Delay
FBUVPth
Output Undervoltage Protection Fault
Latch Blanking Time
UVPTblk
115
ms
ms
120
1.5
FB compared to 0.8 V
75
Hystersis
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7
%
80
ms
85
%
−
ms
10
−
3. Guaranteed by design, not tested in production.
%
−5
OVPTd
Output Undervoltage Trip Threshold
95
−5
Power Good High Delay
FB compared to 0.8 V
%
27
NCP5222
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VIN = 12 V, TA = −40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
TA = 25°C
0.794
0.8
0.806
V
TA = −40°C to 85°C
0.792
INTERNAL REFERENCE
VFB Regulation Voltage
VFB1, VFB2
0.808
SWITCHING FREQUENCY
Normal Operation Frequency
FSW
TA = 25°C
276
TA = −40°C to 85°C
270
300
324
kHz
330
INTERNAL SOFT−START
TSS
Soft−Start Time
0.8
1
1.2
ms
SWITCHING REGULATOR
Ramp Offset Voltage
Ramp Amplitude Voltage
Vramp_offset
Vramp_V
(Note 3)
0.4
V
VIN = 5 V (Note 3)
1.25
V
VIN = 12 V (Note 3)
3
Minimum Ton
Ton_min
70
ns
Minimum Toff
Toff_min
360
ns
VOLTAGE ERROR AMPLIFIER
GAIN_VEA
(Note 3)
88
dB
Unity Gain Bandwidth
Ft_VEA
(Note 3)
15
MHz
Slew Rate
SR_VEA
COMP to GND 100 pF
(Note 3)
2.5
V/ms
Output Voltage Swing
Vmax_EA
Isource_EA = 2 mA
Vmin_EA
Isink_EA = 2 mA
DC Gain
3.3
3.6
0.1
V
0.3
V
3.5
V
DIFFERENTIAL CURRENT SENSE AMPLIFIER
CS+ and CS−Common−mode Input
Signal Range
VCS to ICS Gain
Internal Resistance from ICS to 1.25 V
Bias
ICS Voltage Dynamic Range
VCSCOM_MAX
ICS_GAIN
(ICS/VCS)
Refer to AGND
2PH Mode, VCS = V(CS+)
−V(CS−) = 4 mV
RICS
VICS_Dyn
2PH Mode (Note 3)
[V(ICS2)−V(ICS1)] to IFB2 Gain
IFB2_GAIN
(IFB2/(V(ICS2)−
V(ICS1)))
2PH Mode
Current−Sharing Gain
ISH_GAIN
(IFB2/(VCS2−V
CS1))
2PH Mode (IFB2/((V(CS2+)
−V(CS2−))−(V(CS1+)
−V(CS1−)))
IFB2_offset
2PH Mode, VCS1 = VCS2 =
0V
IFB2 Offset Current
IFB2 Current Dynamic Range in 2PH
Mode
0.5
mA/mV
20
kW
0.75 ~
1.75
V
0.1
mA/mV
1
mA/mV
−0.5
0.5
mA
2PH Mode
−9
9
mA
V(CS+) – V(CS−), Vo = 0.8 V
to 3.3 V
27
30
33
mV
−
107
−
ms
OVERCURRENT PROTECTION
OCP Threshold
VTH_OC
OCP Fault Latch Blanking Time
OCPTblk
SHARING SWITCH GATE DRIVE
IDRVS
1
mA
Pull−HIGH Resistance
RH_DRVS
20
W
Pull−LOW Resistance
RL_DRVS
10
W
Soft−On Source Current
3. Guaranteed by design, not tested in production.
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NCP5222
ELECTRICAL CHARACTERISTICS (VCC = 5 V, VIN = 12 V, TA = −40°C to 85°C, unless other noted)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
CONFIGURATION DETECTION
Configuration Detection Time
Pull−LOW Resistance in Detection
Detection Threshold
TCD
53
ms
RL_CD
2
kW
0.5
V
VCD
VCCP pin to DRVS/2CH pin
GATE DRIVER
DH Pull−HIGH Resistance
RH_DH1,
RH_DH2
2.5
5
W
DH Pull−LOW Resistance
RL_DH1,
RL_DH2
1.5
2.5
W
DL Pull−HIGH Resistance
RH_DL1,
RH_DL2
2
3
W
DL Pull−LOW Resistance
RL_DL1,
RL_DL2
0.75
1.5
W
Dead Time
TLH
DL−off to DH−on (see
Figure 4)
10
25
40
ns
THL
DH−off to DL−on (see
Figure 4)
10
25
40
ns
CONTROL LOGIC
EN Logic Input Voltage Threshold for
Disable
VEN_Disable
EN Logic Input Voltage Threshold for
FPWM
VEN_FPWM
EN Logic Input Voltage Threshold for
Skip
VEN_SKIP
EN Source Current
EN goes low
0.7
1.0
1.3
V
Hysteresis
150
200
250
mV
1.7
1.95
2.25
V
EN goes high
2.4
2.65
2.9
V
Hysteresis
100
175
250
mV
IEN_SOURCE
EN = 0 V (Note 3)
0.1
mA
EN Sink Current
IEN_SINK
EN = 5 V (Note 3)
0.1
mA
PGOOD Pin ON Resistance
PGOOD_R
I_PGOOD = 5 mA
PGOOD Pin OFF Current
PGOOD_LK
1
mA
35
W
70
W
OUTPUT DISCHARGE MODE
Output Discharge On−Resistance
Rdischarge
EN = 0 V, Vout = 0.5 V
25
Shutdown Threshold (Note 3)
150
°C
Hysteresis (Note 3)
−25
°C
THERMAL SHUTDOWN
Thermal Shutdown
Tsd
3. Guaranteed by design, not tested in production.
DH−SWN
1V
TLH
THL
DL−PGND
1V
Figure 4. Dead Time between High−Side Gate Drive and Low−Side Gate Drive
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NCP5222
Dual−Channel Mode or Two−Phase Mode
The NCP5222 can be externally configured to be working
in dual−channel operation mode or two−phase operation
mode. In the dual−channel operation mode, the two output
power rails are regulated individually. In the two−phase
operation mode, the two output power rails are connected
together by an external switch and current−sharing control
is enabled to balance power delivery between phases.
Figure 5 shows two typical external configurations. In
Figure 5(a), the controller is configured to operate in the
dual−channel mode by connecting the pin DRVS with the
pin VCCP. In Figure 5(b), the controller is configured to
operate in the two−phase mode. In this mode, an external
MOSFET SSH is employed to connect the two output power
rails together, and the pin DRVS of the NCP5222 provides
driving signal to SSH. Two filter capacitors CCS1 and
CICS2 are connected with two current−sense output pins
ICS1 and ICS2, respectively. A typical timing diagram is
shown in Figure 6.
General
The NCP5222, a fast−transient−response and
high−efficiency dual−channel / two−phase buck controller
with builtin gate drivers, provides multifunctional power
solutions for notebook power system. 180° interleaved
operation between the two channels / phases has a capability
of reducing cost of the common input capacitors and
improving noise immunity. The interleaved operation also
can reduce cost of the output capacitors with the two−phase
configuration. Input supply voltage feedforward control is
employed to deal with wide input voltage range. On−line
programmable and automatic power−saving control ensures
high efficiency over entire load range. Fast transient
response reduces requirement on the output filters. In the
dual−channel operation mode, the two output power rails are
regulated individually. In the two−phase operation mode,
the two output power rails are connected together by an
external switch and current−sharing control is enabled to
balance power delivery between phases.
7
DRVS/
2 CH
VCCP
VCCP
NCP5222
NCP5222
DRVS/
2CH
1
ICS1
1
ICS2
I CS2
7
C I CS1
I CS1
C ICS2
18 19
18 19
Vo2
S SH
Vo1
S SH
( a ) Dual−C hannel
( b ) Two−Phas e
Figure 5. Mode Configurations
Mode Detection
system goes to the two−phase mode and the DRVS pin is
pulled down to PGND1 by an internal 10 W FET.
In the initial stage of the IC powering up, there is mode
detection period to read the external setup just after VIN and
VCC are both ready and at least one of ENs is enabled. In
Figure 6, VIN and VCC are powered up first. At 3.5 us after
EN2 goes high, a 53 ms mode detection period starts. The
DRVS pin is pulled down by an internal 2 kW. At the end of
the mode detection, if the DRVS is higher than VCCP − 0.5 V
the system goes to the dual−channel mode and leaves DRVS
high impedance. If the DRVS is lower than VCCP − 0.5 V, the
DRVS Softstart in Two−Phase Mode
In the two−phase mode, the DRVS softstart begins after
the both PGOOD1 and PGOOD2 become valid. During the
DRVS softstart, 1 mA current is sourced out from the DRVS
pin and thus voltage in DRVS is ramping up. The DRVS
soft−start is complete after the DRVS voltage is higher than
VCCP − 0.2 V, and then the DRVS pin is pulled up to VCCP
by an internal 20 W FET.
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NCP5222
VIN
3 .6V
VCC
4.2 5V
EN1
EN2
3.5us
53us
0.2V
0 .5V
DRVS
150us
PGOOD1
150us
PGOOD2
57us
1ms
260us
Vo1
67us
1ms
260 us
Vo2
Mode detection
complete.
Ch2 r amping up
complet e.
PGOOD2
vali d.
Ch1 sof tst art
begins.
System and Ch2 reset complete Ch2 i n
EN1 goes hi gh
EN2 goes high and
regul ati on. and Ch1 reset.
mode detection starts. and Ch2 soft start begins.
Ch1 i n
regul ation.
Ch1 rampi ng up
complet e.
DRVS soft start
complet e.
PGOOD1 valid and
Ch1 power down.
DRVS soft start begins.
Ch2 power down.
Figure 6. Timing Diagram in Two−Phase Mode
Control Logic
The NCP5222 monitors VCC with undervoltage lockout
(UVLO) function. If VCC is in normal operation range, the
converter has a soft−start after EN signal goes high. The
internal digital soft−start time is fixed to 1 ms. The two
channels share one DAC ramping−up circuit. If the two ENs
become high at the same time (within 5 ms), the two channels
start soft−start together; If one channel’s EN comes when the
other channel is powering up, the channel starts powering up
after the other channel completes soft start. If one channel’s
EN comes when the other channel is in any fault condition,
the channel does not start powering up until the fault is
cleared. The NCP5222 has output discharge operation
through one internal 20 W MOSFET per channel connected
from CS−/Vo pin to PGND pin, when EN is low or the
channel is under any fault condition.
differential amplifier in each channel allows low−resistance
current−sense resistor or low−DCR inductor to be used to
minimize power dissipation. For lossless inductor current
sensing as shown in Figure 7, the sensing RC network
should satisfy:
R CS1 @ R CS2
L
+
@ C CS + k CS @ R CS1 @ C CS (eq. 1)
R CS1 ) R CS2
DCR
where the dividing−down ratio kCS is
k CS +
R CS2
R CS1 ) R CS2
(eq. 2)
DCR is a DC resistance of an inductor, and normally CCS
is selected to be around 0.1 mF. The current−sense input
voltage across CS+ and CS− is
V CS + k CS @ I L @ DCR
(eq. 3)
If there is a need to compensate measurement error caused
by temperature, an additional resistance network including
Current−Sense Network
In the NCP5222, the output current of each channel is
sensed differentially. A high gain and low offset−voltage
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NCP5222
a negative−temperature−coefficient (NTC) thermistor may
be connected with CCS in parallel.
CLK
FB
R
Ramp
L
Rcs1
DCR
Ccs
Vref
CS+
Rcs2
1
OC
CS−
S
Error
Amplifier
Q
PWM
_
Q
PWM
Comparator
Figure 8. PWM Output Regulation
30mV
Output Regulation in Dual−Channel Mode
In dual−channel operation mode, the two channels
regulate their output voltage individually. As shown in
Figure 9, the output voltage is programmed by external
feedback resistors.
Figure 7. Current Sensing Network and Overcurrent
Protection
ǒ
Output Regulation
As shown in Figure 8, with a high gain error amplifier and
an accurate internal reference voltage, the NCP5222
regulates average DC value of the output voltage to a design
target by error integration function. The output has good
accuracy over full−range operation conditions and external
component variations.
Vo + 1 )
Ǔ@V
R1
R4
ref
(eq. 4)
where Vref is an internal 0.8 V reference voltage.
R1
FB
COMP
R4
PWM1
SWN
L
Vo
C
0.8V
Figure 9. PWM Output Regulation in Dual−Channel Mode
Output Regulation in Two−Phase Mode
I Share +
Figure 10 shows a block diagram for explanation of the
output regulation in the two−phase mode. Under the
two−phase configuration, a MOSFET SSH called sharing
switch is employed to connect two power rails VO1 and VO2.
V O2 * V O1
R ON_S
where RON_S is on resistance of SSH.
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(eq. 5)
NCP5222
R11
FB1
COMP1
R14
PWM1
Rcs11
0.8V
IL1
L1
SWN1
Io1
Vo1
Ccs1
C1
Rcs12
CS1+
ICS1
IFB2
Gi
ISH
CS1−
Rics1
20k
1.25V
Rics2
20k
CS2−
Gm
ICS2
Gi
Ssh
CS2+
Rcs22
0.8V
Rcs21
COMP2
R24
FB2
PWM2
L2
SWN2
Ccs2
C2
Vo2
IL2
Io2
R21
Figure 10. PWM Output Regulation in Two−Phase Mode
In the two−phase operation, the phase 1 has the same
output regulation control as what is in the dual−channel
operation. The output voltage is
ǒ
V O1 + 1 )
Ǔ@V
R 11
R 14
ref1
ǒ
+ 1)
Ǔ @ 0.8
R 11
R 14
where
V ICS1 + G ICS1 @ R ICS1 @ V CS1 ) V ICS_Offset
+ 10 @ V CS1 ) 1.25
(eq. 6)
V ICS2 + G ICS2 @ R ICS2 @ V CS2 ) V ICS_Offset
+ 10 @ V CS2 ) 1.25
However, in order to achieve current−sharing function,
the output voltage in phase 2 is adjusted to be higher or lower
than VO1 to balance the power delivery in the two phases, by
means of an injection current IFB2 into the phase 2 error
amplifier’s non−inverting node. Thus output voltage of the
phase 2 is
ǒ
R 21
ǒ
R 21
V O2 + 1 )
+ 1)
Ǔ@V
R 24
Ǔ @ 0.8 * I
(eq. 11)
V CS2 + k CS2 @ I L2 @ DCR 2
(eq. 12)
k CS1 +
k CS2 +
FB2 @ R 21
R CS12
R CS11 ) R CS12
R CS22
R CS21 ) R CS22
(eq. 13)
(eq. 14)
Based on understanding of the power stage connection,
the current distribution in the two phases can be calculated
by
The injection current IFB2 is proportional to the difference
between the two current−sense output signals VICS2 and
VICS1, that is
I FB2 + G IFB2 @ ǒV ICS2 * V ICS1Ǔ
+ 1x10 −3 @ ǒV ICS2 * V ICS1Ǔ
V CS1 + k CS1 @ I L1 @ DCR 1
(eq. 7)
+ 1x10 −4 @ ǒV ICS2 * V ICS1Ǔ
(eq. 10)
and
ref2 * I FB2 @ R 21
R 24
(eq. 9)
I L1 + I O1 * I Share
(eq. 15)
I L2 + I O2 * I Share
(eq. 16)
and
(eq. 8)
+ 1x10 −3 @ ǒk CS2 @ DCR 2 @ I L2 * k CS1 @ DCR 1 @ I L1Ǔ
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NCP5222
Where IO1 is the loading current in the power rail VO1, and
IO2 is the loading current in the power rail VO2. Using of
Equations 5, 6, 7, 8, 15, and 16 gives:
I FB2 + k IL2_IFB2 @ I O2 * k IL1_IFB2 @ I O1 ) ǒk IL1_IFB2 ) k IL2_IFB2Ǔ
ǒ1 ) Ǔ @ V
R
R
@
21
24
ref2 *
ǒ1 ) Ǔ @ V
R
11
R
14
ref1 ) R 21 @
ǒkIL1_IFB2 @ IO1 * kIL2_IFB2 @ IO2Ǔ
(eq. 17)
R ON_S ) R 21 @ ǒk IL1_IFB2 ) k IL2_IFB2Ǔ
continuous−conduction mode (CCM). To reduce the
common input ripple and capacitors, the two channels /
phases operate 180° interleaved in CCM. To speed up
transient response and increase system sampling rate, an
internal 1.2 MHz high−frequency oscillator is employed. A
digital circuitry divides down the high−frequency clock
CLK_H and generates two interleaved 300 kHz clocks
(CLK1 and CLK2), which are delivered to the two PWM
control blocks as normal operation clocks.
where
k IL1_IFB2 + G IFB2 @ G ICS1 @ R ICS1 @ k CS1 @ DCR 1
R CS12
(eq. 18)
+ 1x10 −3 @
@ DCR 1
R CS11 ) R CS12
k IL2_IFB2 + G IFB2 @ G ICS2 @ R ICS2 @ k CS2 @ DCR 2
+ 1x10 −3 @
R CS22
R CS21 ) R CS22
@ DCR 2
(eq. 19)
To maintain the output voltage VO2 of the phase 2 in
certain regulation window in case of any fault or non−ideal
conditions, such as the sharing switch is broken or has too
high on resistance, the injection current IFB2 has magnitude
limits as $9 mA. As a result, VO2 has a limited adjustable
range as
ǒ1 ) RR Ǔ @ 0.8 * 8 @ 10 @ R v V
R
Ǔ @ 0.8 ) 9 @ 10 @ R
v ǒ1 )
R
21
−6
21
24
21
24
−6
Forced−PWM Operation (FPWM Mode)
If the voltage level at the EN pin is a medium level around
1.95 V, the corresponding channel of the NCP5222 works
under forced−PWM mode with fixed 300 kHz switching
frequency. In this mode, the low−side gate−drive signal is
forced to be the complement of the high−side gate−drive
signal and thus the converter always operates in CCM. This
mode allows reverse inductor current, in such a way that it
provides more accurate voltage regulation and fast transient
response. During soft−start operation, the NCP5222
automatically runs in FPWM mode regardless of the EN
pin’s setting to guarantee smooth powering up.
O2
(eq. 20)
21
In an Ideal case that the sharing switch has very small on
resistance and the two phases matches perfectly, the
current−sense input voltages in the two phases are equal, that
is
I L1 @ DCR 1 @ k CS1 + I L2 @ DCR 2 @ k CS2
Pulse−Skipping Operation (Skip Mode)
Skip mode is enabled by pulling EN pin higher than
2.65 V, and then the corresponding channel works in
pulse−skipping enabled operation. In medium and high load
range, the converter still runs in CCM, and the switching
frequency is fixed to 300 kHz. If the both channels run in
CCM, they operate interleaved. In light load range, the
converter automatically enters diode emulation and skip
mode to maintain high efficiency. The PWM on−time in
discontinuous−conduction mode (DCM) is adaptively
controlled to be similar to the PWM on−time in CCM.
(eq. 21)
Using of Equations 15, 16, and 21 gives
I L1 +
I L2 +
I Share +
DCR 2 @ k CS2 @ ǒI O1 ) I O2Ǔ
DCR 1 @ k CS1 ) DCR 2 @ k CS2
DCR 1 @ k CS1 @ ǒI O1 ) I O2Ǔ
DCR 1 @ k CS1 ) DCR 2 @ k CS2
DCR 1 @ k CS1 @ I O1 * DCR 2 @ k CS2 @ I O2
DCR 1 @ k CS1 ) DCR 2 @ k CS2
(eq. 22)
(eq. 23)
Transient Response Enhancement (TRE)
For a conventional trailing−edge PWM controller in
CCM, the minimum response delay time is one switching
period in the worst case. To further improve transient
response, a transient response enhancement circuitry is
introduced to the NCP5222. The controller continuously
monitors the COMP signal, which is the output voltage of
the error amplifier, to detect load transient events. A desired
stable close−loop system with the NCP5222 has a ripple
voltage in the COMP signal, which peak−to−peak value is
normally in a range from 200 mV to 500 mV. There is a
threshold voltage in each channel made in a way that a
filtered COMP signal pluses an offset voltage. Once a large
(eq. 24)
PWM Operation
There are two available operation modes, which are
forced PWM mode and power−saving skip mode, selected
by two different voltage levels at EN pin for each channel,
respectively. The operation modes can be external preset or
on−line programmed.
The two channels / phases controlled by the NCP5222
share one input power rail. The both channels / phases
operate at a fixed 300 kHz normal switching frequency in
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NCP5222
load transient occurs, the COMP signal is possible to exceed
the threshold and then TRE is tripped in a short period,
which is typically around one normal switching cycle. In this
short period, the controller runs at higher frequency and
therefore has faster response. After that the controller comes
back to normal operation.
so that the overcurrent threshold IOC is the maximum
loading current IOmax per channel.
I OC2 + I O2max )
(eq. 29)
DCR 1 @ k CS1
DCR 1 @ k CS1 ) DCR 2 @ k CS2
(eq. 30)
(eq. 31)
Use of Equations 29, 30, and 31 leads to:
ǒ
ǒ
I OC1 + I O1max @ 1 )
I OC2 + I O2max @ 1 )
I O2max
I O1max ) I O2max
I O1max
I O1max ) I O2max
Ǔ
Ǔ
(eq. 32)
(eq. 33)
Output Overvoltage Protection (OVP)
An OVP circuit monitors the feedback voltages to prevent
loads from over voltage. OVP limit is typically 115% of the
nominal output voltage level, and the hysteresis of the OV
detection comparator is 5% of the nominal output voltage.
If the OV event lasts less than 1.5 ms, the controller remains
normal operation when the output of the OV comparator is
released, otherwise an OV fault is latched after 1.5 ms. After
the fault is latched, the high−side MOSFET is latched off and
the low−side MOSFET will be on and off responding to the
output of the OV detection comparator. The fault remains set
until the system has shutdown and re−applied VCC and/or
the enable signal EN has toggled states.
(eq. 25)
Output Undervoltage Protection (UVP)
The DC current limit is
2 @ V IN @ f SW @ L
DCR 1 @ k CS1 ) DCR 2 @ k CS2
I OC1 @ DCR 1 @ k CS1 + I OC2 @ DCR 2 @ k CS2 + V TH_OC
The NCP5222 protects converter if overcurrent occurs.
The current through each channel is continuously monitored
with differential current sense. If inductor current exceeds
the current threshold, the high−side gate drive will be turned
off cycle−by−cycle. In the meanwhile, an internal OC fault
timer will be triggered. If the fault still exists after about
53 ms, the corresponding channel latches off, both the
high−side MOSFET and the low−side MOSFET are turned
off. The fault remains set until the system has shutdown and
re−applied VCC and/or the enable signal EN has toggled
states.
Current limit threshold VTH_OC between CS+ and CS−is
internally fixed to 30 mV. The current limit can be
programmed by the inductor’s DCR and the current−sense
resistor divider with RCS1 and RCS2. The inductor peak
current limit is
V O @ ǒV IN * V OǓ
DCR 2 @ k CS2
The both phases also has the same internal overcurrent
current−sense threshold VTH_OC = 30 mV, that means
Output Overcurrent Protection (OCP)
I OC + I OC(Peak) *
(eq. 28)
and
The NCP5222 provides UVLO functions for both input
power supplies (VIN and VCC) of the power stage and
controller itself. The two UVLO functions make it possible
to have flexible power sequence between VIN and VCC for
the power systems. The start threshold of VIN is 3.6 V, and
the starting threshold of VCC is 4.25 V.
k CS @ DCR
I OC2 + I O2max
I OC1 + I O1max )
Input Power Supply Undervoltage Lock Out (UVLO)
V TH_OC
(eq. 27)
In two−phase operation mode, to make sure the OCP is not
triggered in the normal operation, the worst case need to be
considered, in which the maximum load step in one power
rail comes just after the two phases are sharing the maximum
load from the other power rail. In this case, the two
overcurrent thresholds need to be set as
Protection Funtions
The NCP5222 provides comprehensive protection
functions for the power system, which include input power
supply undervoltage lock out, output overcurrent protection,
output overvoltage protection, output undervoltage
protection, and thermal shutdown protection. The priority of
the protections from high to low as: 1. Thermal protection
and input power supply undervoltage lockout; 2. Output
overvoltage protection; 3. Output overcurrent protection
and output undervoltage protection.
I OC(Peak) +
I OC1 + I O1max
A UVP circuit monitors the feedback voltages to detect
undervoltage. UVP limit is typically 80% of the nominal
output voltage level. If the output voltage is below this
threshold, a UV fault is set. If an OV protection is set before,
the UV fault will be masked. If no OV protection set, an
internal fault timer will be triggered. If the fault still exists
after about 27 ms, the corresponding channel is latches off,
both the high−side MOSFET and the low−side MOSFET are
(eq. 26)
where VIN is input supply voltage of the power stage, and
fSW is 300 kHz normal switching frequency.
In the dual−channel mode, the steady−state inductor DC
current is equal to output loading current IOmax per channel,
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NCP5222
power delivery between the two phases. The smaller RDS(on)
of the sharing switch (Ron_ssh), the better the current balance
and the smaller output voltage deviation in VO2. Actually,
the current through the sharing switch can be calculated by
Issh = (VO2 − VO1) / Ron_effective, in which Ron_effective =
Ron_ssh + Rpcb, and Rpcb is the copper resistance between the
two output sensing points. So that too large Rpcb effectively
wastes RDS(on) of the sharing switch, and thus reduces the
power sharing capability and enlarges VO2 deviation.
In a real application, to make sure the CH1 has perfect
voltage regulation, the VO1 sensing point and AGND can be
designed like remote sensing. In the meantime, to fully use
the sharing switch for the current sharing operation and
reduce VO2 deviation, the distance between the two sensing
points VO1 and VO2 should be arranged to be as close as
possible.
turned off. The fault remains set until the system has
shutdown and re−applied VCC and/or the enable signal EN
has toggled states.
Thermal Protection
The NCP5222 has a thermal shutdown protection to
protect the device itself from overheating when the die
temperature exceeds 150°C. After the thermal protection is
triggered, the fault state can be ended by re−applying VCC
or EN when the die temperature drops down below 125°C.
Layout Guidelines
Figures 11 and 12 show exemplary layout of the power
stage components for dual−channel configuration and
two−phase configuration, respectively.
In the two−phase mode, after the sharing switch is turned
on, the voltage difference across the sharing−switch will
cause a current flow through it, which is used to balance
Figure 11. Layout Guidelines in Dual−Channel Mode
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NCP5222
Figure 12. Layout Guidelines in Two−Phase Mode
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NCP5222
TYPICAL OPERATING CHARACTERISTICS
330
0.808
FSW, SWITCHING FREQUENCY
(kHz)
VFB, FB VOLTAGE (V)
0.806
0.804
0.802
0.8
0.798
0.796
0.794
0.792
−40
−20
0
20
40
60
80
100
120
300
290
280
270
−40
−20
0
20
40
60
80
100
TA, AMBIENT TEMPERATURE (°C)
Figure 13. Reference Voltage VFB vs. Ambient
Temperature
Figure 14. Switching Frequency vs. Ambient
Temperature
120
3
32
IVCC_FPWM, VCC QUIESCENT
CURRENT (mA)
VTH_OC, OCP THRESHOLD (mV)
310
TA, AMBIENT TEMPERATURE (°C)
33
31
30
29
28
27
−40
−20
0
20
40
60
80
100
120
2.8
2.6
2.4
2.2
2
−40
0
20
40
60
80
100
120
TA, AMBIENT TEMPERATURE (°C)
Figure 15. OCP Threshold vs. Ambient
Temperature
Figure 16. VCC Quiescent Current vs. Ambient
Temperature in FPWM Mode
3
1
2.8
0.8
2.6
2.4
2.2
2
−40
−20
TA, AMBIENT TEMPERATURE (°C)
IVCC_SD, VCC SHUTDOWN
CURRENT (mA)
IVCC_PS, VCC QUIESCENT CURRENT
(mA)
320
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
100
120
0.6
0.4
0.2
0
−40
Figure 17. VCC Quiescent Current vs. Ambient
Temperature in Skip Mode
−20
0
20
40
60
80
100
TA, AMBIENT TEMPERATURE (°C)
120
Figure 18. VCC Shutdown Current vs. Ambient
Temperature
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NCP5222
TYPICAL OPERATING CHARACTERISTICS
4.5
VCCHYS, VCC UVLO HYSTERESIS
(mV)
VCCUV+, VCC START THRESHOLD
(V)
−200
4.4
4.3
4.2
4.1
4
−40
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
100
−240
−280
−320
−360
−400
−40
120
Figure 19. VCC Start Threshold VCCUV+ vs.
Ambient Temperature
VINHYS, VIN UVLO HYSTERESIS (mV)
VINUV+, VIN START THRESHOLD (V)
120
−300
3.8
3.6
3.4
3.2
3
−40
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
100
120
−380
−460
−540
−620
−700
−40
Figure 21. VIN Start Threshold VINUV+ vs.
Ambient Temperature
−20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
100
120
Figure 22. VIN UVLO Hysteresis VINHYS vs.
Ambient Temperature
350
302
fSW, SWITCHING FREQUENCY (kHz)
fSW, SWITCHING FREQUENCY (kHz)
0
20
40
60
80
100
TA, AMBIENT TEMPERATURE (°C)
Figure 20. VCC UVLO Hysteresis VCCHYS vs.
Ambient Temperature
4
300
250
VIN = 20 V
200
VIN = 12 V
150
VIN = 5 V
100
50
0
−20
0
4
8
12
IO, OUTPUT CURRENT (A)
16
20
301
300
VIN = 12 V
299
VIN = 5 V
298
VIN = 20 V
297
296
0
Figure 23. Switching Frequency vs. Output
Current in Skip Mode
4
8
12
16
IO, OUTPUT CURRENT (A)
Figure 24. Switching Frequency vs. Output
Current in FPWM Mode
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20
NCP5222
1.055
1.055
1.054
1.054
1.053
VIN = 5 V
VOUT, OUTPUT VOLTAGE (V)
VOUT, OUTPUT VOLTAGE (V)
TYPICAL OPERATING CHARACTERISTICS
VIN = 20 V
1.052
VIN = 12 V
1.051
1.05
1.049
0.1
1
10
100
VIN = 5 V
1.052
1.051
VIN = 12 V
VIN = 20 V
1.05
1.049
0
4
8
12
16
IO, OUTPUT CURRENT (A)
IO, OUTPUT CURRENT (A)
Figure 25. Output Voltage vs. Output Current
in Skip Mode
Figure 26. Output Voltage vs. Output Current
in FPWM Mode
100
90
70
VIN = 12 V
VIN = 20 V
EFFICIENCY (%)
80
60
50
40
30
20
0.1
20
100
VIN = 5 V
90
EFFICIENCY (%)
1.053
80
VIN = 5 V
VIN = 12 V
70
60
VIN = 20 V
50
40
30
1
10
IO, OUTPUT CURRENT (A)
100
20
0.1
Figure 27. Efficiency vs. Output Current in
Skip Mode
1
10
IO, OUTPUT CURRENT (A)
Figure 28. Efficiency vs. Output Current in
FPWM Mode
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10
NCP5222
TYPICAL OPERATING CHARACTERISTICS
Figure 29. Input Voltage Ripple (VIN = 12 V, CIN =
10 mF * 4, VO1 = 1.05 V, IO1 = 10 A, L1 = 0.56 mH, CO1
= 470 mF * 2, VO2 = 1.05 V, IO2 = 10 A, L2 = 0.56 mH,
CO2 = 470 mF * 2, Dual−Channel Operation)
Figure 30. Output Voltage Ripple (VIN = 12 V, VO1 =
1.05 V, IO1 = 10 A, L1 = 0.56 mH, CO1 = 470 mF * 2,
VO2 = 1.05 V, IO2 = 10 A, L2 = 0.56 mH, CO2 = 470 mF
* 2, Dual−Channel Operation)
Figure 31. Powerup with Two ENs Together (VIN =
12 V, VO1 = 1.05 V, IO1 = 0 A, VO2 = 1.05 V, IO2 = 0 A,
Dual−Channel Operation)
Figure 32. Powerup with EN2 Comes before CH1
Completes Soft−Start (VIN = 12 V, VO1 = 1.05 V, IO1
= 0 A, VO1 = 1.05 V, IO2 = 0 A, Dual−Channel
Operation)
Figure 33. Powerup with EN2 Comes after CH1
Completes Soft−Start (VIN = 12 V, VO1 = 1.05 V, IO1
= 0 A, VO2 = 1.05 V, IO2 = 0 A, Dual−Channel
Operation)
Figure 34. Powerdown and Soft−Stop (VIN = 12 V,
VO1 = 1.05 V, IO1 = 0 A, VO2 = 1.05 V, IO2 = 0 A,
Dual−Channel Operation)
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NCP5222
TYPICAL OPERATING CHARACTERISTICS
Figure 35. Powerup Operation without Biased
Output (VIN = 12 V, VO = 1.05 V, IO = 0 A, Skip
Mode)
Figure 36. Powerup Operation with Biased Output
(VIN = 12 V, VO = 1.05 V, IO = 0 A, Skip Mode)
Figure 37. Power−Down Operation (VIN = 12 V, VO
= 1.05 V, IO = 0 A, Skip Mode)
Figure 38. On−Line Mode Transition (VIN = 12 V, VO
= 1.05 V, IO = 0.5 A, FPWM − Skip − FPWM Mode)
Figure 39. Load Transient Response in Skip Mode
(VIN = 12 V, VO = 1.05 V, IO = 0.1 A to 10 A to 0.1 A,
L = 0.56 mH, CO = 470 mF * 2)
Figure 40. Load Transient Response in FPWM
Mode (VIN = 12 V, VO = 1.05 V, IO = 0.1 A to 10 A to
0.1 A, L = 0.56 mH, CO = 470 mF * 2)
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22
NCP5222
TYPICAL OPERATING CHARACTERISTICS
Figure 41. Line Transient Response (VIN = 12 V to
20 V, VO1 = 1.05 V, IO1 = 9 A, L1 = 0.56 mH, CO1 =
470 mF * 2, VO2 = 1.05 V, IO2 = 9 A, L2 = 0.56 mH,
CO2 = 470 mF * 2, Dual−Channel Mode)
Figure 42. Line Transient Response (VIN = 20 V to
12 V, VO1 = 1.05 V, IO1 = 9 A, L1 = 0.56 mH, CO1 =
470 mF * 2, VO2 = 1.05 V, IO2 = 9 A, L2 = 0.56 mH,
CO2 = 470 mF * 2, Dual−Channel Mode)
Figure 43. Powerup with EN1 in Two−Phase Mode
(VIN = 12 V, VO1 = 1.05 V, IO1 = 0 A, VO2 = 1.05 V, IO2
= 0 A)
Figure 44. Powerdown with EN1 in Two−Phase
Mode (VIN = 12 V, VO1 = 1.05 V, IO1 = 0 A, VO2 =
1.05 V, IO2 = 0 A)
Figure 45. Powerup with Two ENs together in
Two−Phase Mode (VIN = 12 V, VO1 = 1.05 V, IO1 =
0 A, VO2 = 1.05 V, IO2 = 0 A)
Figure 46. Powerdown with Two ENs together in
Two−Phase Mode (VIN = 12 V, VO1 = 1.05 V, IO1 =
0 A, VO2 = 1.05 V, IO2 = 0 A)
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23
NCP5222
Figure 47. Schematic of Evaluation Board
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24
NCP5222
Figure 48. Layout of Evaluation Board
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25
NCP5222
BILL OF MATERIALS FOR EVALUATION BOARD
Item
Part Reference
Package
Part Number
Manufacturer
Qty
1
U1
Dual−Channel /
Two−Phase Synchronous
Buck Controller
Description
QFN28
(4x4 mm)
NCP5222MNR2G
ON Semiconductor
1
2
M11 M21 Q1 Q2
Small Signal MOSFET
60 V, 115 mA, N−Channel
SOT−23
2N7002LT1G
ON Semiconductor
4
3
Q3
Small Signal MOSFET
30 V, 270 mA, N−Channel
SC−70
NTS4001NT1G
ON Semiconductor
1
4
M12 M14 M22 M24
Power MOSFET 30 V,
58.5 A, Single N−Channel
SO−8 Flat
Lead
NTMFS4821NT1G
ON Semiconductor
4
5
M13 M15 M23 M25
Power MOSFET 30 V,
85 A, Single N−Channel
SO−8 Flat
Lead
NTMFS4847NT1G
ON Semiconductor
4
6
M1
Power MOSFET 30 V,
191 A, Single N−Channel
SO−8 Flat
Lead
NTMFS4833NT1G
ON Semiconductor
0
7
D1
Schottky Diode, dual,
common anode, 30 V
SOT−23
BAT54ALT1G
ON Semiconductor
1
8
D12 D22
LED, SMT, 2 mm, GRN
0805
L−0170GCT
PARA Light
2
9
C11 C21
MLCC Cap 50 V, 22 pF,
$5%, Char: COG
0603
C1608C0G1H220J
TDK
2
10
C12 C22
MLCC Cap 50 V, 330 pF,
$5%, Char: COG
0603
C1608C0G1H331J
TDK
2
11
C13 C23
MLCC Cap 50 V, 820 pF,
$5%, Char: COG
0603
C1608C0G1H821J
TDK
2
12
C1 C4
MLCC Cap 50 V, 2.2 nF,
$5%, Char: COG
0603
C1608C0G1H222J
TDK
0
13
C5
MLCC Cap 50 V, 10 nF,
$5%, Char: COG
0603
C1608C0G1H103J
TDK
1
14
C2
MLCC Cap 50 V, 15 nF,
$10%, Char: X7R
0603
C1608X7R1H153K
TDK
1
15
CB1 CB2 CS1 CS2
MLCC Cap 50 V, 0.1 mF,
$10%, Char: X7R
0603
C1608X7R1H104K
TDK
4
16
C3
MLCC Cap 16 V, 1 mF,
$10%, Char: X5R
0805
C2012X7R1C105K
TDK
1
17
C41
MLCC Cap 6.3 V, 3.3 mF,
$10%, Char: X5R
0603
C1608JB0J335KT
TDK
1
18
C6 C16 C26
19
C111 C222
MLCC Cap 6.3 V, 10 mF,
$10%, Char: X5R
0805
ECJ2FB0J106M
Panasonic
2
20
CIN1 CIN2 CIN3
CIN4
MLCC Cap 25V, 10 mF,
$20%, Char: X5R
1812
C4532X7R1E106M
TDK
4
21
C17 C18 C27 C28
SP−Capacitors, 2 V,
470 mF, ESR = 4.5 mW
7.3mm x
4.3mm
EEFSX0D471XR
Panasonic
4
22
RB1 RB2
Thick Film Chip Resistors,
3.3 W, $1%, 0.1 W
0603
ERJ3BSF3R3V
Panasonic
2
23
R1 R5
Thick Film Chip Resistors,
20 W, $1%, 0.1 W
0603
ERJ3EKF20R0V
Panasonic
2
24
R13 R23
Thick Film Chip Resistors,
100 W, $1%, 0.1 W
0603
ERJ3EKF1000V
Panasonic
2
25
R18 R19
Thick Film Chip Resistors,
1 kW, $1%, 0.1 W
0603
ERJ3EKF1001V
Panasonic
2
26
R16 R26
Thick Film Chip Resistors,
3.9 kW, $1%, 0.1 W
0603
ERJ3EKF3901V
Panasonic
2
0603
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26
0
NCP5222
BILL OF MATERIALS FOR EVALUATION BOARD
Item
Part Reference
Description
Package
Part Number
Manufacturer
Qty
27
R11 R21
Thick Film Chip Resistors,
5.1 kW, $1%, 0.1 W
0603
ERJ3EKF5101V
Panasonic
2
28
R15 R25
Thick Film Chip Resistors,
16 kW, $1%, 0.1 W
0603
ERJ3EKF1602V
Panasonic
2
29
R14 R24
Thick Film Chip Resistors,
16.2 kW, $1%, 0.1 W
0603
PCF0603R 16K2BI
WELWTN
2
30
R9 R10
Thick Film Chip Resistors,
39 kW, $1%, 0.1 W
0603
ERJ3EKF3902V
Panasonic
2
31
R6 R7 R8 R20
Thick Film Chip Resistors,
62 kW, $1%, 0.1 W
0603
ERJ3EKF6202V
Panasonic
4
32
R12 R22
Thick Film Chip Resistors,
91 kW, $1%, 0.1 W
0603
ERJ3EKF9102V
Panasonic
2
33
R29 R30
Thick Film Chip Resistors,
86.6 kW, $1%, 0.1 W
0603
PCF0603R 86K6BI
WELWTN
2
34
R2 R3 R28
Thick Film Chip Resistors,
100 kW, $1%, 0.1 W
0603
ERJ3EKF1003V
Panasonic
3
35
R4 R17 R27
36
L1 L2
37
TT1, TT2, TT3,
TT4, TT00, TT01,
TT21, TT22
PCB Terminal
38
TP11 TP12 TP13
TP14, TP21 TP22
TP23 TP24, JP1
JP2 JP4 JP5, T3
T4 T5 T6 J3
39
J1 J2
40
SW1 SW2 SW3
SW4
0603
0
11.2mm x
10.0mm
FDU1040D−R56M
TOKO
2
7.54mm, f =
3.18 mm
H−2121
HARWIN
8
THT Header Pitch =
2.54 mm; Height = 12 mm
547−3302
RS Components
17
SMB−Connectors,
Impedance = 50 W
295−5665
RS Components
2
NKK
4
Power Choke 0.56 mH,
DCRtyp=1.4 mW, ISAT =
22.9 A
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27
NCP5222
PACKAGE DIMENSIONS
QFN28 4x4, 0.4P
CASE 485AR−01
ISSUE A
PIN ONE
REFERENCE
B
A
D
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉ
ÉÉ
EXPOSED Cu
0.10 C
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L
L
MOLD CMPD
DETAIL B
TOP VIEW
ALTERNATE
CONSTRUCTION
A
DETAIL B
A3
0.10 C
0.08 C
NOTE 4
A1
SIDE VIEW
RECOMMENDED
MOUNTING FOOTPRINT*
SEATING
PLANE
C
4.30
2.71
0.10 C A B
D2
DETAIL A
K
8
28X
0.62
1
0.10 C A B
15
28X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.15
0.25
4.00 BSC
2.50
2.70
4.00 BSC
2.50
2.70
0.40 BSC
0.30 REF
0.30
0.50
−−−
0.15
L
2.71
4.30
E2
PACKAGE
OUTLINE
1
PIN 1
INDICATOR
0.40
PITCH
22
e
28X
BOTTOM VIEW
b
0.07 C A B
0.05 C
NOTE 3
28X
0.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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28
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP5222/D