NCP1589A D

NCP1589A, NCP1589B
Low Voltage Synchronous
Buck Controller
The NCP1589A/B is a low cost PWM controller designed to operate
from a 5 V or 12 V supply. This device is capable of producing an
output voltage as low as 0.8 V. This device is capable of converting
voltage from as low as 2.5 V. This 10−pin device provides an optimal
level of integration to reduce size and cost of the power supply.
Features include a 1.5 A gate driver design and an internally set
300 kHz or 600 kHz oscillator. In addition to the 1.5 A gate drive
capability, other efficiency enhancing features of the gate driver
include adaptive non−overlap circuitry. The NCP1589A/B also
incorporates an externally compensated error amplifier. Protection
features include programmable short circuit protection and
undervoltage lockout (UVLO).
Features
•
•
•
•
•
•
•
•
•
•
•
MARKING DIAGRAM
1589x
ALYWG
G
DFN10
CASE 485C
1589x
= Specific Device Code
x = A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Device
A
L
Y
W
G
VCC Range from 4.5 V to 13.2 V
300 kHz and 600 kHz Internal Oscillator
Boost Pin Operates to 30 V
Voltage Mode PWM Control
Precision 0.8 V Internal Reference
Adjustable Output Voltage
Internal 1.5 A Gate Drivers
80% Max Duty Cycle
Input Under Voltage Lockout
Programmable Current Limit
This is a Pb−Free Device
(Note: Microdot may be in either location)
PIN CONNECTIONS
Applications
•
•
•
•
•
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Graphics Cards
Desktop Computers
Servers / Networking
DSP & FPGA Power Supply
DC−DC Regulator Modules
PGOOD
BOOT
1
10
LX
2
9
VOS
UG
3
8
FB
LG
4
7
COMP/EN
GND
5
6
VCC
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
DFN10
(Pb−Free)
3000 /
Tape & Reel
NCP1589AMNTWG
NCP1589BMNTWG
NCP1589AMNTXG
NCP1589BMNTXG
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 1
1
Publication Order Number:
NCP1589A/D
NCP1589A, NCP1589B
1mF
VIN = 2.5 V − 20 V
3x22mF
VBST = 4.5 V − 15 V
1500mF
VCC = 4.5 V − 13.2 V
2x0.22mF
1500mF
VCC
BOOT
NTD4809
PGOOD
0.1mF
COMP/EN
UG
R2
17.08kW
LG
GND
C3
0.014mF
R3
74.2W
R9
R10
2x1800mF
4.7nF
1.02k
R1
4.12kW
1.02k
R4
3.878kW
VOS
VOUT
1.65 V
1mH
2.2
FB
NTD4806
LX
C2
0.007mF
ROCSET
C1
0.0015mF
GND
Figure 1. Typical Application Diagram
PGOOD
PGOOD
MONITOR
OV and UV
VOS 9
±10% of Vref
±25% of Vref
0.8 V
(Vref)
POR
UVLO
8
−
+
+
−
0.8 V
(Vref)
+
LATCH
FAULT
FB
10
6
VCC
1
BOOT
3
UG
2
LX
4
LG
5
GND
VOCP
−
FAULT
R
S
PWM
OUT
Q
+
−
CLOCK
RAMP
COMP/EN
7
2V
+
SOFT
START
−
OSC
OSC
FAULT
Figure 2. Detailed Block Diagram
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2
VCC
NCP1589A, NCP1589B
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
BOOT
Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired
input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (CBOOT) between this pin and
the LX pin. Typical values for CBOOT range from 0.1 mF to 1 mF. Ensure that CBOOT is placed near the IC.
2
LX
Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top
MOSFET.
3
UG
Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET.
4
LG
Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET.
5
GND
IC ground reference. All control circuits are referenced to this pin.
6
VCC
Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor
to GND. Ensure that this decoupling capacitor is placed near the IC.
7
COMP/EN
Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. Pull this
pin low for disable.
8
FB
9
VOS
10
PGOOD
This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly
to Vout.
Voltage Offset Sense
Power Good output. Pulled Low if VOS is ±10% of 0.8 V Vref.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Symbol
VMAX
VMIN
VCC
15 V
−0.3 V
BOOT
35 V wrt/GND
40 V < 100 ns
15 V wrt/LX
−0.3 V
−0.3 V
−0.3 V
Switching Node (Bootstrap Supply Return)
LX
35 V
40 V for < 100 ns
−5 V
−10 V for < 200 ns
High−Side Driver Output (Top Gate)
UG
30 V wrt/GND
15 V wrt/LX
40 V for < 100 ns
−0.3 V wrt/LX
−2 V for < 200 ns
Low−Side Driver Output (Bottom Gate)
LG
VCC + 0.3 V
−0.3 V
−5 V for < 200 ns
FB, VOS
5.0 V
−0.3 V
COMP/EN
3.6 V
−0.3 V
PGOOD
7V
−0.3 V
Symbol
Value
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
165
°C/W
Thermal Resistance, Junction−to−Case
RqJC
45
°C/W
Operating Junction Temperature Range
TJ
0 to 150
°C
Operating Ambient Temperature Range
TA
0 to 70
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Moisture Sensitivity Level
MSL
1
−
Main Supply Voltage Input
Bootstrap Supply Voltage Input
Feedback, VOS
COMP/EN
PGOOD
MAXIMUM RATINGS
Rating
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
This device is ESD sensitive. Use standard ESD precautions when handling.
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3
NCP1589A, NCP1589B
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V, 0 V < PHASE < 21 V,
CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.)
Characteristic
Conditions
Max
Unit
4.5
13.2
V
13.2 V wrt LX
4.5
30
V
VFB = 1.0 V, No Switching, VCC = 13.2 V
1.0
8.0
mA
VFB = 1.0 V, No Switching
0.1
VCC Rising
3.8
4.0
4.2
V
UVLO Threshold
VCC Falling
3.4
3.6
3.8
V
UVLO Hysteresis
VCC Rising or VCC Falling
VCC Voltage Range
Boost Voltage Range
Min
Typ
Supply Current
Quiescent Supply Current (NCP1589A)
Boost Quiescent Current
mA
Undervoltage Lockout
UVLO Threshold
0.4
V
Switching Regulator
VFB Feedback Voltage
0.7936
0.8
0.8064
V
Oscillator Frequency (NCP1589A)
(FB Tied to Comp. Measure FB Pin.)
270
300
330
kHz
Oscillator Frequency (NCP1589B)
540
600
660
kHz
Ramp−Amplitude Voltage
Minimum Duty Cycle
Maximum Duty Cycle
70
LG Minimum on Time
1.1
V
0
%
75
80
500
%
ns
Error Amplifier
Open Loop DC Gain (Note 1)
70
Output Source Current
Output Sink Current
Vfb < 0.8 V
Vfb > 0.8 V
Input Offset Voltage (Note 1)
80
dB
2.0
2.0
−2.0
Input Bias Current
Unity Gain Bandwidth (Note 1)
15
Disable Threshold
0.6
Output Source Current During Disable
mA
0
2.0
0.1
1.0
mV
mA
Mhz
0.8
10
V
40
mA
Gate Drivers
Upper Gate Source
VCC = 5 V, VUG − VLX = 2.5 V
1.5
Upper Gate Sink
A
W
1.4
Lower Gate Source
1.5
A
1.0
W
UG Falling to LG Rising Delay
VCC = 12 V, UG−LX < 2.0 V, LG > 2.0 V
12.4
18
ns
LG Falling to UG Rising Delay
VCC = 12 V, LG < 2.0 V, UG > 2.0 V
12.4
18
ns
Lower Gate Sink
VCC = 12 V
Soft−Start
Soft−Start time
3.0
7.0
ms
0.4
V
Power Good
Output Voltage
OVP Threshold to PGOOD Output Low
OVP Threshold to Part Disable
Logic Low, Sinking 4 mA
Ramp VOS from 0.7 to 1.2.
Monitor when PGOOD goes Low
0.88
1.0
V
Ramp VOS from 0.8 to 1.2.
Monitor when outputs disable
1.0
1.2
V
UVP Threshold to PGOOD Output Low
Ramp VOS from 800 mV to 500 mV.
Monitor when PGOOD goes Low
0.65
0.72
V
UVP Threshold to Part Disable
Ramp VOS from 800 mV to 500 mV.
Monitor when utputs stop switching
0.5
0.6
V
Sourced from LG pin, before SS
9.0
10
Overcurrent Protection
OC Current Source (Note 1)
1. Guaranteed by design but not tested in production.
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4
11
mA
NCP1589A, NCP1589B
TYPICAL CHARACTERISTICS
303
808
806
Vref, REFERENCE (mV)
FSW, FREQUENCY (kHz)
VCC = 12 V
VCC = 5 V
302
301
300
804
802
800
798
796
794
299
792
0
10
20
30
40
50
60
70
0
TJ, JUNCTION TEMPERATURE (°C)
20
40
60
80
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Oscillator Frequency (FSW) vs.
Temperature
Figure 4. Reference Voltage (Vref) vs.
Temperature
543
5.3
NCP1589B
OCP THRESHOLD (mV)
5.0
ICC (mA)
4.7
NCP1589A
4.4
4.1
542
541
540
3.8
3.5
0
20
40
60
539
0
80
20
40
60
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. ICC vs. Temperature
Figure 6. OCP Threshold at 55k vs. Temperature
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5
80
NCP1589A, NCP1589B
APPLICATIONS INFORMATION
Over Current Protection (OCP)
the under voltage lockout threshold, or if the NCP1589A/B
is disabled by having the COMP pin pulled low.
The NCP1589A/B monitors the voltage drop across the
low side mosfet and uses this information to determine if
there is excessive output current. The voltage across the low
side mosfet is measured from the LX pin, and is referenced
to ground. The over current measurement is timed to occur
at the end of the low side mosfet conduction period, just
before the bottom mosfet is turned off.
If the voltage drop across the bottom mosfet exceeds the
over current protection threshold, then an internal counter is
incremented. If the voltage drop does not exceed the over
current protection threshold, then the internal counter is
reset. The NCP1589A/B will latch the over current
protection fault condition only if the over current protection
threshold is exceeded for four consecutive cycles.
When the NCP1589A/B latches an over current
protection fault, both the high side and low side mosfets are
turned off. To reset the over current protection fault, the
power to the VCC pin must be cycled.
The over current threshold voltage can be externally, by
varying the value of the ROCSET resistor. The ROCSET
resistor is a resistor connected between the LG pin (low side
mosfet gate) and ground.
During startup, after the VCC and BOOT pins reach the
under voltage lock out threshold, the NCP1589A/B will
source 10 mA of current out of the LG pin. This current will
flow through the ROCSET resistor and produce a voltage
that is sampled and then used as the over current protection
threshold voltage. For example, if ROCSET is set to 10 kW,
the 10 mA of current will yield a 100 mV threshold, and if the
voltage drop across the low side mosfet exceeds 100 mV at
the end of its conduction period, then an over current event
will be detected.
If the ROCSET resistor is not present, then the over
current protection threshold will max out at 640 mV. The
valid range for ROCSET is 5 kW to 55 kW which yields a
threshold voltage range of 50 mV to 550 mV.
Startup into a Precharged Load
During a startup and soft start sequence the NCP1589A
will detect a residual charge on the output capacitors and not
forcefully discharge the capacitors before beginning the
softstart sequence, instead, the softstart ramping of the
output will begin at the voltage level of the residual charge.
For example, if the NCP1589A/B is configured to provide
a regulated output voltage of 2.5 V, the normal softstart
sequence will ramp the output voltage from 0 to 2.5 V in
4.2 ms; however if the output capcitors already have a 1.2 V
charge on them, the NCP1589A/B will not discharge the
capacitors, instead the softstart sequence will begin at 1.2 V
and then ramp the output to 2.5 V.
Power Good
The PGOOD pin is an open drain active high output pin
that signals the condition of the VOS (Voltage Output Sense)
pin. PGOOD is pulled low during soft start cycle, and if there
is a latched over current, over voltage, or under voltage fault.
If the voltage on the VOS pin is within ±10% of Vref
(800 mV) then the PGOOD pin will not be pulled low. The
PGOOD pin does not have an internal pull-up resistor.
Overvoltage Protection
If the voltage on the VOS pin exceeds the over voltage
threshold the NCP1589A/B will latch an over voltage fault.
During an over voltage fault the UG pin will be pulled low,
and the LG pin will be high while the until the voltage on the
VOS pin goes below Vref/2 (400 mV). The NCP1589A will
continue drive the LG pin, LG will go high if VOS exceeds
1 V and then go low when VOS goes below 400 mV. The
power to the NCP1589 must be cycled to reset the over
voltage protection fault.
Under Voltage Protection
If the voltage on the VOS pin falls below the under voltage
threshold after the soft start cycle completes, then the
NCP1589A/B will latch an under voltage fault. During an
under voltage fault, both the UG and LG pins will be pulled
low. The power to the NCP1589 must be cycled to reset the
under voltage protection fault.
Internal Soft-Start
To prevent excess inrush current during startup, the
NCP1589A/B uses a calibrated current source with an
internal soft start capacitor to ramp the reference voltage
from 0 to 800 mV over a period of 4 ms. The softstart ramp
generator will reset if the input power supply voltages reach
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6
NCP1589A, NCP1589B
4.0 V
3.6 V
VCC
Internal
UVLO
Fault
1.45 V
COMP
−0.7 V
LG
700 mV
50 mV
OCP
Programmable
UG
VOUT
0.8 V
FB
PGOOD
POR
UVLO
SS
NORMAL
Figure 7. Typical Startup Sequence
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7
NCP1589A, NCP1589B
VOS
1.0V
0.88V
0.8V
0.88V
0.8V
0.72V
0.6V
0.4V
PGOOD
UG
LG
Overvoltage
Undervoltage
Figure 8. Typical Power Good Function
Feedback and Compensation
Design Example
The NCP1589A/B allows the output voltage to be
adjusted from 0.8 V to 5.0 V via an external resistor divider
network. The controller will try to maintain 0.8 V at
feedback pin. Thus, if a resistor divider circuit was placed
across the feedback pin to VOUT, the controller will regulate
the output voltage proportional to the resistor divider
network in order to maintain 0.8 V at the FB pin. The same
formula applies to the VOS pin and the controller will
maintain 0.8 V at the VOS pin.
Voltage Mode Control Loop with TYPE III
Compensation
Converter Parameters:
Input Voltage: VIN = 5 V
Output Voltage: VOUT = 1.65 V
Switching Frequency: 300 kHz
Total Output Capacitance: COUT = 3600 mF
Total ESR: ESR = 6 mW
Output Inductance: LOUT: 1 mH
Ramp Amplitude: VRAMP = 1.1 V
VOUT
C1
R1
FB
R3
C3
R2
C2
R4
VOUT
Figure 9.
VCOMP
Vref
ǒVOUTVREF
Ǔ
* VREF
Figure 10.
a.. Set a target for the close loop bandwidth at 1/6th of
the switching frequency.
The same formula can be applied to the feedback resistors
at VOS.
R9 + R10
−
E/A
+
R4
The relationship between the resistor divider network
above and the output voltage is shown in the following
equation:
R4 + R1
R1
ǒVOUTVREF
Ǔ
* VREF
F cross_over :+ 50 kHz
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8
NCP1589A, NCP1589B
Step 5: Place 2nd zero at the output filter double pole
frequency.
b.. Output Filter Double Pole Frequency
F lc :+
1
2 @ p @ Ǹ L OUT @ C OUT
R3 :+
Step 6: Place 2nd pole at half the switching frequency.
1
2 @ p @ C OUT @ C ESR
C3 :+
F ESR + 7.368 kHz
Step 7: R4 is sized to maintain the feedback voltage to
Vref = 0.8 V.
R1 :+ 4.12 kW
Step 2: Pick compensation DC gain (R2/R1) for desired
close loop bandwidth.
R4 :+
V RAMP :+ 1.1 V
Ǔǒ
V RAMP
V IN
@
Ǔ
F lc
R1 = 4.12 kW
R2 = 17.085 kW
R3 = 74.169 W
R4 = 3.878 kW
C1 = 0.0015 mF
C2 = 0.007 mF
C3 = 0.014 mF
NOTE: Recommend to change values to industry
standard component values.
2 @ ǸL OUT @ C OUT
R2
10 −3 mF
Step 4: Place 1st pole at ESR zero frequency.
C1 :+
C2
C2 @ R2 @ 2 @ p @ F ESR * 1
C1 + 1.542
V OUT * V REF
The Component values for Type III Compensation are:
Step 3: Place 1st zero at half the output filter double pole
frequency.
C2 + 7.024
V REF @ R1
R4 + 3.878 kW
F cross_over
R2 + 17.085 kW
C2 :+
1
ǒ p @ R3 @ FSWǓ
C3 + 0.014 mF
Step 1: Set a value for R1 between 2 kW and 5 kW
ǒ
*1
lc
R3 + 74.169 W
c.. ESR Zero Frequency:
R2 :+ R1 @
SW
2@F
F lc + 2.653 kHz
F ESR :+
R1
F
10 −3 mF
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9
NCP1589A, NCP1589B
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE D
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG
SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A AND B
ALTERNATE CONSTRUCTION ARE NOT APPLICABLE.
L
L1
PIN ONE
REFERENCE
0.15 C
2X
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.15 C
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTION
E
ÉÉÉ
ÇÇÇ
ÇÇÇ
EXPOSED Cu
TOP VIEW
(A3)
DETAIL B
0.10 C
A1
C
10X
1
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.70
1.90
0.50 BSC
0.19 TYP
0.35
0.45
0.00
0.03
SOLDERING FOOTPRINT*
D2
DETAIL A
ÇÇ
ÉÉ
ALTERNATE
CONSTRUCTIONS
0.08 C
SIDE VIEW
A1
A3
DETAIL B
A
10X
MOLD CMPD
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L
2.64
5
PACKAGE
OUTLINE
10X
0.55
E2
1.90
K
10
6
10X
e
BOTTOM VIEW
3.30
b
0.10 C A B
0.05 C
10X
0.30
0.50
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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NCP1589A/D