NCP4208 D

NCP4208
VR11.1 Digital
Programmable 8-Phase
Synchronous Buck
Converter with I2C
Interface
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The NCP4208 is an integrated power control IC with an I2C interface.
The NCP4208 is a highly efficient, multiphase, synchronous buck
switching regulator controller, which aids design of High Efficiency and
High Density solutions. The NCP4208 can be programmed for 1−, 2−,
3−, 4−, 5−, 6−, 7− or 8−phase operation, allowing for the construction of
up to 8 complementary buck switching stages.
The NCP4208 supports PSI, which is a power state indicator and
can be used to reduce the number of operating phases at light loads.
The I2C interface enables digital programming of key system
parameters to optimize system performance and provide feedback to
the system.
The NCP4208 has a built in shunt regulator that allows the part to be
powered from the +12 V system supply through a series resistor. The
NCP4208 is specified over the extended commercial temperature
range of 0°C to +85°C and is available in a 48 Lead QFN package.
QFN 48
CASE 485AJ
1 48
MARKING DIAGRAM
NCP4208
AWLYYWWG
A
WL
YY
WW
G
Features
• Selectable 1−, 2−, 3−, 4−, 5−, 6−, 7− or 8−Phase Operation at
•
•
•
•
Applications
• Desktop PC
• Servers
PSI
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VCC
PWM1
PWM2
48
47
46
45
44
43
42
41
40
39
38
37
VCC3
PWRDG
ALERT
SDA
SCL
EN
GND
NC
NC
IMON
IREF
RT
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
NCP4208
TOP VIEW
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
SW1
SW2
SW3
SW4
SW5
SW6
13
14
15
16
17
18
19
20
21
22
23
24
•
•
•
PIN ASSIGNMENT
RAMPADJ
FBRTN
COMP
FB
CSREF
CSSUM
CSCOMP
ILIMIFS
ODN
OD1
SW8
SW7
•
•
Up to 1.5 MHz per Phase
Temperature Measurement
Logic−Level PWM Outputs for Interface to External High
Power Drivers
Fast−Enhanced PWM for Excellent Load Transient Performance
Active Current Balancing Between All Output Phases
Built−In Power−Good/Crowbar Blanking Supports
On−The−Fly (OTF) VID Code Changes
Digitally Programmable 0.375 V to 1.6 V Output Supports
VR11.1 Specifications
Short Circuit Protection with Latchoff Delay
Supports PSI Power Saving Mode During Light Loads
This is a Pb−Free Device
= Assembly Lot
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NCP4208MNR2G
Package
Shipping†
QFN48 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
September, 2013 − Rev. 5
1
Publication Order Number:
NCP4208/D
NCP4208
VCC
VCC3
39
1
SHUNT
REGULATOR
3.3 V
REGULATOR
SCL SDA
5
4
RAMPADJ
12
13
PSI
21
ODN
22
OD1
RESET
38
PWM1
RESET
37
PWM2
36
PWM3
35
PWM4
34
PWM5
33
PWM6
32
PWM7
31
PWM8
30
SW1
29
SW2
28
SW3
27
SW4
26
SW5
25
SW6
24
SW7
23
SW8
19
CSCOMP
17
CSREF
18
CSSUM
10
IMON
16
FB
SET
SMBUS
7
48
OSCILLATOR
UVLO
SHUTDOWN
GND
RT
CMP
EN
850 mV
EN/VTT
CMP
6
CMP
CONTROL
CURRENT
BALANCING
CIRCUIT
CONTROL
RESET
CMP
CMP
CSREF
PWRGD
ALERT
CMP
CMP
2
3
DELAY
RESET
RESET
RESET
CROWBAR
COMPARATORS
1− 8 PHASE
DRIVER
LOGIC
RESET
CMP
CONTROL
RESET
CURRENT
LIMIT
DIGITAL
REGISTERS
CONTROL
EN
FB
FBRTN
IMON
MUX
ADC
CONTROL
ILIMIFS
20
CURRENT
MEASUREMENT
AND LIMIT
CONTROL
IREF
11
COMP
15
CONTROL
NCP4208
PRECISION
REFERENCE
14
FBRTN
BOOT VOLTAGE
AND SOFT−START
CONTROL
VID DAC
47
46
45
44
43
42
41
40
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
Figure 1. Simplified Block Diagram
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2
NCP4208
0.1 uF
Vin 12 V
4.7 uF
ADP3121
1200 uF
16 V
1
BST
2
IN
3
OD
DRVH
8
SW
7
PGND
6
4
VCC
DRVL
5
150 nH
Vcc Core
Vcc Core (RTN)
10
1.0 uF
Vcc Sense
SW1
0.1 uF
Vcc Sense
4.7 uF
ADP3121
1
BST
2
IN
DRVH
8
SW
3
7
OD
PGND
6
4
VCC
DRVL
5
150 nH
10
1.0 uF
SW2
0.1 uF
4.7 uF
ADP3121
1k
680
680
1 uF
X7R
1
BST
2
IN
3
OD
4
VCC
DRVH
8
SW
7
PGND
6
DRVL
5
150 nH
10
1.0 uF
1 uF
X7R
PSI
0.1 uF
SW3
4.7 uF
PWM2
PWM4
ALERT
PWM5
I2C
SDA
PWM6
Interface
SCL
PWM7
EN
PWM8
1 nF
NCP4208
GND
1k
SW1
BST
2
IN
DRVH
8
SW
3
7
OD
PGND
6
4
VCC
DRVL
5
1k
10
SW2
1k
SW3
1k
4.7 uF
SW4
ADP3121
SW5
SW6
63.4 k
63.4 k
63.4 k
63.4 k
63.4 k
63.4 k
7.5 k, 1%
1k
63.4 k
SW7
SW8
SW7
SW8
OD1
ODN
FB
348 k
220 k
121 k
ILIMFS
SW6
CSCOMP
SW5
CSSUM
IREF
1k
COMP
SW4
CSREF
SW3
FBRTN
SW2
IMON
1k
1
BST
2
IN
3
OD
DRVH
8
SW
7
PGND
6
4
VCC
DRVL
5
10
SW5
1500 pF
X7R
35.7 k
4.7 uF
82.5 k
ADP3121
100 k Thermistor
5%
470 pF
X7R
3.3 pF
1.21 k
32.4 k
150 nH
1.0 uF
0.1 uF
1500 pF
X7R
150 nH
SW4
0.1 uF
SW1
1k
NC
RT
1
1.0 uF
NC
RAMPADJ
4.99 k
4.7 uF
PWM3
PWRGD
ALERT
VTT I/O
PWM1
VCC
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI
VCC3
POWERGOOD
ADP3121
470 pF
X7R
1
BST
2
IN
3
OD
DRVH
8
SW
7
PGND
6
4
VCC
DRVL
5
150 nH
10
1.0 uF
SW6
0.1 uF
4.7 uF
ADP3121
1000 pF
1
BST
2
IN
3
OD
4
VCC
DRVH
8
SW
7
PGND
6
DRVL
5
150 nH
10
1.0 uF
SW7
0.1 uF
4.7 uF
ADP3121
1
BST
2
IN
3
OD
DRVH
8
SW
7
PGND
6
4
VCC
DRVL
5
150 nH
10
1.0 uF
SW8
Figure 2. Application Schematic
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3
NCP4208
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 6
V
VFBRTN
−0.3 to +0.3
V
−0.3 to VIN + 0.3
V
SW1 to SW8
−5 to +25
V
SW1 to SW8 (<200 ns)
−10 to +25
V
Input Voltage Range
FBRTN
PWM2 to PWM8, Rampadj
All other Inputs and Outputs
Storage Temperature Range
−0.3 to VIN + 0.3
V
−65 to 150
°C
TSTG
Operating Ambient Temperature Range
0 to 85
°C
ESD Capability, Human Body Model
ESDHBM
1.5
kV
ESD Capability, Machine Model
ESDMM
150
V
TSLD
260
°C
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 2)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
RqJA
27
°C/W
Thermal Resistance, Junction−to−Air (Note 2)
QFN, 7x7 mm
2. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
TYPICAL CHARACTERISTICS
2500
Frequency (kHz)
2000
1500
PWM1
1000
500
0
0
100
200
300
400
500
600
700
RT (kW)
Figure 3. NCP4208 RT vs Frequency
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4
800
900
NCP4208
PIN ASSIGNMENT
Pin No.
Mnemonic
Description
1
VCC3
2
PWRGD
3
ALERT
4
SDA
Digital Input / Output. I2C serial data bidirectional pin. Requires pullup.
5
SCL
Digital Input. I2C serial bus clock open drain input. Requires pullup.
6
EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the
PWRGD output low.
7
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this
ground.
3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the
interval 3.3 V LDO.
Power−Good Output: Open−drain output that signals when the output voltage is outside of the
proper operating range.
ALERT Output: Open drain output that asserts low when the VR exceeds a programmable limit.
Can be configured for Comparator Mode or Interrupt Mode.
8 to 9
NC
10
IMON
No Connect
Total Current Output Pin.
11
IREF
Current Reference Input. An external resistor from this pin to ground sets the reference current for
IFB, and IILIMFS.
12
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND
sets the oscillator frequency of the device.
13
RAMPADJ
14
FBRTN
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output
voltage.
15
COMP
Error Amplifier Output and Compensation Point.
16
FB
17
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the
current sense amplifier and the power−good and crowbar functions. This pin should be
connected to the common point of the output inductors.
18
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the
average inductor currents together to measure the total output current.
19
CSCOMP
20
ILIMFS
Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the
internal current sensing signal for current limit and IMON. This value can be overwritten using
the I2C interface.
21
ODN
Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low,
otherwise it functions in the same way as OD1.
22
OD1
Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when
VCC is below its UVLO threshold to signal to the Driver IC that the driver high−side and
low−side outputs should go low.
23 to 30
SW8 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of
unused phases should be left open.
31 to 38
PWM8 to PWM1
39
VCC
40 to 47
VID7 to VID0
48
PSI
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets
the internal PWM ramp.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external
resistor between this pin and the output voltage sets the no load offset point.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM
determines the gain of the current sense amplifier and the positioning loop response time.
Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver
such as the ADP3121. Connecting the PWM8, PWM7, PWM6, PWM5, PWM4, PWM3 and
PWM2 outputs to VCC causes that phase to turn off, allowing the NCP4208 to operate as a
1−, 2−, 3−, 4−, 5−, 6−, 7−, or 8−phase controller.
Supply Voltage for the Device. A 340 W resistor should be placed between the 12 V system
supply and the VCC pin. The internal shunt regulator maintains VCC = 5.0 V.
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic
zero if left open. When in normal operation mode, the DAC output programs the FB regulation
voltage from 0.375 V to 1.6 V.
Power State Indicator. Pulling this pin low places the controller in lower power state operation.
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5
NCP4208
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN − GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 1 and 2)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VIREF
1.75
1.8
1.85
V
Reference Current
Reference Bias Voltage
Reference Bias Current
IIREF
RIREF = 121 kW
15
mA
Error Amplifier
Output Voltage Range
VCOMP
0
4.4
V
VFB
−9.0
+9.0
mV
VFB(BOOT)
1.091
1.1
1.109
V
Load Line Positioning Accuracy
−77
−80
−83
mV
Load Line Range
−350
0
mV
Accuracy
Relative to nominal DAC output, referenced
to FBRTN (refer to Figure 4)
In startup
Load Line Attenuation
Differential Non−linearity
Input Bias Current
IFB = IIREF
Offset Accuracy
VR Offset Register = 111111, VID = 1.0 V
VR Offset Register = 011111, VID = 1.0 V
IFB
FBRTN Current
Output Current
FB forced to VOUT −3%
Gain Bandwidth Product
COMP = FB
Slew Rate
COMP = FB
BOOT Voltage Hold Time
Internal Timer
0
100
%
−1.0
+1.0
LSB
13.3
15
18.5
−193.75
193.75
mA
mV
IFBRTN
100
200
ICOMP
500
mA
GBW(ERR)
20
MHz
25
V/ms
tBOOT
2.0
ms
mA
VID Inputs
Input Low Voltage
Input High Voltage
VID(X)
VIL(VID)
VIH(VID)
Input Current
0.3
0.8
IIN(VID)
−5.0
V
mA
VID Transition Delay Time
VID code change to FB change
400
ns
No CPU Detection Turn−Off Delay
Time
VID code change to PWM going low
5.0
ms
Oscillator
Frequency Range
Frequency Variation
TA = 25°C, RT = 500 kW, 4−phase
TA = 25°C, RT = 250 kW, 4−phase
TA = 25°C, RT = 121 kW, 4−phase
Output Voltage
RT = 500 kW to GND
RAMPADJ Output Voltage
RAMPADJ − FB, VFB = 1.0 V,
IRAMPADJ = −150 mA
RAMPADJ Input Current Range
fOSC
0.25
9.0
MHz
fPHASE
170
195
375
750
225
kHz
VRT
1.9
2.01
2.1
V
VRAMPADJ
−50
+50
mV
IRAMPADJ
5.0
60
mA
VOS(CSA)
−1.0
+1.0
mV
Current Sense Amplifier
Offset Voltage
CSSUM − CSREF (refer to Figure 5)
Input Bias Current, CSREF
CSREF = 1.0 V
IBIAS(CSREF)
−20
+20
mA
Input Bias Current, CSSUM
CSREF = 1.0 V
IBIAS(CSSUM)
−10
+10
nA
Gain Bandwidth Product
CSSUM = CSCOMP
Slew Rate
CCSCOMP = 10 pF
Input Common−Mode Range
CSSUM and CSREF
GBW(CSA)
Output Voltage Range
Output Current
Current Limit Latchoff Delay Time
ICSCOMP
Internal Timer
10
MHz
10
V/ms
0
3.0
V
0.05
3.0
V
500
mA
8.0
ms
1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
2. Refer to Application Information section.
3. Values based on design and/or characterization.
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6
NCP4208
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN − GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 1 and 2)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
0.3
V
PSI
Input Low Voltage
Input High Voltage
0.8
Input Current
−5.0
Assertion Timing
Fsw = 300kHz
De−assertion Timing
Fsw = 300kHz
mA
3.3
ms
825
ns
IMON
Clamp Voltage
Accuracy
10 x (CSREF − CSCOMP) / RILIM
1.0
1.15
V
−3.0
3.0
%
Output Current
Offset
−6.0
800
mA
6.0
mV
Current Limit Comparator
ILIM Bias Current
CSREF − CSCOMP / RILIM,
CSREF − CSCOMP = 150 mV, RILIMC = 7.5 kW
ILIM
20
mA
Current Limit Threshold Current
4/3 x IIREF
ICL
20
mA
Current Balance Amplifier
Common−Mode Range
VSW(X)CM
−600
RSW(X)
14
19
ISW(X)
7.0
12
DISW(X)
−6.0
+200
mV
25
kW
20
mA
+6.0
%
Input Resistance
SW(X) = 0 V
Input Current
SW(X) = 0 V
Input Current Matching
SW(X) = 0 V
Phase Balance Adj. Range Low
Phase Bal Registers = 00000
−25
%
Phase Balance Adj. Range High
Phase Bal Registers = 11111
+25
%
Internal Timer
Delay Time Register = 011
2.0
ms
Timer Range Low
Delay Time Register = 000
0.5
ms
Timer Range High
Delay Time Register = 111
4.0
ms
Internal Timer
Soft−Start Slope Register = 010
0.5
V/ms
Timer Range Low
Soft−Start Slope Register = 000
0.1
V/ms
Timer Range High
Soft−Start Slope Register = 111
1.5
V/ms
Delay Timer
Soft−Start
Enable Input
Input Low Voltage
Input High Voltage
VIL(EN)
VIH(EN)
Input Current
0.3
0.8
V
IIN(EN)
−1.0
mA
EN > 0.8 V, Internal Delay
tDELAY(EN)
2.0
ms
Output Low Voltage
IOD(SINK) = −400 mA
VOL(ODN/1)
160
Output High Voltage
IOD(SOURCE) = 400 mA
VOL(ODN/1)
Delay Time
ODN and OD1 Outputs
4.0
ODN / OD1 Pulldown Resistor
500
mV
5.0
V
60
kW
Power−Good Comparator
Undervoltage Threshold
Relative to Nominal DAC Output
Undervoltage Adj. Range Low
PWRGD_LO Register = 000
Undervoltage Adj. Range High
PWRGD_LO Register = 111
Overvoltage Threshold
Relative to DAC Output, PWRGD_Hi = 00
VPWRGD(UV)
−600
−500
−400
−500
mV
−150
VPWRGD(OV)
200
300
mV
mV
400
mV
1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
2. Refer to Application Information section.
3. Values based on design and/or characterization.
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7
NCP4208
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN − GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 1 and 2)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Power−Good Comparator
Overvoltage Adjustment Range Low
PWRGD_Hi Register = 11
Overvoltage Adjustment Range High
PWRGD_Hi Register = 00
Output Low Voltage
IPWRGD(SINK) = −4 mA
Power−Good Delay Time
During Soft−Start
VID Code Changing
VID Code Static
150
mV
300
VOL(PWRGD)
Internal Timer
150
100
Crowbar Trip Point
Crowbar Adjustment Range
Crowbar Reset Point
Relative to DAC Output, PWRGD_Hi = 00
PWRGD_Hi Limit
Relative to FBRTN
VCROWBAR
Crowbar Delay Time
VID Code Changing
VID Code Static
Overvoltage to PWM going low
tCROWBAR
Output Low Voltage
IPWM(SINK) = −400 mA
VOL(PWM)
Output High Voltage
IPWM(SOURCE) = 400 mA
VOH(PWM)
mV
300
2.0
250
200
200
150
250
300
100
250
400
300
mV
ms
ms
ns
400
300
350
mV
ms
ns
PWM Outputs
160
4.0
Duty Cycle Matching
500
mV
5.0
V
±3
%
I2C Interface
Logic High Input Voltage
VIH(SDA,SCL)
Logic Low Input Voltage
VIH(SDA,SCL)
2.1
Hysteresis
SDA Output Low Voltage
V
0.8
500
ISDA = −6 mA
VOL
Input Current
VIH; IIL
Input Capacitance
CSCL, SDA
Clock Frequency
fSCL
−1.0
mV
0.4
V
1.0
mA
5.0
SCL Falling Edge to SDA Valid Time
V
pF
400
kHz
1.0
ms
ALERT, FAULT Outputs
Output Low Voltage
IOUT = −6 mA
VOL
0.4
V
Output High Leakage Current
VOH = 5.0 V
VOH
1.0
mA
Analog / Digital Converter
Total Unadjusted Error (TUE)
±1.0
%
Differential Non−linearity (DNL)
8 Bits
1.0
LSB
Conversion Time
Averaging Enabled (32 averages)
80
ms
Supply
VCC
VCC
DC Supply Current
VSYSTEM = 13.2 V, RSHUNT = 340 W
4.70
IVCC
UVLO Turn−On Current
UVLO Threshold Voltage
VCC Rising
UVLO Turn−Off Voltage
VCC Falling
VCC3 Output Voltage
IVCC3 = 1 mA
VUVLO
5.25
5.75
V
21
26
mA
6.5
11
mA
9.0
V
4.1
VCC3
3.0
3.3
V
3.6
V
1. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25_C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
2. Refer to Application Information section.
3. Values based on design and/or characterization.
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8
NCP4208
TEST CIRCUITS
+12 V
680 W
680 W
VCC3
PWRGD
ALERT
SDA
SCL
EN
GND
NC
NC
IMON
IREF
RT
100 nF
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
SW1
SW2
SW3
SW4
SW5
SW6
ODN
OD1
SW7
SW8
NCP4208
RAMPADJ
FBRTN
COMP
FB
CSREF
CSSUM
CSCOMP
ILIMIFS
+1.25 V
+1 mF
VID6
VID7
VCC
PWM1
PWM2
PSI
VID0
VID1
VID2
VID3
VID4
VID5
8 BIT VID CODE
121 kW
1 kW
10 kW
20 kW
100 nF
Figure 4. Closed−Loop Output Voltage Accuracy
12 V
NCP4208
680W
680W
39
VCC
12 V
COMP
15
NCP4208
680W
10 kW
16
FB
680W
VCC
39
−
+
19
−
CSREF
17
+
100 nF
39 kW
18
+
−
CSCOMP
CSSUM
−
1 kW
+
VID DAC
17
1.0 V +
CSREF
1.0 V +
−
7
−
GND
7
GND
VOS =
DVFB = FBDV = 80 mV − FBDV = 0 mV
CSCOMP − 1.0 V
40
Figure 6. Positioning Voltage
Figure 5. Current Sense Amplifier VOS
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NCP4208
Theory of Operation
(TD2 in Figure 7) starts. The SS circuit uses the internal VID
DAC to increase the output voltage in 6.25 mV steps up to
the 1.1 V boot voltage.
Once the SS circuit has reached the boot voltage, the boot
voltage delay time (TD3) is started. The end of the boot
voltage delay time signals the beginning of the second
soft−start time (TD4). The SS voltage changes from the boot
voltage to the programmed VID DAC voltage (either higher
or lower) using 6.25 mV steps.
The soft− start slew rate is programmed using Bits <2:0>
of the Ton_Rise (0xD5) command code. Table 1. Soft−Start
Codes provides the soft−start values. Figure 8 shows typical
startup waveforms for the NCP4208.
The NCP4208 is an 8−phase VR11 controller; it combines
a multi−mode, fixed frequency PWM control with
multi−phase logic outputs for use in multi−phase
synchronous buck CPU core supply power converters. In
addition, the NCP4208 incorporates a serial interface to
allow the programming of key system performance
specifications and read back CPU data such as voltage,
current and power. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a
single−phase converter would place high thermal demands
on the components in the system such as the inductors and
MOSFETs.
Table 1. Soft−Start Codes
Startup Sequence
The NCP4208 follows the VR11 startup sequence shown
in Figure 7. After both the EN and UVLO conditions are
met, a programmable internal timer goes through one cycle
TD1. This delay cycle is programmed using Delay
Command, default delay = 2 ms). The first eight clock
cycles of TD2 are blanked from the PWM outputs and used
for phase detection as explained in the following section.
Then the programmable internal soft−start ramp is enabled
(TD2) and the output comes up to the boot voltage of 1.1 V.
The boot hold time is also set by the Delay Command. This
second delay cycle is called TD3. During TD3 the processor
VID pins settle to the required VID code. When TD3 is over,
the NCP4208 reads the VID inputs and soft starts either up
or down to the final VID voltage (TD4). After TD4 has been
completed and the PWRGD masking time (equal to VID
OTF masking) is finished, a third cycle of the internal timer
sets the PWRGD blanking (TD5).
The internal delay and soft−start times are programmable
using the serial interface and the Delay Command and
Soft−Start Command.
5.0 V
SUPPLY
VTT I/O
(NCP4208 EN)
VCC_CORE
VR READY
(ADP4000 PWRGD)
Soft−Start (V/msec)
000
0.3
001
0.3
010
0.5 = default
011
0.7
100
0.9
101
1.1
110
1.3
111
1.5
UVLO
THRESHOLD
0.85 V
TD3
VBOOT
(1.1 V)
TD1
V VID
Figure 8. Typical Startup Waveforms
Channel 1: CSREF, Channel 2: EN, Channel 3: PWM1
TD4
TD2
Phase Detection
50 ms
CPU
VID INPUTS
Code
VID INVALID
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the NCP4208 operates
as an 8−phase PWM controller.
To operate as a 7−phase controller connect PWM8 to VCC.
To operate as a 6−phase controller, connect PWM7 and
PWM8 to VCC. To operate as a 5−phase controller connect
PWM6, PWM7 and PWM8 to VCC. To operate as a 4−phase
controller, connect PWM5, PWM6, PWM7 and PWM8 to
VCC. To operate as a 3−phase controller, connect PWM4,
PWM5, PWM6, PWM7 and PWM8 to VCC. To operate as
TD5
VID VALID
Figure 7. System Startup Sequence for VR11
Soft−Start
The Soft−Start slope for the output voltage is set by an
internal timer. The default value is 0.5 V/msec, which can be
programmed through the I2C interface. After TD1 and the
phase detection cycle have been completed, the SS time
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NCP4208
method than peak current detection or sampling the current
across a sense element such as the low−side MOSFET. This
amplifier can be configured several ways, depending on the
objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lowest cost.
• Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor
temperature.
• Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the
CSREF pin, which is connected to the average output
voltage. The inputs to the amplifier are summed together
through resistors from the sensing element, such as the
switch node side of the output inductors, to the inverting
input CSSUM. The feedback resistor between CSCOMP
and CSSUM sets the gain of the amplifier and a filter
capacitor is placed in parallel with this resistor. The gain of
the amplifier is programmable by adjusting the feedback
resistor. This difference signal is used internally to offset the
VID DAC for voltage positioning. This different signal can
be adjusted between 50%−150% of the external value using
the I2C Loadline Calibration (0xDE) and Loadline Set
(0xDF) commands.
The difference between CSREF and CSCOMP is then
used as a differential input for the current limit comparator.
To provide the best accuracy for sensing current, the CSA
is designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors to make it
extremely accurate.
The CPU current can also be monitored over the I2C
interface. The current limit and the loadline can be
programmed over I2C interface.
a 2−phase controller connect PWM3, PWM4, PWM5,
PWM6, PWM7 and PWM8 to VCC. To operate as a 1−phase
controller connect PWM2, PWM3, PWM4, PWM5,
PWM6, PWM7 and PWM8 to VCC.
Prior to soft−start, while EN is low, the PWM8, PWM7,
PWM6, PWM5, PWM4, PWM3 and PWM2 pins sink
approximately 100 mA each. An internal comparator checks
each pin’s voltage vs. a threshold of 3.0 V. If the pin is tied
to VCC, it is above the threshold. Otherwise, an internal
current sink pulls the pin to GND, which is below the
threshold. PWM1 is low during the phase detection interval
that occurs during the first eight clock cycles of TD2. After
this time, if the remaining PWM outputs are not pulled to
VCC, the 100 mA current sink is removed, and they function
as normal PWM outputs. If they are pulled to VCC, the
100 mA current source is removed, and the outputs are put
into a high impedance state.
The PWM outputs are logic−level devices intended for
driving fast response external gate drivers such as the
ADP3121. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In
addition, more than one output can be on at the same time to
allow overlapping phases.
Master Clock Frequency
The clock frequency of the NCP4208 is set with an
external resistor connected from the RT pin to ground. The
frequency follows the graph in Figure 3. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If all phases are in use, divide by 8. If 4 phases
are in use divide by 4.
Output Voltage Differential Sensing
The NCP4208 combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error
amplifier. This maintains a worst−case specification of
±9 mV differential sensing error over its full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and FBRTN pin. FB is connected
through a resistor, RB, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 70 mA to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
Loadline Setting
The Loadline is programmable over the I2C on the
NCP4208. It is programmed using the Loadline Calibration
(0xDE) and Loadline Set (0xDF) commands. The Loadline
can be adjusted between 0% and 100% of the external RCSA.
In this example RCSA = 1 mW. RO needs to be 0.8 mW,
therefore programming the Loadline Calibration + Loadline
Set register to give a combined percentage of 80% will set
the RO to 0.8 mW.
Table 2. Loadline Commands
Code
Output Current Sensing
The NCP4208 provides a dedicated current sense
amplifier (CSA) to monitor the total output current for
proper voltage positioning vs. load current, for the IMON
output and for current limit detection. Sensing the load
current at the output gives the total real time current being
delivered to the load, which is an inherently more accurate
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Loadline (as a percentage of RCSA)
0 0000
0%
0 0001
3.226%
1 0000
51.6% = default
1 0001
53.3%
1 1110
96.7%
1 1111
100%
NCP4208
Current Limit Setpoint
reference input voltage directly to tell the error amplifier
where the output voltage should be. This allows enhanced
feed−forward response.
The current limit threshold on the NCP4208 is
programmed by a resistor between the IILIMFS pin and the
CSCOMP pin. The IILIMFS current, IILIMFS, is compared
with an internal current reference of 20 mA. If IILIMFS
exceeds 20 mA then the output current has exceeded the limit
and the current limit protection is tripped.
I ILIMFS +
V ILIMFS * V CSCOMP
R ILIMFS
Output Current Monitor
IMON is an analog output from the NCP4208 representing
the total current being delivered to the load. It outputs an
accurate current that is directly proportional to the current
set by the ILIMFS resistor. The current is then run through a
parallel RC connected from the IMON pin to the FBRTN pin
to generate an accurately scaled and filtered voltage as per
the VR11.1 specification. The size of the resistor is used to
set the IMON scaling.
(eq. 1)
Where VILIMFS = VCSREF
I ILIMFS +
V CSREF * V CSCOMP
R ILIMFS
R
V CSREF * V CSCOMP + CS
R PH
(eq. 2)
RL
I IMON + 10
I LOAD
R CSA +
i.e. the external circuit is set up for a 1 mW Loadline then
the RILIMFS is calculated as follows:
I ILIMFS +
1 mW I LOAD
R ILIMIFS
(eq. 4)
Assuming we want a current limit of 150 A that means that
ILIMFS must equal 20 mA at that load.
1 mW 150 AD
20 mA +
+ 7.5 kW
R ILIMIFS
Current Limit (% of External Limit)
50%
0 0001
53.3%
1 0000
100% = default
1 0001
103.3%
1 1110
143.3%
1 1111
146.7%
(eq. 7)
The NCP4208 has individual inputs (SW1 to SW8) for
each phase that are used for monitoring the current of each
phase. This information is combined with an internal ramp
to create a current balancing feedback system that has been
optimized for initial current balance accuracy and dynamic
thermal balancing during operation. This current balance
information is independent of the average output current
information used for positioning as described in the Output
Current Sensing section.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the
supply voltage for feed−forward control for changes in the
supply. A resistor connected from the power input voltage
to the RAMPADJ pin determines the slope of the internal
PWM ramp.
The balance between the phases can be programmed using
the I2C Phase Bal SW(x) commands (0xE3 to 0xEA).
This allows each phase to be adjusted if there is a
difference in temperature due to layout and airflow
considerations. The phase balance can be adjusted from a
default gain of 5 (Bits 4:0 = 10000). The minimum gain
programmable is 3.75 (Bits 4:0 = 00000) and the maximum
gain is 6.25 (Bits 4:0 = 11111).
(eq. 5)
Table 3. Current Limit
0 0000
RCS
Current Control Mode and Thermal Balance
Solving this equation for RLIMITFS we get 7.5 kW.
The current limit threshold can be modified from the
resistor programmed value by using the I2C interface using
Bits <4:0> of the Current Limit Threshold command
(0xE2). The limit is programmable between 50% of the
external limit and 146.7% of the external limit. The
resolution is 3.3%. Table 3 gives some examples codes.
Code
DCR(inductor)
R PH
If the IMON and the OCP need to be changed based on the
TDC of the CPU, then the ILIMFS resistor is the only
component that needs to be changed. If the IMON scaling is
the only change needed then changing the IMON resistor
accomplishes this.
The IMON pin also includes an active clamp to limit the
IMON voltage to 1.15 V MAX while maintaining 900 mV
MIN full scale accurate reporting.
(eq. 3)
R L + 1 mW
(eq. 6)
and
Where RL = DCR of the Inductor.
Assuming that:
R CS
R PH
R CSA I LOAD
R ILIMFS
Active Impedance Control Mode
For controlling the dynamic output voltage droop as a
function of output current, the CSA gain and loadline
programming can be scaled to be equal to the droop
impedance of the regulator times the output current. This
droop voltage is then used to set the input control voltage to
the system. The droop voltage is subtracted from the DAC
Voltage Control Mode
A high gain, high bandwidth, voltage mode error
amplifier is used for the voltage mode control loop. The
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NCP4208
CROWBAR event. Each VID change resets the internal
timer.
If a VID off code is detected the NCP4208 will wait for
5 msec to ensure that the code is correct before initiating a
shutdown of the controller.
The NCP4208 also uses the TON_Transition (0xD6) to
limit the DVID slew rates. These can be encountered when
the system does a large single VID step for power state
changes, thus the DVID slew rate needs to be limited to
prevent large inrush currents.
The transition slew rate is programmed using Bits <2:0>
of the Ton_Transition (0xD6) command code. Table 5
provides the transition rate values.
control input voltage to the positive input is set via the VID
logic according to the voltages listed in Table 8. The VID
code is set using the VID Input pins or it can be programmed
over the I2C using the VOUT_Command. By default, the
NCP4208 outputs a voltage corresponding to the VID
Inputs. To output a voltage following the VOUT_Command
the user first needs to program the required VID Code. Then
the VID_EN Bits need to be enabled. The following is the
sequence:
1. Program the required VID Code to the
VOUT_Command code (0x21).
2. Set the VID_EN bit (Bit 3) in the VR Config 1A
(0xD2) and on the VR Config 1B (0xD3).
This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location
with Resistor RB and is used for sensing and controlling the
output voltage at this point. A current source (equal to IREF)
from the FB pin flowing through RB is used for setting the
no load offset voltage from the VID voltage. The no load
voltage is negative with respect to the VID DAC for Intel
CPU’s. The main loop compensation is incorporated into the
feedback network between FB and COMP.
An offset voltage can be added to the control voltage over
the serial interface. This is done using Bits <5:0> of the
VOUT_CAL (0xDD) Command. The max offset that can be
applied is ±200 mV. The LSB size id 6.25 mV. A positive
offset is applied when Bit 5 = 0. A negative offset is applied
when Bit 5 = 1.
Table 5. Transition Rate Codes
OFFSET VOLTAGE
0 0001
+6.25 mV
0 0010
+12.5 mV
0 0011
+18.75 mV
Transition Rate (V/msec)
000
1
001
3
010
5 = default
011
7
100
9
101
11
110
13
111
15
Enhanced transient Mode
The NCP4208 incorporates enhanced transient response
for both load step up and load release. For load step up it
senses the output of the error amp to determine if a load step
up has occurred and then sequences on the appropriate
number of phases to ramp up the output current.
For load release, it also senses the output of the error amp
and uses the load release information to trigger the TRDET
pin, which is then used to adjust the error amp feedback for
optimal positioning. This is especially important during
high frequency load steps.
Additional information is used during load transients to
ensure proper sequencing and balancing of phases during
high frequency load steps as well as minimizing the stress on
components such as the input filter and MOSFET’s.
Table 4. Offset Codes
VOUT_Cal CODE
Code
Dynamic VID
The NCP4208 has the ability to dynamically change the
VID inputs while the controller is running. This allows the
output voltage to change while the supply is running and
supplying current to the load. This is commonly referred to
as Dynamic VID (DVID). A DVID can occur under either
light or heavy load conditions. The processor signals the
controller by changing the VID inputs (or by programming
a new VOUT_Command) in a single or multiple steps from
the start code to the finish code. This change can be positive
or negative.
When a VID bit changes state, the NCP4208 detects the
change and ignores the DAC inputs for a minimum of 200 ns.
This time prevents a false code due to logic skew while the
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for
a minimum of 100 ms to prevent a false PWRGD or
Current Reference
The IREF pin is used to set an internal current reference.
This reference current sets IFB. A resistor to ground
programs the current based on the 1.8 V output.
I REF +
1.8 V
R IREF
(eq. 8)
Typically, RIREF is set to 121 kW to program IREF = 15 mA.
Internal Delay Timer
The delay times for the startup timing sequence are set by
an internal timer. The default time is 2 msec which can be
changed through the I2C interface. This timer is used for
multiple delay timings (TD1, TD3, and TD5) during the
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NCP4208
This secondary current limit limits controls of the internal
COMP voltage to the PWM comparators to 1.5 V. This
limits the voltage drop across the low−side MOSFETs
through the current balance circuitry. Typical overcurrent
latchoff waveforms are shown in Figure 9.
startup sequence. Also, it is used for timing the current limit
latchoff as explained in the Current Limit section. The
current limit timer is set to 4 times the delay timer.
The delay timer is programmed using Bits <2:0> of the
Ton Delay command (0xD4). The delay can be programmed
between 0.5 msec and 4 msec. Table 6 provides the
programmable delay values.
Table 6. Delay Codes
Code
Delay (msec)
000
0.5
001
1
010
1.5
011
2 = default
100
2.5
101
3
110
3.5
111
4
Current Limit, Short−Circuit and Latchoff Protection
The NCP4208 compares a programmable current limit set
point to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor
from the ILIMFS pin to CSCOMP, and can be adjusted using
the I2C interface.
The current limit threshold can be modified from the
resistor programmed value by using the I2C interface using
Bits <4:0> of the Current Limit Threshold command
(0xE2). The limit is programmable between 50% of the
external limit and 146.7% of the external limit. The
resolution is 3.3%. The current limit threshold can be
modified from the resistor programmed value by using the
serial interface.
If the limit is reached and TD5 has completed, an internal
latchoff delay time will start, and the controller will shut
down if the fault is not removed. This delay is four times
longer than the delay time during the startup sequence. The
current limit delay time only starts after the TD5 has
completed. If there is a current limit during startup, the
NCP4208 will go through TD1 to TD5, and then start the
latchoff time. As the controller continues to cycle the phases
during the latchoff delay time, if the short is removed before
the timer is complete, the controller can return to normal
operation.
The latchoff function can be reset by either removing and
reapplying the supply voltage to the NCP4208, or by
toggling the EN pin low for a short time.
The OCP latchoff function can be disabled by using the
I2C interface. Setting the CLIM_EN bit (bit 1) of the VR
Config 1A (0xD2) and VR Config 1B (0xD3) registers to 0
disables the current limit latchoff function. The NCP4208
can continue to operate in current limit indefinitely.
During startup when the output voltage is below 200 mV,
a secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
Figure 9. Overcurrent Latchoff Waveforms
Channel 1: CSREF, Channel 2: COMP,
Channel 3: PWM1
An inherent per phase current limit protects individual
phases if one or more phases stops functioning because of a
faulty component. This limit is based on the maximum
normal mode COMP voltage.
Power Good Monitoring
The power good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open−drain
output whose high level (when connected to a pullup
resistor) indicates that the output voltage is within the
nominal limits specified in the specifications above based on
the VID voltage setting. PWRGD goes low if the output
voltage is outside of this specified range, if the VID DAC
inputs are in no CPU mode, or whenever the EN pin is pulled
low. PWRGD is blanked during a DVID event for a period
of 100 ms to prevent false signals during the time the output
is changing.
The PWRGD circuitry also incorporates an initial turn−on
delay time (TD5). Prior to the SS voltage reaching the
programmed VID DAC voltage and the PWRGD masking
time finishing, the PWRGD pin is held low. Once the SS
circuit reaches the programmed DAC voltage, the internal
timer operates.
The value for the PWRGD high limit and low limit can be
programmed using the serial interface.
Power State Indicator
The PSI pin is an input used to determine the operating
state of the load. If this input is pulled low, the load is in a low
power state and the controller asserts the ODN pin low,
which can be used to disable phases and maintain better
efficiency at lighter loads.
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NCP4208
action stops once the output voltage falls below the release
threshold of approximately 300 mV.
The value for the crowbar limit follows the programmable
PWRGD high limit.
Turning on the low−side MOSFETs pulls down the output
as the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high−side MOSFET, this
action current limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.
The sequencing into and out of low power operation is
maintained to minimize output deviations as well as
providing full power load transients immediately after
exiting a low power state. The number of phases switched on
when PSI is asserted is set using Bits 7:6 of the Manufacturer
Config Register 0x03. Table 7 shows which phases are
enabled for each configuration.
Table 7. Configuration and Enabled Phases
# Phases
Running
Normally
8
7
6
5
4
3
2
1
Code
# Phases
Running
During
PSI
Current
Limit
Divided by:
00
1
4
1
01
2
4
1 and 5
10
4
2
1, 3, 5, 7
Output Enable and UVLO
Phases
Running
11
4
2
1, 3, 5, 7
00
1
4
1
01
1
4
1
10
1
2
1
11
1
2
1
00
1
4
1
01
2
3
1 and 4
10
3
2
1, 3, 5
11
1
2
1, 3, 5
00
1
4
1
01
1
2
1
10
1
2
1
11
1
2
1
00
1
4
1
01
1
2
1
10
1
2
1
11
1
2
1
00
1
3
1
01
1
2
1
10
1
2
1
11
1
2
1
00
1
2
1
01
1
2
1
10
1
2
1
11
1
2
1
00
1
1
1
01
1
1
1
10
1
1
1
11
1
1
1
For the NCP4208 to begin switching, the input supply
current to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.8 V
threshold. This initiates a system startup sequence. If either
UVLO or EN is less than their respective thresholds, the
NCP4208 is disabled. This holds the PWM outputs at
ground and forces PWRGD, ODN and OD1 signals low.
In the application circuit (see Figure 2), the OD1 pin
should be connected to the OD inputs of the external drivers
for the phases that are always on. The ODN pin should be
connected to the OD inputs of the external drivers on the
phases that are shut down during low power operation.
Grounding the driver OD inputs disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important in preventing the discharge of the output
capacitors when the controller is shut off. If the driver
outputs are not disabled, a negative voltage can be generated
during output due to the high current discharge of the output
capacitors through the inductors.
The NCP4208 uses a shunt to generate 5.0 V from the
12 V supply range. A trade-off can be made between the
power dissipated in the shunt resistor and the UVLO
threshold. Figure 10 shows the typical resistor value needed
to realize certain UVLO voltages. It also gives the maximum
power dissipated in the shunt resistor for these UVLO
voltages.
0.325
400
0.3
350
0.275
300
0.25
250
0.225
200
0.2
0.175
150
8
Output Crowbar
9
10
11
12
13
ICC (UVLO)
As part of the protection for the load and output
components of the supply, the PWM outputs are driven low
(turning on the low−side MOSFETs) when the output
voltage exceeds the upper crowbar threshold. This crowbar
14
15
16
Rshunt
Pshunt
2−0603 Limit
2−0805 Limit
Figure 10. Typical Shunt Resistor Value and Power
Dissipation for Different UVLO Voltage
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15
NCP4208
I2C Interface
two bytes. The command code or register address
determines the number of bytes to be read or written,
See the register map for more information.
To write data to one of the device data registers or
read data from it, the address pointer register must
be set so that the correct data register is addressed
(i.e. command code), and then data can be written to
that register or read from it. The first byte of a read
or write operation always contains an address that is
stored in the address pointer register. If data is to be
written to the device, the write operation contains a
second data byte that is written to the register
selected by the address pointer register.
This write byte operation is shown in Figure 12. The
device address is sent over the bus, and then R/W is
set to 0. This is followed by two data bytes. The first
data byte is the address of the internal data register
to be written to, which is stored in the address
pointer register. The second data byte is the data to
be written to the internal data register.
2. The read byte operation is shown in Figure 13. First
the command code needs to be written to the
NCP4208 so that the required data is sent back.
This is done by performing a write to the NCP4208
as before, but only the data byte containing the
register address is sent, because no data is written to
the register. A repeated start is then issued and a
read operation is then performed consisting of the
serial bus address; R/W bit set to 1, followed by the
data byte read from the data register.
Control of the NCP4208 is carried out using the I2C
Interface. The NCP4208 SMBus address is 0x20
(010 0000). With the R/W bit set to 0 this gives an 8 bit
address of 0x40.
Data is sent over the serial bus in sequences of nine clock
pulses: 8 bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low−to−high transition
when the clock is high might be interpreted as a stop signal.
The number of data bytes that can be transmitted over the
serial bus in a single read or write operation is limited only
by what the master and slave devices can handle.
1. When all data bytes have been read or written, stop
conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read mode,
the master device overrides the acknowledge bit by
pulling the data line high during the low period
before the ninth clock pulse; this is known as No
Acknowledge. The master takes the data line low
during the low period before the tenth clock pulse,
and then high during the tenth clock pulse to assert
a stop condition.
Any number of bytes of data can be transferred over
the serial bus in one operation, but it is not possible
to mix read and write in one operation because the
type of operation is determined at the beginning and
cannot subsequently be changed without starting a
new operation.
In the NCP4208, write operations contain one, two
or three bytes, and read operations contain one or
1
9
9
1
SCL
0
SDA
1
START BY MASTER
0
0
0
0
0
FRAME 1
SERIAL BUS ADDRESS
BYTE
D7
R/W
D6
D5
D4
D3
D2
ACK. BY NCP4208
D1
D0
STOP BY
MASTER
ACK. BY NCP4208
FRAME 2
COMMAND CODE
Figure 11. Send Byte
1
9
9
1
SCL
SDA
START BY
MASTER
0
1
0
0
0
0
0
D7
R/W
D6
D5
D4
D3
D2
D1
FRAME 1
SERIAL BUS ADDRESS
BYTE
D0
ACK. BY
NCP4208
ACK. BY
NCP4208
FRAME 2
COMMAND CODE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
Figure 12. Write Byte
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16
D6
D5
D4
D3
FRAME 3
D ATA
BYTE
D2
D1
D0
ACK. BY
NCP4208
STOP BY
MASTER
NCP4208
1
9
9
1
SCL
SDA
0
1
0
0
START BY
MASTER
0
0
0
D6
D7
R/W
D4
D5
D3
D2
D1
D0
ACK. BY
NCP4208
FRAME 1
SERIAL BUS ADDRESS
BYTE
ACK. BY
NCP4208
FRAME 2
COMMAND CODE
1
9
1
9
SCL
0
SDA
1
0
REPEATED START
BY MASTER
0
0
0
0
D6
D7
R/W
D4
D5
ACK. BY
NCP4208
FRAME 1
SERIAL BUS ADDRESS
BYTE
D3
D2
D1
D0
NO ACK. BY
MASTER
FRAME 2
DATA BYTE
FROM NCP4208
STOP BY
MASTER
Figure 13. Read Byte
3. It is not possible to read or write a data byte from a
data register without first writing to the address
pointer register, even if the address pointer register
is already at the correct value.
4. In addition to supporting the send byte, the
NCP4208 also supports the read byte, write byte,
read word and write word protocols.
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device as follows: The master
device asserts a start condition on SDA.
1. The master sends the 7−bit slave address followed
by the write bit (low).
2. The addressed slave device asserts ACK on SDA.
3. The master sends a command code.
4. The slave asserts ACK on SDA.
5. The master sends a data byte.
6. The slave asserts ACK on SDA.
7. The master asserts a stop condition on SDA and
the transaction ends.
The byte write operation is shown Figure 15.
Write Operations
The following abbreviations are used in the diagrams:
S—START
P—STOP
R—READ
W—WRITE
A—ACKNOWLEDGE
A—NO ACKNOWLEDGE
The NCP4208 uses the following I2C write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
For the NCP4208, the send byte protocol is used to clear
Faults. This operation is shown in Figure 14.
1
2
3
SLAVE
S
W A
ADDRESS
4
5 6
COMMAND
CODE
A P
1
2
3
SLAVE
S
W A
ADDRESS
4
COMMAND
CODE
5
6
7
8
A DATA A P
Figure 15. Single Byte Write to a Register
Write Word
In this operation, the master device sends a command byte
and two data bytes to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
Figure 14. Send Byte Command
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NCP4208
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on
SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the Data Byte.
10. The master asserts NO ACK on SDA.
11. The master asserts a stop condition on SDA and
the transaction ends.
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the first data byte.
7. The slave asserts ACK on SDA.
8. The master sends the second data byte.
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA and
the transaction ends.
The word write operation is shown in Figure 16.
1
2
3
SLAVE
S
W A
ADDRESS
4
5
COMMAND
CODE
6
7
8
9 10
DATA
DATA
A
A
A P
(LSB)
(MSB)
1
2
Figure 16. Single Word Write to a Register
In this operation, the master device sends a command byte
and a byte count followed by the stated number of data bytes
to the slave device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the byte count N
7. The slave asserts ACK on SDA.
8. The master sends the first data byte
9. The slave asserts ACK on SDA.
10. The master sends the second data byte.
11. The slave asserts ACK on SDA.
12. The master sends the remainder of the data byes.
13. The slave asserts an ACK on SDA after each data
byte.
14. After the last data byte the master asserts a STOP
condition on SDA.
S
2
4
5
COMMAND
CODE
6
8
7
9
10 11
SLAVE
A S
R A DATA A
ADDRESS
P
Figure 18. Single Byte Read from a Register
Block Write
1
3
SLAVE
S
W A
ADDRESS
3
SLAVE
W A
ADDRESS
4
5
COMMAND
CODE
A
10
11
DATA
BYTE 2
A
...
...
6
7
BYTE COUNT
A
=N
12
DATA
BYTE N
13
A
8
Read Word
In this operation, the master device receives two data
bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the first Data Byte (low Data Byte).
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data
Byte).
12. The masters asserts a No ACK on SDA
13. The master asserts a stop condition on SDA and
the transaction ends.
1
9
2
3
SLAVE
S
W A
ADDRESS
DATA
A
BYTE 1
4
COMMAND
CODE
5
6
7
8
11
14
9
10
SLAVE
DATA
A S
R A
A
ADDRESS
(LSB)
12 13
DATA
A P
(MSB)
P
Figure 19. Word Read from a Command Coder
In this operation, the master device sends a command
byte, the slave sends a byte count followed by the stated
number of data bytes to the master device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition
on SDA.
Figure 17. Block Write to a Register
Read Operations
The NCP4208 uses the following I2C read protocols.
Read Byte
In this operation, the master device receives a single byte
from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
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NCP4208
5. The master sends the 7−bit slave address followed
by the read bit (high).
6. The slave asserts ACK on SDA.
7. The slave sends the byte count N.
8. The master asserts ACK on SDA.
9. The slave sends the first data byte.
10. The master asserts ACK on SDA.
11. The slave sends the remainder of the data byes, the
master asserts an ACK on SDA after each data byte.
12. After the last data byte the master asserts a No ACK
on SDA.
13. The master asserts a STOP condition on SDA.
1
2
3
4
5
6
7
SLAVE
SLAVE
BYTE COUNT
S
W A S
R A
ADDRESS
ADDRESS
=N
8
9
10
A
DATA
BYTE 1
A
...
11
12 13
DATA
BYTE N
A P
Figure 20. Block Write to a Command Coder
I2C Timeout
The NCP4208 includes a I2C timeout feature. If there is
no I2C activity for 35 ms, the NCP4208 assumes that the
bus is locked and releases the bus. This prevents the
device from locking or holding the I2C expecting data.
The timeout feature can be disabled.
Configuration Register 1 (0xD1)
Bit 3 BUS_TO_EN = 1; Bus timeout enabled.
Table 8. VR11 and VR10.x VID CODES for the NCP4208
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
OFF
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
1.60000
0
0
0
0
0
0
1
0
1.59375
0
0
0
0
0
0
1
1
1.58750
0
0
0
0
0
1
0
0
1.58125
0
0
0
0
0
1
0
1
1.57500
0
0
0
0
0
1
1
0
1.56875
0
0
0
0
0
1
1
1
1.56250
0
0
0
0
1
0
0
0
1.55625
0
0
0
0
1
0
0
1
1.55000
0
0
0
0
1
0
1
0
1.54375
0
0
0
0
1
0
1
1
1.53750
0
0
0
0
1
1
0
0
1.53125
0
0
0
0
1
1
0
1
1.52500
0
0
0
0
1
1
1
0
1.51875
0
0
0
0
1
1
1
1
1.51250
0
0
0
1
0
0
0
0
1.50625
0
0
0
1
0
0
0
1
1.50000
0
0
0
1
0
0
1
0
1.49375
0
0
0
1
0
0
1
1
1.48750
0
0
0
1
0
1
0
0
1.48125
0
0
0
1
0
1
0
1
1.47500
0
0
0
1
0
1
1
0
1.46875
0
0
0
1
0
1
1
1
1.46250
0
0
0
1
1
0
0
0
1.45625
0
0
0
1
1
0
0
1
1.45000
0
0
0
1
1
0
1
0
1.44375
0
0
0
1
1
0
1
1
1.43750
0
0
0
1
1
1
0
0
1.43125
0
0
0
1
1
1
0
1
1.42500
0
0
0
1
1
1
1
0
1.41875
0
0
0
1
1
1
1
1
1.41250
0
0
1
0
0
0
0
0
1.40625
0
0
1
0
0
0
0
1
1.40000
0
0
1
0
0
0
1
0
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NCP4208
Table 8. VR11 and VR10.x VID CODES for the NCP4208
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1.39375
0
0
1
0
0
0
1
1
1.38750
0
0
1
0
0
1
0
0
1.38125
0
0
1
0
0
1
0
1
1.37500
0
0
1
0
0
1
1
0
1.36875
0
0
1
0
0
1
1
1
1.36250
0
0
1
0
1
0
0
0
1.35625
0
0
1
0
1
0
0
1
1.35000
0
0
1
0
1
0
1
0
1.34375
0
0
1
0
1
0
1
1
1.33750
0
0
1
0
1
1
0
0
1.33125
0
0
1
0
1
1
0
1
1.32500
0
0
1
0
1
1
1
0
1.31875
0
0
1
0
1
1
1
1
1.31250
0
0
1
1
0
0
0
0
1.30625
0
0
1
1
0
0
0
1
1.30000
0
0
1
1
0
0
1
0
1.29375
0
0
1
1
0
0
1
1
1.28750
0
0
1
1
0
1
0
0
1.28125
0
0
1
1
0
1
0
1
1.27500
0
0
1
1
0
1
1
0
1.26875
0
0
1
1
0
1
1
1
1.26250
0
0
1
1
1
0
0
0
1.25625
0
0
1
1
1
0
0
1
1.25000
0
0
1
1
1
0
1
0
1.24375
0
0
1
1
1
0
1
1
1.23750
0
0
1
1
1
1
0
0
1.23125
0
0
1
1
1
1
0
1
1.22500
0
0
1
1
1
1
1
0
1.21875
0
0
1
1
1
1
1
1
1.21250
0
1
0
0
0
0
0
0
1.20625
0
1
0
0
0
0
0
1
1.20000
0
1
0
0
0
0
1
0
1.19375
0
1
0
0
0
0
1
1
1.18750
0
1
0
0
0
1
0
0
1.18125
0
1
0
0
0
1
0
1
1.17500
0
1
0
0
0
1
1
0
1.16875
0
1
0
0
0
1
1
1
1.16250
0
1
0
0
1
0
0
0
1.15625
0
1
0
0
1
0
0
1
1.15000
0
1
0
0
1
0
1
0
1.14375
0
1
0
0
1
0
1
1
1.13750
0
1
0
0
1
1
0
0
1.13125
0
1
0
0
1
1
0
1
1.12500
0
1
0
0
1
1
1
0
1.11875
0
1
0
0
1
1
1
1
1.11250
0
1
0
1
0
0
0
0
1.10625
0
1
0
1
0
0
0
1
1.10000
0
1
0
1
0
0
1
0
1.09375
0
1
0
1
0
0
1
1
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NCP4208
Table 8. VR11 and VR10.x VID CODES for the NCP4208
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1.08750
0
1
0
1
0
1
0
0
1.08125
0
1
0
1
0
1
0
1
1.07500
0
1
0
1
0
1
1
0
1.06875
0
1
0
1
0
1
1
1
1.06250
0
1
0
1
1
0
0
0
1.05625
0
1
0
1
1
0
0
1
1.05000
0
1
0
1
1
0
1
0
1.04375
0
1
0
1
1
0
1
1
1.03750
0
1
0
1
1
1
0
0
1.03125
0
1
0
1
1
1
0
1
1.02500
0
1
0
1
1
1
1
0
1.01875
0
1
0
1
1
1
1
1
1.01250
0
1
1
0
0
0
0
0
1.00625
0
1
1
0
0
0
0
1
1.00000
0
1
1
0
0
0
1
0
0.99375
0
1
1
0
0
0
1
1
0.98750
0
1
1
0
0
1
0
0
0.98125
0
1
1
0
0
1
0
1
0.97500
0
1
1
0
0
1
1
0
0.96875
0
1
1
0
0
1
1
1
0.96250
0
1
1
0
1
0
0
0
0.95625
0
1
1
0
1
0
0
1
0.95000
0
1
1
0
1
0
1
0
0.94375
0
1
1
0
1
0
1
1
0.93750
0
1
1
0
1
1
0
0
0.93125
0
1
1
0
1
1
0
1
0.92500
0
1
1
0
1
1
1
0
0.91875
0
1
1
0
1
1
1
1
0.91250
0
1
1
1
0
0
0
0
0.90625
0
1
1
1
0
0
0
1
0.90000
0
1
1
1
0
0
1
0
0.89375
0
1
1
1
0
0
1
1
0.88750
0
1
1
1
0
1
0
0
0.88125
0
1
1
1
0
1
0
1
0.87500
0
1
1
1
0
1
1
0
0.86875
0
1
1
1
0
1
1
1
0.86250
0
1
1
1
1
0
0
0
0.85625
0
1
1
1
1
0
0
1
0.85000
0
1
1
1
1
0
1
0
0.84375
0
1
1
1
1
0
1
1
0.83750
0
1
1
1
1
1
0
0
0.83125
0
1
1
1
1
1
0
1
0.82500
0
1
1
1
1
1
1
0
0.81875
0
1
1
1
1
1
1
1
0.81250
1
0
0
0
0
0
0
0
0.80625
1
0
0
0
0
0
0
1
0.80000
1
0
0
0
0
0
1
0
0.79375
1
0
0
0
0
0
1
1
0.78750
1
0
0
0
0
1
0
0
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21
NCP4208
Table 8. VR11 and VR10.x VID CODES for the NCP4208
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0.78125
1
0
0
0
0
1
0
1
0.77500
1
0
0
0
0
1
1
0
0.76875
1
0
0
0
0
1
1
1
0.76250
1
0
0
0
1
0
0
0
0.75625
1
0
0
0
1
0
0
1
0.75000
1
0
0
0
1
0
1
0
0.74375
1
0
0
0
1
0
1
1
0.73750
1
0
0
0
1
1
0
0
0.73125
1
0
0
0
1
1
0
1
0.72500
1
0
0
0
1
1
1
0
0.71875
1
0
0
0
1
1
1
1
0.71250
1
0
0
1
0
0
0
0
0.70625
1
0
0
1
0
0
0
1
0.70000
1
0
0
1
0
0
1
0
0.69375
1
0
0
1
0
0
1
1
0.68750
1
0
0
1
0
1
0
0
0.68125
1
0
0
1
0
1
0
1
0.67500
1
0
0
1
0
1
1
0
0.66875
1
0
0
1
0
1
1
1
0.66250
1
0
0
1
1
0
0
0
0.65625
1
0
0
1
1
0
0
1
0.65000
1
0
0
1
1
0
1
0
0.64375
1
0
0
1
1
0
1
1
0.63750
1
0
0
1
1
1
0
0
0.63125
1
0
0
1
1
1
0
1
0.62500
1
0
0
1
1
1
1
0
0.61875
1
0
0
1
1
1
1
1
0.61250
1
0
1
0
0
0
0
0
0.60625
1
0
1
0
0
0
0
1
0.60000
1
0
1
0
0
0
1
0
0.59375
1
0
1
0
0
0
1
1
0.58750
1
0
1
0
0
1
0
0
0.58125
1
0
1
0
0
1
0
1
0.57500
1
0
1
0
0
1
1
0
0.56875
1
0
1
0
0
1
1
1
0.56250
1
0
1
0
1
0
0
0
0.55625
1
0
1
0
1
0
0
1
0.55000
1
0
1
0
1
0
1
0
0.54375
1
0
1
0
1
0
1
1
0.53750
1
0
1
0
1
1
0
0
0.53125
1
0
1
0
1
1
0
1
0.52500
1
0
1
0
1
1
1
0
0.51875
1
0
1
0
1
1
1
1
0.51250
1
0
1
1
0
0
0
0
0.50625
1
0
1
1
0
0
0
1
0.50000
1
0
1
1
0
0
1
0
OFF
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
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22
NCP4208
Table 9. I2C Commands for the NCP4208
Cmd
Code
R/W
Default
0x01
R/W
0x80
Operation
1
0x02
R/W
0x17
ON_OFF_Config
1
Description
#
Bytes
Comment
00xx xxxx – Immediate Off
01xx xxxx – Soft Off
1000 xxxx – On (slew rate set by soft−start) − Default
1001 01xx – Margin Low (Ignore Fault)
1001 10xx – Margin Low (Act on Fault)
1010 01xx – Margin High (Ignore Fault)
1010 10xx – Margin High (Act on Fault)
Configures how the controller is turned on and off.
Bit
Default
7:5
000
Comment
4
1
This bit is read only. Switching starts when
commanded by the Control Pin and the
Operation Command, as set in Bits 3:0.
3
0
0: Unit ignores OPERATION commands over
the I2C interface
1: Unit responds to OPERATION command,
powerup may also depend upon Control input,
as described in Bit 2
2
1
0: Unit ignores EN pin
1: Unit responds EN pin, powerup may also
depend upon the Operation Register, as
described for Bit 3
1
1
Control Pin polarity
0 = Active Low
1 = Active High
0
1
This bit is read only.
1: means that when the controller is disabled it
will either immediately turn off or soft off (as set
in the Operation Command)
Reserved for Future Use
0x03
W
NA
Clear_Faults
0
Writing any value to this command code will clear all Status Bits
immediately. The SMBus ALERT is deasserted on this command. If the
fault is still present the fault bit shall immediately be asserted again.
0x10
R/W
0x00
Write Protect
1
The Write_Protect command is used to control writing to the I2C
device. There is also a lock bit in the Manufacture Specific Registers
that once set will disable writes to all commands until the power to
the NCP4208 is cycled.
Data Byte
0x19
R
0xB0
Capability
1
Comment
1000 0000
Disables all writes except to the Write_Protect
Command
0100 0000
Disables all writes except to the Write_Protect
and Operation Commands
0010 0000
Disables all writes except to the Write_Protect,
Operation, ON_OFF_Config and
VOUT_COMMAND Commands
0000 0000
Enables writes to all commands
0001 0000
Disables all writes except to
WRITE_PROTECT, PAGE and all
MFR−SPECIFIC Commands
This command allows the host to get some information on the I2C
device.
Bit
Default
7
1
PEC (Packet Error Checking is supported)
Comment
6:5
01
Max supported bus speed is 400 kHz
4
1
NCP4208 has an SMBus ALERT pin and ARA
is supported
3:0
000
Reserved for future use
0x20
R
0x20
VOUT_MODE
1
The NCP4208 supports VID mode for programming the output voltage.
0x21
R/W
0x00
VOUT_COMMAND
2
Sets the output voltage using VID.
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23
NCP4208
Cmd
Code
R/W
Default
0x25
R/W
0x0020
VOUT_MARGIN_HIGH
2
Sets the output voltage when operation command is set to Margin
High. Programmed in VID Mode.
0x26
R/W
0x00B2
VOUT_MARGIN_LOW
2
Sets the output voltage when operation command is set to Margin
Low. Programmed in VID Mode.
0x38
R/W
0x0001
IOUT_CAL_GAIN
2
Sets the ratio of voltage sensed to current output. Scale is Linear
and is expressed in 1/W
0x39
R/W
0x0000
IOUT_CAL_OFFSET
2
This offset is used to null out any offsets in the output current
sensing circuitry. Units are Amps
0x4A
R/W
0x0064
IOUT_OC_WARN_LIMIT
2
This sets the high current limit. Once this limit is exceeded
IOUT_OC_WARN_LIMIT bit is set in the Status_IOUT register and
an ALERT is generated. This limit is set in Amps.
0x6A
R/W
0x012C
POUT_OP_WARN LIMIT
2
This sets the output power over power warn limit. Once exceeded
Bit 0 of the Status IOUT Command gets set and the ALERT output
gets asserted (if not masked)
0x78
R
0x00
STATUS BYTE
1
Bit
Name
7
BUSY
A fault was declared because the NCP4208
was busy and unable to respond.
6
OFF
This bit is set whenever the NCP4208 is not
switching.
5
VOUT_OV
This bit gets set whenever the NCP4208 goes
into OVP mode.
4
IOUT_OC
This bit gets set whenever the NCP4208
latches off due to an overcurrent event.
3
VIN_UV
Not supported.
2
TEMP
Not supported.
1
CML
0
None of the
Above
Byte
Bit
Name
Low
7
Res
Reserved for future use.
Low
6
OFF
This bit is set whenever the
NCP4208 is not switching.
Low
5
VOUT_OV
This bit gets set whenever the
NCP4208 goes into OVP mode.
Low
4
IOUT_OC
This bit gets set whenever the
NCP4208 latches off due to an
overcurrent event.
Low
3
Res
Low
2
TEMP
Low
1
CML
High
0
None of the
Above
High
7
VOUT
This bit gets set whenever the
measured output voltage goes
outside its power good limits or
an OVP event has taken place,
i.e. any bit in Status VOUT is set.
Byte
Bit
Name
Description
High
6
IOUT/POUT
This bit gets set whenever the
measured output current or
power exceeds its warning limit
or goes into OCP. i.e. any bit in
Status IOUT is set.
High
5
INPUT
0x79
0x79
R
R
0x0000
0x0000
Description
STATUS WORD
STATUS WORD
#
Bytes
2
2
Comment
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24
Description
A Communications, memory or logic fault has
occurred.
A fault has occurred which is not one of the
above.
Description
Reserved for future use.
Not supported.
A Communications, memory or
logic fault has occurred.
A fault has occurred which is
not one of the above.
Not supported.
NCP4208
Cmd
Code
0x7A
0x7B
0x7E
R/W
R
R
R
Default
0x00
0x00
0x00
Description
STATUS VOUT
STATUS IOUT
STATUS CML
#
Bytes
1
1
1
Comment
High
4
MFR
A manufacturer specific
warning or fault has occurred.
High
3
POWER_
GOOD
The Power Good signal is
deasserted. Same as
PowerGood in General Status.
High
2
Res
High
1
OTHER
High
0
Res
Bit
Name
7
Res
6
VOUT_
OVER
VOLTAGE
WARNING
This bit gets set whenever the measured output
voltage goes above its powergood limit.
5
VOUT_
UNDER
VOLTAGE
WARNING
This bit gets set whenever the measured output
voltage goes below its powergood limit.
Reserved for future use.
A Status bit in Status Other is
asserted.
Reserved for future use.
Description
Not supported.
4
Res
3
VOUT_MAX
Warning
Reserved for future use.
2
Res
Not supported.
1
Res
Not supported.
0
Res
Not supported.
Bit
Name
Description
7
IOUT
Overcurrent
This bit gets set if the NCP4208 latches off due
to an OCP Event.
Not supported, Can’t program an output greater
than MAX VID as there are no bits to program it.
6
Res
5
IOUT
Overcurrent
Warning
Reserved for future use.
4
Res
Reserved for future use.
3
Res
Reserved for future use.
2
Res
Reserved for future use.
1
Res
Not supported.
0
POUT Over
Power
Warning
Fault
This bit gets set if IOUT exceeds its programmed
high warning limit.
This bit gets set if the measured POUT exceeds
the Warn Limit.
Bit
Desc.
7
Supported
Invalid or Unsupported Command Received
6
Supported
Invalid or Unsupported Data Received
5
Supported
PEC Failed
4
Not
supported
Memory Fault Detected
3
Not
supported
Processor Fault Detected
2
Supported
Reserved
1
Supported
A communication fault other than the ones
listed has occurred
0
Not
supported
Other memory or Logic Fault has occurred
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Name
NCP4208
Cmd
Code
R/W
Default
0x80
R
0x00
Description
STATUS_ALERT
#
Bytes
1
Comment
Bit
Name
7
Res
Reserved for future use.
Description
6
Res
Reserved for future use.
5
Res
Reserved for future use.
4
Res
Reserved for future use.
3
Res
Reserved for future use.
2
VMON
WARN
1
Res
Reserved for future use.
0
Res
Reserved for future use.
Gets asserted when VMON exceeds it
programmed WARN limits.
0x8B
R
0x00
READ_VOUT
2
Readback output voltage. Voltage is read back in VID Mode
0x8C
R
0x00
READ_IOUT
2
Readback output current. Current is read back in Linear Mode (Amps).
0x96
R
0x00
READ_POUT
2
Readback Output Power, read back in Linear Mode in W’s.
0x99
R
0x41
MFR_ID
1
0x9A
R
0x0208
MFR_MODEL
2
0x9B
R
0x03
MFR_REVISION
1
Table 10. Manufacturer Specific Command Codes for the NCP4208
Cmd
Code
R/W
Default
0xDO
R/W
0x00
0xD1
R/W
0x03
Description
Lock/Reset
Mfr Config
#
Bytes
1
1
Comment
Bit
Name
Description
1
Reset
Resets all registers to their POR Value. Has
no effect if Lock bit is set.
0
Lock
Logic 1 locks all limit values to their current
settings. Once this bit is set, all lockable
registers become read−only and cannot be
modified until the NCP4208 is powered down
and powered up again. This prevents rogue
programs such as viruses from modifying
critical system limit settings. (Lockable).
Bit
Name
Description
7:6
PSI
These bits sets the number of phases turned
on during PSI.
00 = CL set for 1 Phase (default)
01 = CL set for 2 Phases
10 = CL set for 3 Phases
11 = CL set for 1 Phase
5
Res
Reserved for future use.
4
ALERT Mode
1 = Comparator Mode.
3
BUS_TO_EN
Bus Timeout Enable. When the BUS_TO_EN
bit is set to 1, the I2C Timeout feature is
enabled. In this state if, at any point during an
I2C transaction involving the NCP4208, activity
ceases for more than 35 ms, the NCP4208
assumes the bus is locked and releases the
bus. This allows the NCP4208 to be used with
I2C controllers that cannot handle I2C timeouts.
(Lockable).
2
Res
Reserved for future use.
1
ALERT_EN
Enable the ALERT pin.
0
ENABLE_
MONITOR
When the ENABLE_MONITOR bit is set to 1,
the NCP4208 starts conversions with the
ADC and monitors the voltages and
temperatures.
http://onsemi.com
26
0 = ALERT Mode.
NCP4208
Cmd
Code
R/W
Default
0xD2
R/W
0x72
Description
VR Config. 1A
#
Bytes
1
Comment
Bit
Name
6:4
Phase
Enable Bits
Description
3
VID_EN
When the VID_EN bit is set to 1, the VID
code in the VOUT_COMMAND register sets
the output voltage. When VID_EN is set to 0,
the output voltage follows the VID input pins.
2
LOOP_EN
When the LOOP_EN bit is set to 1 in both
registers, the control loop test function is
enabled. This allows measurement of the
control loop AC gain and phase response
with appropriate instrumentation. The control
loop signal insertion pin is IMON. The control
loop output pin is COMP.
1
CLIM_EN
When CLIM_EN is set to 1, the current limit
time out latchoff functions normally. When
this bit is set to 0 in both registers, the
current limit latchoff is disabled. In this state,
the part can be in current limit indefinitely.
0
Res
000 = Phase 1
001 = Phase 2
010 = Phase 3
011 = Phase 4
100 = Phase 5
101 = Phase 6
110 = Phase 7
111 = Phase 8
Reserved for future use.
0xD3
R/W
0x72
VR Config. 1B
1
This register is for security reasons. It has the same format as
register 0xD2. Bits need to be set in both registers for the function
to take effect.
0xD4
R/W
0x03
Ton Delay
1
0xD5
R/W
0x02
Ton Rise
1
0xD6
R/W
0x01
Ton Transition
1
0xD7
R
0x00
VMON Voltage
2
This is a 16 bit value that reports back the voltage measured
between FB and FBRTN
0xD8
R
0x00
EN/VTT Voltage
2
This is a 16 bit value that reports back the voltage on the VTT Pin.
0xDD
R/W
0x00
VOUT_CAL
1
Offset Command Code for VOUT, max ±200 mV
0xDE
R/W
0x10
Loadline Calibration
1
This value sets the internal loadline attenuation DAC calibration
value. The maximum loadline is controlled externally by setting the
gain of the current sense amplifier as explained in the applications
section. This maximum loadline can then be adjusted from 100% to
0% in 30 steps. Each LSB represents a 3.226% change in the load
line.
00000 = No Load Line
10000 = 51.6% of external load line
11111 = 100% of external Loadline
0xDF
R/W
0x00
Loadline Set
1
This value sets the internal loadline attenuation DAC value. The
maximum loadline is controlled externally by setting the gain of the
current sense amplifier as explained in the applications section.
This maximum loadline can then be adjusted from 100% to 0% in
30 steps. Each LSB represents a 3.226% change in the load line.
00000 = No Load Line
10000 = 51.6% of external load line
11111 = 100% of external load Line
0xE0
R/W
0x00
PWRGD Hi Threshold
1
This value sets the PWRGD Hi Threshold and the CROWBAR
Threshold:
Code = 00, PWRGD HI = 300 mV (default)
Code = 01, PWRGD HI = 250 mV
Code = 10, PWRGD HI = 200 mV
Code = 11, PWRGD HI = 150 mV
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27
NCP4208
Cmd
Code
R/W
Default
0xE1
R/W
0x00
PWRGD Lo Threshold
1
This value sets the PWRGD Lo Threshold:
Code = 000, PWRGD Lo = −500 mV (default)
Code = 001, PWRGD Lo = −450 mV
Code = 010, PWRGD Lo = −400 mV
Code = 011, PWRGD Lo = −350 mV
Code = 100, PWRGD Lo = −300 mV
Code = 101, PWRGD Lo = −250 mV
Code = 110, PWRGD Lo = −200 mV
Code = 111, PWRGD Lo = −150 mV
0xE2
R/W
0x10
Current Limit Threshold
1
This value sets the internal current limit adjustment value. The
default current limit is programmed using a resistor to ground on the
LIMIT pin. The value of this register adjusts this value by a
percentage between 50% and 146.7%. Each LSB represents a
3.33% change in the current limit threshold.
11111 = 146.7% of external current limit
10000 = 100% of external current limit (default)
00000 = 50% of external current limit
0xE3
R/W
0x10
Phase Bal SW1
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE4
R/W
0x10
Phase Bal SW2
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE5
R/W
0x10
Phase Bal SW3
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE6
R/W
0x10
Phase Bal SW4
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE7
R/W
0x10
Phase Bal SW5
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE8
R/W
0x10
Phase Bal SW6
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE9
R/W
0x10
Phase Bal SW7
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xEA
R/W
0x10
Phase Bal SW8
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
Description
#
Bytes
Comment
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28
NCP4208
Cmd
Code
R/W
Default
0xF1
R
0x00
0xF6
R/W
0x0002
0xF9
R/W
0x00
0xFA
0xFB
0xFC
R/W
R
R
0x00
0x10
0x00
Description
#
Bytes
Comment
ICPU MSB
1
VMON Warn Limit
2
VMON Warn Limit
Mask ALERT
1
Bit
Name
7
Mask VOUT
Masks any ALERT caused by bits in Status
VOUT Register.
6
Mask IOUT
Masks any ALERT caused by bits in Status
IOUT Register.
Mask FAULT
General Status
Phase Status
1
1
1
5
Res
4
Mask
Temperature
3
Mask CML
2
VMON
Description
Reserved
Not Supported
Masks any ALERT caused by bits in Status
CML Register.
Masks any ALERT caused by VMON
exceeding its high or low limit.
1
Res
0
Mask POUT
Bit
Name
7
Mask VOUT
FAULT
Masks any ALERT caused by OVP.
6
Mask IOUT
FAULT
Masks any ALERT caused by OCP.
Bit
Name
6
ALERT
5
POWER
GOOD
4
RDY
Reserved
Masks any ALERT caused by POUT
exceeding its programmed limit.
Description
Description
Replaced by Bit 3 of the Status Word
Command
Bit
Name
Description
7
Phase 8
This bit is set to 1 when Phase 8 is enabled.
6
Phase 7
This bit is set to 1 when Phase 7 is enabled.
5
Phase 6
This bit is set to 1 when Phase 6 is enabled.
4
Phase 5
This bit is set to 1 when Phase 5 is enabled.
3
Phase 4
This bit is set to 1 when Phase 4 is enabled.
2
Phase 3
This bit is set to 1 when Phase 3 is enabled.
1
Phase 2
This bit is set to 1 when Phase 2 is enabled.
0
Phase 1
This bit is set to 1 when Phase 1 is enabled
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NCP4208
PACKAGE DIMENSIONS
QFN48 7x7, 0.5P
CASE 485AJ
ISSUE O
D
ÈÈÈ
ÈÈÈ
PIN 1
LOCATION
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO THE PLATED
TERMINAL AND IS MEASURED ABETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L
2X
0.15 C
DETAIL A
OPTIONAL CONSTRUCTION
2X SCALE
2X
0.15 C
TOP VIEW
(A3)
0.05 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
7.00 BSC
5.00
5.20
7.00 BSC
5.00
5.20
0.50 BSC
0.20
−−−
0.30
0.50
A
0.08 C
SOLDERING FOOTPRINT*
A1
NOTE 4
C
SIDE VIEW
D2
DETAIL A
2X
SEATING
PLANE
5.20
1
K
13
25
12
2X
7.30
48X
0.63
E2
1
48
48X
L
48X
0.30
36
37
e
e/2
48X
BOTTOM VIEW
b
0.10 C A B
0.05 C
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
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