NCP81232 D

NCP81232
Dual-Channel/Multi-Phase
Controller for DrMOS
The NCP81232, a dual−channel/multi−phase synchronous buck
controller, provides power management solutions for various
applications supported by DrMOS. It has 8 programmable
power−stage configurations, differential voltage and current sense,
flexible power sequence programming, and comprehensive
protections.
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MARKING
DIAGRAM
Features
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Vin = 4.5~20 V with Input Feedforward
Integrated 5.35 V LDO
Vout = 0.6 V ~ 5.3 V
Fsw = 200k ~ 1.2 MHz
PWM Output Compatible to 3.3 V and 5 V DrMOS
Flexible 8 Combinations of Power Stage Configurations (1~2 Output
Rails, 1~4 Phases)
DDR Power Mode Option
Interleaved Operation
Differential Output Voltage Sense
Differential Current Sense Compatible for both Inductor DCR Sense
and DrMOS Iout
2 Enables with Programmable Input UVLO
Programmable DrMOS Power Ready Detection (DRVON)
2 Power Good Indicators
Comprehensive Fault Indicator
Externally Programmable Soft Start and Delay Time
Programmable Hiccup Over Current Protection
Hiccup Under Voltage Protection
Recoverable Over Voltage Protection
Hiccup Over Temperature Protection
Thermal Shutdown Protection
QFN−40, 5x5 mm, 0.4 mm Pitch Package
This is a Pb−Free Device
1
1
40
TBD
YYWWAG
QFN40
CASE 485CR
A
YY
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping†
NCP81232MNTXG
QFN40
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Typical Applications
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Telecom Applications
Server and Storage System
Multiple Rail Systems
DDR Applications
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 0
1
Publication Order Number:
NCP81232/D
40
39
38
37
36
35
34
33
32
31
VCC5V
VREF
ILMT1
OTP1
COMP1
FB1
DIFFOUT1
VSN1
VSP1
PWM1
NCP81232
ISP1
30
EN1
ISN1
29
3
EN2
ISP2
28
4
DRVON
ISN2
27
5
PGOOD 1
PWM2
26
6
PGOOD 2
PWM3
25
7
FAULT
ISP3
24
8
DLY 1
ISN3
23
9
DLY 2
/ DDR
ISP4
22
SS
ISN4
21
OTP2
/ REFIN
COMP2
FB2
DIFFOUT2
VSN2
VSP2
PWM4
10
GND
41
ILMT2
2
CNFG
VIN
FSET
1
11
12
13
14
15
16
17
18
19
20
Figure 1. Pin Configuration
PIN DESCRIPTION
Pin
Name
Type
Description
1
VIN
Power Input
Power Supply Input. Power supply input pin of the device, which is connected to the
integrated 5V LDO. 4.7 mF or more ceramic capacitors must bypass this input to power
ground. The capacitors should be placed as close as possible to this pin.
2
EN1
Analog Input
Enable 1. Logic high enables channel 1 and logic low disables channel 1. Input supply
UVLO can be programmed at this pin for channel 1.
3
EN2
Analog Input
Enable 2. Logic high enables channel 2 and logic low disables channel 2. Input supply
UVLO can be programmed at this pin for channel 2.
4
DRVON
Logic Input
5
PGOOD1
Logic Output
Power GOOD 1. Open−drain output. Provides a logic high valid power good output signal,
indicating the regulator’s output is in regulation window of channel 1.
6
PGOOD2
Logic Output
Power GOOD 2. Open−drain output. Provides a logic high valid power good output signal,
indicating the regulator’s output is in regulation window of channel 2.
7
FAULT
Logic Output
Fault. Digital output to indicate fault mode.
8
DLY1
Analog Input
Delay 1. A resistor from this pin to GND programs delay time of soft start for channel 1.
9
DLY2
/DDR
Analog Input
Delay 2 / DDR. A resistor from this pin to GND programs delay time of soft start for
channel 2. Short to GND to have DDR operation mode.
10
SS
Analog Input
Soft Start Time. A resistor from this pin to ground programs soft start time for both
channels.
11
FSET
Analog Input
Frequency Selection. A resistor from this pin to ground programs switching frequency.
12
CNFG
Analog Input
Configuration. A resistor from this pin to ground programs configuration of power stages.
13
ILIMT2
Analog Input
Limit of Current 2. Voltage at this pin sets over−current threshold for channel 2.
Driver On. Logic high input means drivers’ power is ready.
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2
NCP81232
PIN DESCRIPTION
Pin
Name
Type
Description
14
OTP2
/REFIN
Analog Input
15
COMP2
Analog Output
16
FB2
Analog Input
17
DIFFOUT2
Analog Output
18
VSN2
Analog Input
Voltage Sense Negative Input 2. Inverting input of differential voltage sense amplifier of
channel 2.
19
VSP2
Analog Input
Voltage Sense Positive Input 2. Non−inverting input of differential voltage sense amplifier
of channel 2.
20
PWM4
Analog Output
21
ISN4
Analog Input
Current Sense Negative Input 4. Inverting input of differential current sense amplifier of
phase 4.
22
ISP4
Analog Input
Current Sense Positive Input 4. Non−inverting input of differential current sense amplifier
of phase 4.
23
ISN3
Analog Input
Current Sense Negative Input 3. Inverting input of differential current sense amplifier of
phase 3.
24
ISP3
Analog Input
Current Sense Positive Input 3. Non−inverting input of differential current sense amplifier
of phase 3.
25
PWM3
Analog Output
PWM 3. PWM output of phase 3.
26
PWM2
Analog Output
PWM 2. PWM output of phase 2.
27
ISN2
Analog Input
Current Sense Negative Input 2. Inverting input of differential current sense amplifier of
phase 2.
28
ISP2
Analog Input
Current Sense Positive Input 2. Non−inverting input of differential current sense amplifier
of phase 2.
29
ISN1
Analog Input
Current Sense Negative Input 1. Inverting input of differential current sense amplifier of
phase 1.
30
ISP1
Analog Input
Current Sense Positive Input 1. Non−inverting input of differential current sense amplifier
of phase 1.
31
PWM1
Analog Output
32
VSP1
Analog Input
Voltage Sense Positive Input 1. Non−inverting input of differential voltage sense amplifier
of channel 1.
33
VSN1
Analog Input
Voltage Sense Negative Input 1. Inverting input of differential voltage sense amplifier of
channel 1.
34
DIFFOUT1
Analog Output
35
FB1
Analog Input
36
COMP1
Analog Output
37
OTP1
Analog Input
Over Temperature Protection 1. Voltage at this pin sets over−temperature threshold for
channel 1.
38
ILIMT1
Analog Input
Limit of Current 1. Voltage at this pin sets over−current threshold for channel 1.
39
VREF
Analog Output
Output of Reference. Output of 0.6 V reference. A 10nF ceramic capacitor bypasses this
input to GND. This capacitor should be placed as close as possible to this pin.
40
VCC5V
Analog Power
Voltage Supply of Controller. Output of integrated 5.35V LDO and power supply input pin
of control circuits. A 4.7 mF ceramic capacitor bypasses this input to GND. This capacitor
should be placed as close as possible to this pin.
41
THERM
/GND
Analog Ground
Thermal Pad and Analog Ground. Ground of internal control circuits. Must be connected to
the system ground.
Over Temperature Protection 2 / Reference Input. Voltage at this pin sets
over−temperature threshold for channel 2. Reference input pin in DDR mode.
Compensation 2. Output pin of error amplifier of channel 2.
Feedback 2. Inverting input of internal error amplifier for channel 2.
Differential Amplifier Output 2. Output pin of differential voltage sense amplifier of
channel 2.
PWM 4. PWM output of phase 4.
PWM 1. PWM output of phase 1.
Differential Amplifier Output 1. Output pin of differential voltage sense amplifier of
channel 1.
Feedback 1. Inverting input of internal error amplifier for channel 1.
Compensation 1. Output pin of error amplifier of channel 1.
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NCP81232
VIN
VIN
VIN
PWM1
VCC5V
VREF
EN1
PGOOD
1
PWM
Vout1
VSWH
NCP5369
VREF
PWM2
EN1
ISP1
ISN1
PGOOD
1
DISB#
CGND
ISP1
PGND
ISN1
ISP1
ISN1
VIN
DIFFOUT
1
FB1
VSP1
VSN1
COMP1
VSP1
VIN
VSN1
PWM
DISB#
DRVON
1
DLY1
ISP2
ISN2
SS
CNFG
VSWH
NCP5369
CGND
ISP2
PGND
ISN2
ISP2
VSN1
ISN2
VSP1
VIN
NCP81232
FSET
VIN
PWM3
PWM
PWM4
DISB#
Vout2
VSWH
NCP5369
ISP3
ISN3
ISP3
CGND
PGND
ISN3
ISP3
ISN3
VIN
DIFFOUT
2
FB2
VSP2
VSN2
COMP2
EN2
PGOOD
2
VSP2
VIN
VSN2
PWM
VSWH
NCP5369
DISB#
DRVON
2
EN2
ISP4
PGOOD
2
DLY2
ISN4
ISP4
CGND
ISN4
PGND
ISP4
VSN2
ISN4
VSP2
GND
Figure 2. Typical Application Circuit for Dual Channel Applications (2 Phase + 2 Phase)
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4
NCP81232
VIN
VIN
VIN
VCC5V
PWM1
VREF
PWM2
PWM
Vout1
VSWH
NCP5369
EN1
PGOOD1
EN1
ISP1
PGOOD1
ISN1
CGND
ISP1
PGND
ISP1
ISN1
ISN1
VIN
DIFFOUT1
VSP1
FB1
VSN1
COMP1
VIN
VSN1
PWM
VSWH
NCP5369
DLY1
ISP2
ISN2
SS
CNFG
VSP1
ISP2
CGND
PGND
ISN2
ISP2
VSN1
ISN2
VSP1
VIN
NCP81232
FSET
VIN
PWM
PWM3
VSWH
NCP5369
PWM4
ISP3
ISN3
CGND
ISP3
PGND
ISN3
ISP3
ISN3
VIN
VIN
PWM
VSWH
NCP5369
ISP4
ISN4
CGND
ISP4
ISN4
PGND
ISP4
ISN4
GND
Figure 3. Typical Application Circuit for Single Channel Applications (4 Phase)
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NCP81232
VIN
VIN
VCC5V
VREF
EN
PGOOD1
VIN
VCC5V
PWM1
VREF
PWM2
PWM
VDDQ
VSWH
NCP5369
EN1
ISP1
PGOOD1
ISN1
ISP1
CGND
PGND
ISN1
ISP1
ISN1
VIN
DIFFOUT1
FB1
VSP1
VSN1
COMP1
VIN
PWM
VSWH
NCP5369
DLY1
ISP2
ISN2
SS
CNFG
VSP1
VSN1
CGND
ISP2
PGND
ISN2
ISP2
VSN1
ISN2
VSP1
VIN
NCP81232
FSET
VIN
PWM
PWM3
DIFFOUT1
VSWH
NCP5369
OTP2
/ REFIN
PWM4
ISP3
ISN3
ISP3
CGND
PGND
ISN3
ISP3
ISN3
VIN
DIFFOUT2
FB2
VSP2
VSN2
COMP2
EN
PGOOD2
VCC5V
VSP2
VIN
VSN2
PWM
VTT
VSWH
NCP5369
EN2
ISP4
PGOOD2
DLY2
/ DDR
ISN4
CGND
ISP4
ISN4
PGND
ISP4
ISN4
VSN2
GND
VSP2
Figure 4. Typical Application Circuit for DDR Applications (3 Phase + 1 Phase)
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NCP81232
VIN
VIN
VIN
PWM1
VCC5V
PWM
Vout1
VSWH
NCP81290
VREF
PWM2
VTEMP1
VTEMP2
ISP1
ISN1
ILMT1
VTEMP
IOUT
CGND
ISP1
PGND
ISP1
ISN1
ISN1
VIN
ILMT2
OTP1
VSP1
OTP2
VSN1
VSP1
VIN
VSN1
PWM
VTEMP1
DIFFOUT1
ISP2
FB1
ISN2
VSWH
NCP81290
VTEMP
ISP2
IOUT
CGND
PGND
ISN2
ISP2
VSN1
ISN2
VSP1
VIN
COMP1
EN1
PGOOD1
EN2
PGOOD2
NCP81232
EN1
VIN
PGOOD1
PWM
PWM3
Vout2
VSWH
NCP81290
EN2
PWM4
PGOOD2
ISP3
CNFG
ISN3
FSET
VTEMP
IOUT
CGND
ISP3
PGND
ISN3
ISP3
ISN3
VIN
SS
DLY1
VSP2
DLY2
VSN2
VSP2
VIN
VSN2
PWM
VTEMP2
DIFFOUT2
FB2
ISP4
ISN4
COMP2
VSWH
NCP81290
VTEMP
ISP4
CGND
ISN4
IOUT
PGND
ISP4
VSN2
ISN4
VSP2
GND
Figure 5. Typical Application Circuit for DrMOS with Integrated Current Sense and Temperature Sense
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NCP81232
VIN
VCC5V
5V LDO
FB1
FB2
VREF
Reference
OC1
OC2
Dual−Channel / Multi−Phase
PWM1
PWM Control
PWM2
&
PWM3
Protections
PWM4
OC3
OC4
DRVON
OT1
EN1
UVLO
&
PGOOD
EN2
PGOOD1
PGOOD2
OT2
FAULT
ISP1
CS1
ISN1
CNFG
FSET
Programming
Detection
SS
DLY 1
ISP2
CS2
ISN2
DLY 2/DDR
ISP3
CS3
VSP1
ISN3
VSN1
DIFFOUT1
ISP4
CS4
COMP1
ISN4
FB1
OC1
OC2
OC3
0.6V
OC4
REFIN
MUX
Current
Limit
ILMT1
ILMT2
CS1
FB2
CS2
CS3
COMP2
CS4
DIFFOUT2
OT1
VSN2
OT2
VSP2
Figure 6. Functional Block Diagram
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Over
Temperature
Protection
OTP1
OTP2/REFIN
NCP81232
MAXIMUM RATINGS
Value
Rating
Symbol
Power Supply Voltage to PGND
VVIN
Supply Voltage VCC5V to GND
VVCC5V
VVSN
VSNx to GND
Other Pins to GND
Min
Max
Unit
30
V
−0.3
6.5
V
−0.2
0.2
V
−0.3
VCC5V + 0.3
V
Human Body Model (HBM) ESD Rating (Note 1)
ESD HBM
4000
V
Machine Model (MM) ESD Rating (Note 1)
ESD MM
400
V
ESD CDM
2000
Charge Device Mode (CDM) ESD Rating (Note 1)
Latch up Current: (Note 2)
All pins, except digital pins
Digital pins
ILU
−100
−10
100
10
V
mA
Operating Junction Temperature Range (Note 3)
TJ
−40
125
°C
Operating Ambient Temperature Range
TA
−40
100
°C
Storage Temperature Range
TSTG
−55
150
°C
Thermal Resistance Junction to Top Case (Note 4)
RYJC
5.0
°C/W
Thermal Resistance Junction to Board (Note 4)
RYJB
3.5
°C/W
Thermal Resistance Junction to Ambient (Note 4)
RθJA
38
°C/W
PD
2.63
W
MSL
1
−
Power Dissipation (Note 5)
Moisture Sensitivity Level (Note 6)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. It is for checking junction temperature using external measurement.
5. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected. TA = 25°C,
TJ_max = 125°C, PD = (TJ_max−T_amb)/Theta JA
6. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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NCP81232
ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are referenced to
TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
(Note 7)
VIN
4.5
12
20
V
VCC5V Under−Voltage (UVLO)
Threshold
VCC5V falling
VCCUV−
3.7
VCC5V OK Threshold
VCC5V rising
VCCOK
SUPPLY VOLTAGE
VIN Supply Voltage Range
VCC5V UVLO Hysteresis
V
4.3
VCCHYS
260
V
mV
VCC5V Regulator
Output Voltage
6 V < VIN < 20 V, IVCC5V = 15 mA
(External), EN1 = EN2 = Low
VCC
5.2
5.35
5.5
V
−2.0
0.2
2.0
%
200
mV
Load Regulation
IVCC5V = 5 mA to 25 mA (External), EN1 =
EN2 = Low
Dropout Voltage
VIN = 5 V, IVCC5V = 25 mA (External),
EN1 = EN2 = Low
VDO_VCC
VIN Quiescent Current
EN1 high, 1 channel and 1 phase only
EN1 and EN2 high, 2 channel and 2
phase per channel
IQVIN
−
−
15
18
20
25
mA
VIN Shutdown Current
EN1 and EN2 low
IsdVIN
−
8
10
mA
VFB
596
594
600
600
604
606
mV
VVREF
594
600
606
mV
SUPPLY CURRENT
REGULATION REFERENCE
Regulated Feedback Voltage
Include offset of error
amplifier
0°C to 85°C
–40°C to 125°C
REFERENCE OUTPUT
VREF Output Voltage
IVREF = 500 mA
Load Regulation
IVREF = 0 mA to 2 mA
−1.0
1.0
%
Input Common Mode Voltage Range
(Note 7)
−0.2
VCC−1.8
V
Output Voltage Swing
(Note 7)
VCC−1.8
V
1.005
V/V
DIFFERENTIAL VOLTAGE−SENSE AMPLIFIER
DC Gain
VSP−VSN = 0.6V to VCC−1.8
GAIN_DVA
CL = 20 pF to GND, RL = 10 kW to GND
(Note 7)
BW_DVA
VSP – VSN = 3.5 V
RVSEN
1.0
VSP,VSN = 2.0 V
IVS
−400
400
VSP – VSN = 0.6 V to VCC – 1.8 V
–40°C to 100°C
–40°C to 125°C
VosCS
−1.3
−1.9
1.3
1.9
Open−Loop DC Gain
(Note 7)
GAINEA
80
dB
Unity Gain Bandwidth
(Note 7)
GBWEA
20
MHz
−3dB Gain Bandwidth
Input Impedance
Input Bias Current
Input Offset Voltage
0.995
1.0
10
MHz
MW
nA
mV
VOLTAGE ERROR AMPLIFIER
Slew Rate
COMP Voltage Swing
FB, REFIN Bias Current
(Note 7)
SRCOMP
ICOMP(source) = 2 mA
VmaxCOMP
3.2
3.4
20
−
ICOMP(sink) = 2 mA
VminCOMP
−
1.05
1.15
VFB = VREFIN = 1.0 V
IFB
−400
V/ms
400
V
nA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
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NCP81232
ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are referenced to
TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
DIFFERENTIAL CURRENT−SENSE AMPLIFIER
DC Gain
GAINCA
6
V/V
BWCA
10
MHz
−3dB Gain Bandwidth
(Note 7)
Input Common Mode Voltage Range
(Note 7)
−0.2
Differential Input Voltage Range
(Note 7)
−60
Input Bias Current
−
VCC+0.1
V
60
mV
100
nA
ISP,ISN = 2.5 V
ICS
−100
Rfs = 2.7k
Rfs = 5.1k
Float
Rfs = 8.2k
Short to GND
Rfs = 13k
Rfs = 20k
Rfs = 33k
FSW
180
270
360
450
540
720
900
1080
200
300
400
500
600
800
1000
1200
220
330
440
550
660
880
1100
1320
kHz
IFS
45
50
55
mA
TRST
1.8
2.0
2.2
ms
TDL
−
0.9
1.8
2.7
3.6
7.2
10.8
18
−
0
1.0
2.0
3.0
4.0
8.0
12
20
TDL1
−
1.1
2.2
3.3
4.4
8.8
13.2
22
−
ms
IDL
45
50
55
mA
TSS
0.9
2.7
3.6
5.4
1.0
3.0
4.0
6.0
1.1
3.3
4.4
6.6
ms
0.9
2.7
3.6
5.4
1.0
3.0
4.0
6.0
1.1
3.3
4.4
6.6
45
50
55
SWITCHING FREQUENCY
Switching Frequency
Source Current
SYSTEM RESET TIME
System Reset Time
Measured from EN to start of soft start
with TDL = 0 ms
DELAY TIME
Delay Time
Float
Rdl = 33k
Rdl = 20k
Rdl = 13k
Rdl = 8.2k
Rdl = 5.1k
Rdl = 2.7k
Short to GND
(DLY1 Only)
Short to GND (DDR
Mode, DLY2 Only)
(Note 7)
Source Current
SOFT START TIME
Soft Start Time
OTP Configuration 1
(Note 7)
Rss = 13k
Float
Rss = 20k
Rss = 33k
OTP Configuration 2
(Note 7)
Rss = 2.7k
Short to GND
Rss = 5.1k
Rss = 8.2k
Source Current
ISS
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
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11
NCP81232
ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are referenced to
TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
CONFIGURATION
PWM Configuration
(Note 7)
Channel 1
Channel 2
PWM1
PWM4
Rcnfg = 2.7k
PWM1, PWM2
PWM4
Rcnfg = 5.1k
PWM1, PWM2, PWM3
PWM4
Short to GND
PWM1, PWM2
PWM3, PWM4
Rcnfg = 8.2k
PWM1
Rcnfg = 13k
PWM1, PWM2
Rcnfg = 20k
PWM1, PWM2, PWM3
Rcnfg = 33k
PWM1, PWM2, PWM3, PWM4
Float
Source Current
ICNFG
45
50
55
mA
PGOOD
PGOOD Startup Delay
PGOOD Shutdown Delay
PGOOD Low Voltage
Measured from end of Soft Start to
PGOOD assertion
Td_PGOOD
Measured from EN to PGOOD
de−assertion
100
ms
240
ns
IPGOOD= 4 mA (sink)
VlPGOOD
−
−
0.3
V
PGOOD = 5 V
IlkgPGOOD
−
−
1.0
mA
FAULT Output High Voltage
Isourse = 0.5 mA
VFAULT_H
VCC−0.5
FAULT Output Low Voltage
Isink = 0.5 mA
VFAULT_L
Measured from ILIMT ISP−ISN = 50 mV
to GND
ISP−ISN = 20 mV
VOCTH+
Measured from ILIMT
to GND (only active in
non−latched OVP)
VOCTH−
PGOOD Leakage Current
FAULT
V
0.5
V
mV
PROTECTIONS
Positive Current Limit Threshold
Negative Current Limit Threshold
ISP−ISN =
−50 mV
ISP−ISN =
−20 mV
Positive Over Current Protection
(OCP) Debounce Time
(Note 7)
Under Voltage Protection (UVP)
Threshold
Voltage from FB to GND
VUVTH
Under Voltage Protection (UVP)
Hysteresis
Voltage from FB to GND
VUVHYS
Under Voltage Protection (UVP)
Debounce Time
Shutdown Time in Hiccup Mode
285
300
315
110
120
130
285
300
315
110
120
130
8
Cycles
500
510
mV
ms
520
mV
20
mV
(Note 7)
1.5
us
UVP (Note 7)
OCP (Note 7)
OTP (Note 7)
12*TSS
16*TSS
8*TSS
ms
First−Level Over Voltage Protection
(OVP_L) Threshold
Voltage from FB to GND
VOVTH_L
First−Level Over Voltage Protection
(OVP_L) Hysteresis
Voltage from FB to GND
VLOVHYS
650
660
−20
670
mV
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
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12
NCP81232
ELECTRICAL CHARACTERISTICS (VIN = 12 V, typical values are referenced to TA = 25°C, Min and Max values are referenced to
TA from −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
PROTECTIONS
First−Level Over Voltage Protection
(OVP_L) Debounce Time
(Note 7)
1.0
Second−Level Over Voltage Protection
(OVP_H) Threshold
Voltage from FB to GND
VOVTH_H
Second−Level Over Voltage Protection
(OVP_H) Hysteresis
Voltage from FB to GND
VHOVHYS
Second−Level Over Voltage Protection
(OVP_H) Debounce Time
(Note 7)
Offset Voltage of OTP Comparator
VILMT = 200 mV
OTP Source Current
710
VOS_OTP
−2
IOTP
9
OTP Debounce Time
(Note 7)
Thermal Shutdown (TSD) Threshold
(Note 7)
Tsd
Recovery Temperature Threshold
(Note 7)
Trec
Thermal Shutdown (TSD) Debounce
Time
(Note 7)
140
720
ms
730
mV
−20
mV
1.0
us
10
2
mV
11
mA
160
ns
165
°C
125
°C
120
ns
ENABLE
VEN_TH
0.75
0.8
0.85
V
VCC5V is OK
IEN_HYS
25
30
35
mA
VDRVON_TH
0.75
0.8
0.85
V
VCC5V is OK
IDRVON_HYS
25
30
35
mA
Minimum On Time
(Note 7)
Ton_min
50
ns
Minimum Off Time
(Note 7)
Toff_min
EN ON Threshold
Hysteresis Source Current
DRVON
DRVON ON Threshold
Hysteresis Source Current
PWM MODULATION
160
ns
0% Duty Cycle
COMP voltage when the PWM outputs
remain Lo (Note 7)
1.3
V
100% Duty Cycle
COMP voltage when the PWM outputs
remain HI, Vin = 12.0 V (Note 7)
2.5
V
Ramp Feed*forward Voltage Range
(Note 7)
4.5
20
V
PWM OUTPUT
PWM Output High Voltage
Isourse = 0.5 mA
VPWM_H
PWM Output Low Voltage
Isink = 0.5 mA
VPWM_L
Rise and Fall Times
VCC−0.2
0.2
CL (PCB) = 50 pF, measured between
10% & 90% of VCC (Note 7)
Leakage Current in Hi−Z Stage
V
10
ILK_PWM
−1.0
V
ns
1.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Guaranteed by design, not tested in production.
www.onsemi.com
13
NCP81232
Table 1. RESISTOR OPTIONS FOR FUNCTION PROGRAMMING
Resistance Range (kW)
Resistor Options (kW)
Min
Typ
Max
±5%
2.565
2.7
2.835
2.7
2.61
2.67
4.845
5.1
5.355
5.1
4.87
7.79
8.2
8.61
8.2
7.87
12.35
13
13.65
13
19
20
21
31.35
33
34.65
±1%
2.74
2.80
4.99
5.11
5.23
8.06
8.25
8.45
12.4
12.7
13
13.3
20
19.1
19.6
20
20.5
33
31.6
32.4
33.2
34
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14
NCP81232
DETAILED DESCRIPTION
General
same channel are paralleled together in output of power
stage with a common voltage−sense feedback. All the input
pins of voltage sense and current senses in unused channel
and phases can be left float. For single−channel
configuration, EN2 pin is recommended to be pulled low to
ground.
The
NCP81232,
a
dual−channel/multi−phase
synchronous buck controller, provides power management
solutions for various applications supported by DrMOS. It
has 8 programmable power−stage configurations,
differential voltage and current sense, flexible power
sequence programming, and comprehensive protections.
Operation Modes
The NCP81232 has eight programmable operation
configurations as shown in Figure 7. All the phases in the
(1) PWM1+PWM4
(2) PWM1&PWM2+PWM4
OSC
OSC
PWM1
PWM1
PWM2
PWM4
PWM4
(3) PWM1&PWM2&PWM3+PWM4
(4) PWM1&PWM2+PWM3&PWM4
OSC
OSC
PWM1
PWM1
PWM2
PWM2
PWM3
PWM3
PWM4
PWM4
(1) Dual Channel Operation
(5) PWM1
(6) PWM1&PWM2
OSC
OSC
PWM1
PWM1
PWM2
(7) PWM1&PWM2&PWM3
(8) PWM1&PWM2&PWM3&PWM4
OSC
OSC
PWM1
PWM1
PWM2
PWM2
PWM3
PWM3
PWM4
(2) Single Channel Operation
Figure 7. 8 Programmable Configurations and Interleaved Operation Among Phases
Soft Start
programmable delay time TDLY after the device is enabled
and both VCC5V and DRVON are ready. The device is able
to start up smoothly under an output pre−biased condition
without discharging the output before ramping up.
The NCP81232 has a soft start function and the soft start
time is externally programmed at SS pin. The output starts
to ramp up following a system reset period TRST and a
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15
NCP81232
VCC5V
VCC5V
VCCOK
DRVON
DRVON
VDRVON_OK
EN
EN
TRST
T DLY
T SS
TRST
T d_PGOOD
Vout
Vout
PGOOD
PGOOD
Tri−State
PWM
T DLY
T SS
T d_PGOOD
Tri−State
PWM
(1) VCC5V and DRVON Ready before EN
(2) VCC5V and DRVON Ready after EN
Figure 8. Timing Diagrams of Power Up Sequence
VCC5V
VCC5V
DRVON
DRVON
EN
EN
VDRVON_F
V DRVON_OK
TRST
Vout
Vout
PGOOD
PGOOD
PWM
Tri−State
Td_PGOOD
Tri −State
PWM
Figure 9. Timing Diagram of Power Down
Sequence
T SS
Figure 10. Timing Diagram of DRVON UVLO
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16
NCP81232
VCC OK
VCC UVLO
VCC
5V
VDRVON_TH
EN_Int
DRV
ON
IDRVON_HYS
VEN_TH
EN
IEN_HYS
Figure 11. Enable, DRVON, and VCC UVLO
Enable and Input UVLO
The low threshold in ENABLE signal is
The NCP81232 is enabled when the voltage at EN pin is
higher than an internal threshold VEN_TH = 0.8 V. A
hysteresis can be programmed by an external resistor REN
connected to EN pin as shown in Figure 12. The high
threshold in ENABLE signal is
V EN_H + V EN_TH
V EN_L + V EN_TH * V EN_HYS
(eq. 2)
The programmable hysteresis in ENABLE signal is
V EN_HYS + I EN_HYS @ R EN
(eq. 3)
(eq. 1)
VEN_TH
EN_Int
VEN_H
VEN_L
ENABLE
EN
REN
IEN_HYS
Figure 12. Enable and Hysteresis Programming
A UVLO function for input power supply can be
implemented at EN pins. As shown in Figure 13, the UVLO
thresholds and hysteresis can be programmed by two
external resistors.
V IN_H +
ǒ
R EN1
R EN2
Ǔ
) 1 @ V EN_TH
(eq. 4)
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17
V IN_L + V IN_H * V IN_HYS
(eq. 5)
V IN_HYS + I EN_HYS @ R EN1
(eq. 6)
NCP81232
VIN_H
VEN_TH
EN_Int
VIN_L
VIN
REN1
EN
REN2
IEN_HYS
Figure 13. Enable and Input Supply UVLO Circuit
To avoid undefined operation, EN pins cannot be left float
in applications.
DDR Mode Operation
EN
DLY2 /
DDR
COMP2
VTT+
VTT−
VTT_S
DLY 2/DDR
Detector
VSN1
DIFFOUT1
0.6V
DAC2
OTP2 /
REFIN
FB2
DIFFOUT2
VSN2
VSP2
Out High if pin is
grounded.
VDDQ_S
VDDQ−
VSP1
EN2
EN1
COMP2
VDDQ+
Figure 14. Block Diagram of DDR Mode Operation
external resistor divider, which is connected from
DIFFOUT2 to GND, is applied to obtain an expected VTT
voltage considering FB2 voltage is 0.6V as REFIN.
In DDR mode, two channels have independent fault
detections and protections but have hiccup together if
anyone of them needs to start a hiccup.
If DLY2/DDR pin is shorted to GND before the
NCP81232 starts up, as shown in Figure 14, the device is
internally configured to operate in DDR mode. In DDR
mode, the channel 1 provides power for VDDQ rail and the
channel 2 provides power for VTT rail. The two enable pins
need to be connected together, and the CNFG pin can be
programmed to be one of the four dual−channel options
(1+1, 2+1, 3+1, 2+2). The both channels have the same
delay time programmed at DLY1 pin, and VTT rail always
tracks with VDDQ/2. An external resistor divider, which is
connected from DIFFOUT1 to GND, is employed to get
0.6V at REFIN pin in steady−state operation. Another
Output Voltage Sensing and Regulation
The NCP81233 has a differential voltage−sense amplifier.
As shown in Figure 15, the remote voltage sensing points are
connected to input pins VSP and VSN of the differential
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18
NCP81232
detection at FB pin. If FB voltage is over VOVTH_L
(660 mV typical) for more than 1us, the first over voltage
protection OVPL is triggered and PGOOD is pulled low. In
the meanwhile, all the high−side MOSFETs are turned off
and all the low−side MOSFETs are turned on. A negative
current protection in low−side MOSFETs is active in this
protection level, and it turns off low−side MOSFET for at
least 50 ns if negative current is over the limit. However, in
a worse case that FB voltage rises to be over VOVTH_H
(720 mV typical) for more than 1us, the second level over
voltage protection OVPH takes in charge. As same as the
first level OVP, all the high−side MOSFETs are turned off
and all the low−side MOSFETs are turned on, but the
negative current protection is disabled. The over voltage
protection can be cleared once FB voltage drops 20 mV
lower than VOVTH_L, and then the system comes back to
normal operation.
OVPH detection starts from the beginning of soft−start
time TSS and ends in shutdown and idle time of hiccup mode
caused by other protections, while OVPL detection starts
after PGOOD delay (Td_PGOOD) is expired and ends at the
same time as OVPH.
voltage−sense amplifier via a resistor network composed by
RVS1, RVS2, and RVS3.
In most of cases, RVS3 = 0 W or 100 W. To have enough
operation headroom for the input pins of the differential
amplifier, usually the input voltage VSP−VSN is designed
to be not higher than 2.5 V. If VOUT > 2.5 V, VSP−VSN is
divided down to be 2.5 V by the resistor network. With a
given RVS2 like 1 kW, then the value of RVS1 can be
obtained by
R VS1 +
ǒV OUT * 2.5Ǔ @ R VS3
2.5
* R VS3
(eq. 7)
If VOUT ≤ 2.5 V, RVS1 = 0 W and RVS2 can be left open.
DIFFOUT pin, the output of the differential amplifier, is
fed to FB pin of the error amplifier in the same channel. The
resistance of RFB1 between DIFFOUT and FB can be
selected in a range from 500 W to 50 kW having a typical
value of 10 kW. The resistance of RFB2 from FB to GND can
be calculated by
0.6 @ R FB1
R FB2 +
R
R
VS2
)R
VS2
VS1
)R
VS3
(eq. 8)
* 0.6
Under Voltage Protection (UVP)
RVS1
VSP
RVS2
VSN
The NCP81232 pulls PGOOD low and turns off both
high−side and low−side MOSFETs once FB voltage drops
below VUVTH (540 mV typical) for more than 1.5 ms.
Under voltage protection operates in a hiccup mode. A
normal power up sequence happens after a hiccup interval.
UVP detection starts when PGOOD delay (Td_PGOOD)
is expired right after a soft start, and ends in shutdown and
idle time of hiccup mode.
Vout
RVS3
DIFFOUT
FB
COMP
Over Current Protection (OCP)
The NCP81232 senses phase currents by differential
current sense amplifiers and provides a cycle−by−cycle over
current protection for each phase. If OCP happens in all the
phases of the same channel and lasts for more than 8 times
of switching cycle, the channel shuts down and enters into
a hiccup mode. The channel may enter into hiccup mode
sooner due to the under voltage protection in a case if the
output voltage drops down very fast.
RFB1
0.6V
RFB2
GND
Figure 15. Output Voltage Sensing and Regulation
Over Voltage Protection (OVP)
A two−level recoverable over voltage protection is
employed in the NCP81232, which is based on voltage
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19
NCP81232
ISP
6
ISN
OCP
ISP
ISN
RNTC
RT2
ILMT
RT3
RT1
VREF
OTP
ROTP2
OTP
ROTP1
10uA
(1) OTP Configuration 1
ISP
6
ISN
OCP
ISP
ISN
RILMT1
ILMT
VREF
RILIM2
0.6V
OTP
ROTP2
VT
OTP
ROTP1
10uA
(2) OTP Configuration 2
Figure 16. Over−Current Protection and Over−Temperature Protection
Over Temperature Protection (OTP)
The over−current threshold can be externally
programmed at the ILIM pin for each channel. As shown in
Figure 16 (1), a NTC resistor RNTC can be employed for
temperature compensated over current protection. The peak
current limit per phase can be calculated by
V ISP * V ISN +
1
@
6
R T3
R
@R
R T1 ) R T2)RNTC ) R T3
T2
The NCP81232 provides over temperature protection for
each channel. To serve different types of DrMOS, one of two
internal configurations of OTP detection can be selected at
SS pin combined with a soft start time programming.
With OTP Configuration 1, as shown in Figure 16 (1), the
NTC resistor RNTC senses the hot−spot temperature and
changes the voltage at ILMT pin. Both over−temperature
threshold and hysteresis are externally programmed at OTP
pin by a resistor divider. Once the voltage at ILMT pin is
higher than the voltage at OTP pin, OTP trips and the
channel is shut down. The channel will have a normal start
up after a hiccup interval in condition that the temperature
drops below the OTP reset threshold. The OTP assertion
threshold VOTP and reset threshold VOTP_RST can be
calculated by
(eq. 9)
@ V REF
NTC
If no temperature compensation is needed, as shown in
Figure 16 (2), the peak current limit per phase can be simply
set by
V ISP * V ISN +
R ILIM2
1
@
@ V REF
6 R ILIM1 ) R ILIM2
(eq. 10)
OCP detection starts from the beginning of soft−start time
TSS, and ends in shutdown and idle time of hiccup mode.
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20
NCP81232
V OTP +
V REF ) I OTP_HYS @ R OTP1
happens. The OTP assertion threshold VOTP and reset
threshold VOTP_RST in this configuration can be obtained
by
(eq. 11)
R
1 ) ROTP1
ǒ
OTP2
V OTP_RST +
V T_OTP + 1 )
V REF @ R OTP2
The corresponding OTP temperature TOTP and reset
temperature TOTP_RST can be calculated by
T OTP +
ǒ
ln R
ńR
NTC
B
T OTP_RST +
Ǔ
NTC
* 273.15
ǒ
ńR
NTC_OTPRST
Ǔ
NTC
B
1
) 25)273.15
R
*R
T_OTP
R T_OTPRST +
ǒ
(eq. 15)
1
R
1
R
ǒ
*
T2
1
R NTC_OTPRST +
R T_OTP +
T1
*R
T_OTPRST
V REF
V OTP
T1
*
1
R
V OTP_RST
Ǔ
Ǔ
(eq. 16)
T2
* 1 @ R T3
V REF
(eq. 19)
* 1 @ R T3
ǒ
0.6
R OTP2
Ǔ
* I OTP_HYS @ R OTP1 ) 0.6
(eq. 20)
The NCP81232 has an internal thermal shutdown
protection to protect the device from overheating in an
extreme case that the die temperature exceeds 150°C. TSD
detection is activated when VCC5V and at least one of ENs
are valid. Once the thermal protection is triggered, the whole
chip shuts down and all PWM signals are in high impedance.
If the temperature drops below 125°C, the system
automatically recovers and a normal power sequence
follows.
(eq. 14)
1
1
@ 0.6
Thermal Shutdown (TSD)
* 273.15
where
R NTC_OTP +
Ǔ
OTP detection starts from the beginning of soft−start time
TSS, and ends in shutdown and idle time of hiccup mode.
(eq. 13)
1
ln R
V T_OTP_RST +
1
25)273.15
)
R OTP2
(eq. 12)
R OTP1 ) R OTP2
1
R OTP1
FAULT Indicator
The NCP81232 has a comprehensive fault indicator by
means of a cycle−by−cycle fault signal output from FAULT
pin. Figure 17 shows a typical timing diagram of FAULT
signal. FAULT signal is composed of ALEART and two
portions of fault flags for the two channels, having a total
cycle period of 36 ms. A corresponding fault flag is asserted
to high once the fault happens. The periodic fault signal
starts from the point where any fault has been confirmed and
ends after PGOOD is asserted again. Note the last FAULT
cycle has to be complete after PGOOD assertion.
(eq. 17)
(eq. 18)
With OTP Configuration 2, as shown in Figure 16 (2), the
NCP81232 receives an external signal VT linearly
representing temperature and compares to an internal 0.6 V
reference voltage. If the voltage is over the threshold OTP
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21
NCP81232
PGOOD1 / PGOOD2
FAULT
ALERT
Start
4
4
OC
1 1
Channel 1
Channel 2
Fault Flags
Fault Flags
OT
UV
OV
L
Interval
OV
H
2
OC
OT
UV
4
OV
L
OV
H
End
4
36
Figure 17. Timing Diagram of FAULT Signal
LAYOUT GUIDELINES
• Ground: It would be good to have separated ground
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
• Power Paths: Use wide and short traces for power paths
(such as VIN, VOUT, SW, and PGND) in power stages
to reduce parasitic inductance and high−frequency loop
area. It is also good for efficiency improvement.
• Power Supply Decoupling: The devices should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to VIN and PGND pins.
• VCC Decoupling: Place decoupling caps as close as
possible to VCC5V pin of the NCP81232 and VCCP
pins of DrMOS.
• Switching Node: Each SW node in power stages should
be a copper pour, but compact because it is also a noise
source.
• Bootstrap: The bootstrap cap and an option resistor per
phase need to be very close and directly connected
between bootstrap pin and SW pin of DrMOS.
•
•
•
planes for power ground PGND and analog ground
GND and connect the two planes at one point.
Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
Careful layout for multi−phase locations and output
capacitor distribution would help to get even voltage
ripple at the voltage sensing point, and have better
current balance as well.
Current Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential current sense per phase.
Careful layout for current sensing is critical for jitter
minimization, accurate current limiting, and good
current balance. The current−sense filter capacitors and
resistors should be close to the controller. The
temperature compensating thermistor should be placed
as close as possible to the inductor. The wiring path
should be kept as short as possible but well away from
the switch nodes.
Compensation Network: The small feedback capacitor
from COMP to FB should be as close to the controller
as possible. Keep the FB traces short to minimize their
capacitance to ground.
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22
NCP81232
• More free vias are welcome to be around DrMOS and
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
• The exposed pads must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
•
•
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
Use large area copper pour to help thermal conduction
and radiation.
Do not put the inductor to be too close to the DrMOS,
thus the heat sources are decentralized.
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23
NCP81232
PACKAGE DIMENSIONS
QFN40 5x5, 0.4P
CASE 485CR
ISSUE C
PIN ONE
LOCATION
0.15 C
L2
A
B
D
ÉÉÉ
ÉÉÉ
ÉÉÉ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L2
DETAIL A
E
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
L2
L
L
L1
0.15 C
TOP VIEW
DETAIL B
0.10 C
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
(A3)
ÉÉ
ÉÉ
A
0.08 C
A1
SIDE VIEW
NOTE 4
EXPOSED Cu
C
SEATING
PLANE
MOLD CMPD
DETAIL B
0.10
M
D2
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
ALTERNATE
CONSTRUCTION
C A B
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.15
0.25
5.00 BSC
3.40
3.60
5.00 BSC
3.40
3.60
0.40 BSC
0.30
0.50
−−−
0.15
0.12 REF
5.30
40X
0.63
3.64
11
0.10
21
M
C A B
1
E2
5.30
3.64
1
40X
L
40
e
e/2
BOTTOM VIEW
40X
b
0.10
M
C A B
0.05
M
C
PKG
OUTLINE
NOTE 3
0.40
PITCH
40X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP81232/D