NCV8876 Automotive Grade Start-Stop Non-Synchronous Boost Controller The NCV8876 is a Non-Synchronous Boost controller designed to supply a minimum output voltage during Start-Stop vehicle operation battery voltage sags. The controller drives an external N-channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include, cycle-by-cycle current limiting, protection and thermal shutdown. Additional features include low quiescent current sleep mode operation. The NCV8876 is enabled when the supply voltage drops below 7.3 V, with boost operation initiated when the supply voltage is below 6.8 V. Features • • • • • • • • • • • Automatic Enable Below 7.3 V (Factory Programmable) Boost Mode Operation at 6.8 V $2% Output Accuracy Over Temperature Range Peak Current Mode Control with Internal Slope Compensation Externally Adjustable Frequency Operation Wide Input Voltage Range of 2 V to 40 V, 45 V Load Dump Low Quiescent Current in Sleep Mode (<11 mA Typical) Cycle−by−Cycle Current Limit Protection Hiccup−Mode Overcurrent Protection (OCP) Thermal Shutdown (TSD) This is a Pb−Free Device www.onsemi.com MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 8876xx ALYW G 1 8876xx = Specific Device Code xx = 00, 01 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package PIN CONNECTIONS STATUS 1 8 ROSC ISNS 2 7 VC GND 3 6 VOUT GDRV 4 5 VDRV (Top View) Typical Applications • Applications Requiring Regulated Voltage through Cranking and Start−Stop Operation ORDERING INFORMATION Device Package Shipping† NCV887600D1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCV887601D1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2015 December, 2015 − Rev. 11 1 Publication Order Number: NCV8876/D NCV8876 Vg Cg TEMP VDRV FAULT LOGIC 8 OSC DRIVE LOGIC SC ROSC 4 2 CL VC CSA 3 7 L CDRV NRVB440FS Vo NVMFS5844NL CLK PWM ROSC VDRV 5 Q GDRV Co ISNS RGDRV GND RSNS + SCP RC Cdecoupling Gm CC WAKEUP VREF 6 1 Vmicro VOUT STATUS STATUS Battery In Figure 1. Typical Application Sleep Threshold 7.7 V Wakeup Threshold 7.3 V Regulation 6.8 V (Internal signal) VOUT Wakeup Internal Clamp Voltage COMP GDRV Wakeup Delay Comp Delay Figure 2. Functional Waveforms PACKAGE PIN DESCRIPTIONS Pin No. Pin Symbol 1 STATUS This is an open−drain diagnostic. IC status operation flag indicator. This output is a logic low when IC VOUT is below 7.3 V and device is active. A pull−up resistor of around 80 kW should be connected between STATUS and a microcontroller reference. This output is a logic high when the IC is disabled or in UVLO. 2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. An RGND = 15 kW GDRV−GND resistor is strongly recommended. 5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VOUT. Bypass with a 1.0 mF ceramic capacitor to ground. 6 VOUT Monitors output voltage and provides IC input voltage. 7 VC 8 ROSC Function Output of the voltage error transconductance amplifier. An external compensator network from VC to GND is used to stabilize the converter. Use a resistor to ground to set the frequency. www.onsemi.com 2 NCV8876 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated) Rating Value Unit −0.3 to 40 V Peak Transient Voltage (Load Dump on VOUT) 45 V Dc Supply Voltage (VDRV, GDRV) 12 V −0.3 to 3.6 V Dc Voltage (STATUS) −0.3 to 6 V Dc Voltage Stress (VOUT − VDRV) −0.7 to 40 V Operating Junction Temperature −40 to 150 °C Storage Temperature Range −65 to 150 °C Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C 265 peak °C Dc Supply Voltage (VOUT) Dc Voltage (VC, ISNS, ROSC) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. PACKAGE CAPABILITIES Characteristic ESD Capability (All Pins) Human Body Model Machine Model Moisture Sensitivity Level Value Unit ≥2.0 ≥200 kV V 1 Package Thermal Resistance °C/W 100 Junction−to−Ambient, RqJA (Note 1) 1. 1 in2, 1 oz copper area used for heatsinking. TYPICAL VALUES Part No. Dmax fS Sa Vcl Isrc Isink VOUT SCE NCV887600 83% 170 kHz 34 mV/ms 400 mV 800 mA 600 mA 6.8 V N NCV887601 83% 170 kHz 53 mV/ms 200 mV 800 mA 600 mA 6.8 V N www.onsemi.com 3 NCV8876 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit VOUT = 13.2 V, TJ = 25°C − 12 14 mA − 2.2 4.0 mA 153 153 − − 501 501 kHz − 1.0 − V 153 180 283 409 170 200 315 455 187 220 347 501 kHz 90 115 140 ns 81 83 85 % 30 46 34 53 38 60 mV/ ms GENERAL Quiescent Current, Sleep Mode Iq,sleep Quiescent Current, No switching Iq,off Into VOUT pin, 6.8 V < VOUT < 7.3 V, No switching FSW Operating Range OSCILLATOR Switching Frequency ROSC Voltage Default Switching VROSC FSW Minimum Pulse Width ton,min Maximum Duty Cycle Dmax Slope Compensating Ramp (Note 2) NCV887600 NCV887601 ROSC = Open (NCV887600, NCV887601) ROSC = 100 kW ROSC = 20 kW ROSC = 10 kW ROSC = OPEN Sa NCV887600 NCV887601 STATUS FLAG STATUS Wake Up Delay VOUT < 7.3 V − 9.3 14.0 ms STATUS Pull−down Capability Sinking 1.0 mA − − 400 mV Input−to−output gain at dc, ISNS ≤ 1 V 0.9 1.0 1.1 V/V 2.5 − − MHz CURRENT SENSE AMPLIFIER Low−Frequency Gain Acsa Bandwidth BWcsa Gain of Acsa − 3 dB ISNS Input Bias Current Isns,bias Out of ISNS pin Current Limit Threshold Voltage Vcl Voltage on ISNS pin Current Limit, Response Time (Note 2) tcl CL tripped until GDRV falling edge, VISNS = Vcl(typ) + 60 mV Overcurrent Protection, Threshold Voltage %Vocp Overcurrent Protection, Response Time (Note 2) tocp NCV887600 NCV887601 Percent of Vcl From overcurrent event, Until switching stops, VISNS = VOCP + 40 mV − 30 50 mA 360 180 400 200 440 220 mV − 80 125 ns 125 150 175 % − 80 125 ns 0.8 1.2 1.6 mS VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER VOUT = ±100 mV Transconductance gm,vea VEA Output Resistance (Note 2) Ro,vea 2.0 − − MW VEA Maximum Output Voltage Vc,max 2.5 − − V VEA Sourcing Current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − mA VEA Sinking Current Isnk,vea VEA output current, Vc = 1.5 V 80 100 − mA VEA Clamp Voltage Vc,clamp VOUT < 7.3 V − 1.1 − V VOUT < 7.3 Vwith VC pin compensation network disconnected − 53 60 ms VC Delay GATE DRIVER (Note 3) Sourcing Current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V NCV887600 NCV887601 550 550 800 800 − − mA Sinking Current Isink VGDRV ≥ 2 V NCV887600 NCV887601 500 500 600 600 − − mA − 0.3 0.6 V Driving Voltage Dropout (Note 2) Vdrv,do VOUT − VDRV, IvDRV = 25 mA www.onsemi.com 4 NCV8876 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit VOUT − VDRV = 1 V 35 45 − mA − − 0.7 V 5.8 5.8 6.0 6.0 6.2 6.2 V GATE DRIVER (Note 3) Driving Voltage Source Current Idrv Backdrive Diode Voltage Drop Vd,bd VDRV – VOUT, Id,bd = 5 mA Driving Voltage VDRV IVDRV = 0.1 − 25 mA NCV887600 NCV887601 UVLO Undervoltage Lock−out, Threshold Voltage Vuvlo,fall VOUT falling 3.4 3.59 3.8 V Undervoltage Lock−out Vuvlo,rise VOUT rising 3.90 4.05 4.20 V THERMAL SHUTDOWN Thermal Shutdown Threshold (Note 2) Tsd TJ rising 160 170 180 °C Thermal Shutdown Hysteresis (Note 2) Tsd,hys TJ falling 10 15 20 °C Thermal Shutdown Delay (Note 2) tsd,dly From TJ > Tsd to stop switching − − 100 ns NCV887600 NCV887601 6.66 6.66 6.8 6.8 6.94 6.94 V VOLTAGE REGULATION Voltage Regulation VOUT,reg Threshold IC Enable VOUT descending NCV887600 NCV887601 7.1 7.1 7.3 7.3 7.5 7.5 V Threshold IC Disable VOUT ascending NCV887600 NCV887601 7.5 7.5 7.7 7.7 7.9 7.9 V Threshold IC Enable – Voltage Regulation NCV887600 NCV887601 0.32 0.32 0.5 0.5 − − V Threshold IC Disable – Threshold IC Enable NCV887600 NCV887601 − − 0.4 0.4 − − V 2. Not tested in production. Limits are guaranteed by design. 3. An RGND = 15 kW GDRV−GND resistor is strongly recommended. www.onsemi.com 5 NCV8876 TYPICAL CHARACTERISTICS 2.30 VOUT = 13.2 V Iq,on, QUIESCENT CURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) 22 20 18 16 14 12 10 −50 0 50 100 2.20 2.18 2.16 2.14 2.12 0 50 100 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Quiescent Current vs. Temperature 150 1.010 NORMALIZED CURRENT LIMIT Ton,min, MINIMUM ON TIME (ns) 2.22 TJ, JUNCTION TEMPERATURE (°C) 117 116 115 114 113 112 111 110 0 50 100 1.005 1.000 0.995 0.990 −50 150 0 50 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Minimum On Time vs. Temperature Figure 6. Normalized Current vs. Temperature 150 169.0 SWITCHING FREQUENCY (kHz) 6.84 6.83 VOUT REGULATION 2.24 Figure 3. Sleep Current vs. Temperature 118 6.82 6.81 6.80 6.79 6.78 −50 2.26 2.10 −50 150 119 109 −50 VOUT = 13.2 V fs = 170 kHz 2.28 0 50 168.8 168.6 168.4 168.2 168.0 167.8 167.6 167.4 167.2 167.0 150 −50 100 ROSC = Open 0 50 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. VOUT Regulation vs. Temperature Figure 8. Switching Frequency vs. Temperature www.onsemi.com 6 150 NCV8876 7.8 VOUT Rising THRESHOLD IC VOLTAGE (V) 4.1 UVLO THRESHOLD (V) 4.0 3.9 3.8 3.7 VOUT Falling 3.6 3.5 −50 0 50 100 7.6 7.5 7.4 DISABLE 7.3 7.2 −50 150 ENABLE 7.7 0 50 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 9. UVLO Threshold vs. Temperature Figure 10. Threshold IC Voltage vs. Temperature www.onsemi.com 7 150 NCV8876 THEORY OF OPERATION L ROSC ROSC Oscillator PWM Comparator NRVB440FS GDRV S Q Gate Drive R VOUT NVMFS5844NL CO RGDRV RL ISNS + VIN RSNS CSA Slope Compensation Voltage Error WAKEUP VOUT VEA VMICRO NCV8876 STATUS STATUS Compensation Figure 11. Current Mode Control Schematic Regulation output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV8876 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. The NCV8876 is a non−synchronous boost controller designed to supply a minimum output voltage during Start−Stop vehicle operation battery voltage sags. The NCV8876 is in low quiescent current sleep mode under normal battery operation (12 V) and is enabled when the supply voltage drops below the descending threshold (7.3 V for the NCV887600). Boost operation is initiated when the supply voltage is below the regulation set point (6.8 V for the NCV887600). Once the supply voltage sag condition ends and begins to increase, the NCV8876 boost operation will cease when the supply voltage increases beyond the regulation set point. The NCV8876 low quiescent current sleep mode resumes once the supply voltage increases beyond the ascending voltage threshold (7.7 V for the NCV887600). The NCV8876 VOUT pin serves the dual purpose: (1) powering the NCV8876 and (2) providing the regulation feedback signal. The feedback network is imbedded within the IC to eliminate the constant current battery drain that would exist with the use of external voltage feedback resistors. There is no soft−start operating mode. The NCV8876 will instantly respond to a voltage sag so as to maintain normal operation of downstream loads. Once the NCV8876 is enabled, the voltage error operational transconductance amplifier supplies current to set VC to 1.1 V to minimize the feedback loop response time when the battery voltage sag goes below the regulation set point. Current Limit The NCV8876 features two current limit protections, peak current mode and over current latch off. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. Set the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. If the voltage across the current sense resistor exceeds the over current threshold voltage the device enters over current hiccup mode. The device will remain off for the hiccup time of duration 1024/fosc. Current Mode Control The NCV8876 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the www.onsemi.com 8 NCV8876 UVLO ensure fast turn on times. The capacitor should be between 0.1 mF and 1 mF, depending on switching speed and charge requirements of the external MOSFET. VDRV uses an internal linear regulator to charge the VDRV bypass capacitor. VOUT must be decoupled at the IC by a capacitor that is equal or larger in value than the VDRV decoupling capacitor. Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis and will shut down when VIN drops below the UVLO threshold or the part is disabled. GDRV VDRV An RGND = 15 kW GDRV−GND resistor is strongly recommended. An internal regulator provides the drive voltage for the gate driver. Bypass with a ceramic capacitor to ground to APPLICATION INFORMATION Design Methodology follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. If the calculated Dmax is higher the Dmax of the NCV8876, the conversion will not be possible. It is important for a boost converter to have a restricted Dmax, because while the ideal conversion ration of a boost converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. If the following equation is not satisfied, the device will skip pulses at high VIN: This section details an overview of the component selection process for the NCV8876 in continuous conduction mode boost. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Operating Frequency 3. Select Current Sense Resistor 4. Select Output Inductor 5. Select Output Capacitors 6. Select Input Capacitors 7. Select Compensator Components 8. Select MOSFET(s) 9. Select Diode 10. Design Notes 11. Determine Feedback Loop Compensation Network D min w t on(min) fs Where: fs: switching frequency [Hz] ton(min): minimum on time [s] 2. Select Operating Frequency The default setting is an open ROSC pin, allowing the oscillator to operate at the default frequency Fs. Adding a resistor to GND increases the switching frequency. The graph in Figure 12, below, shows the required resistance to program the frequency. From 200 kHz to 500 kHz, the following formula is accurate to within 3% of the expected. 1. Define Operational Parameters Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] IOUT(max): maximum output current [A] ICL: desired typical cycle-by-cycle current limit [A] 100 90 From this the ideal minimum and maximum duty cycles can be calculated as follows: D max + 1 * 70 V IN(max) ROSC (kW) D min + 1 * 80 V OUT V IN(min) V OUT 60 50 40 30 Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. This is because a boost converter cannot have an output lower than the input. In situations where the input is higher than the output, the output will 20 10 0 150 200 250 300 350 400 FSW (kHz) 450 Figure 12. ROSC vs. FSW www.onsemi.com 9 500 550 NCV8876 R OSC + V OUT(ripple) + 2859 (F sw * 170) DI OUT(max) Where: fsw: switching frequency [kHz] ROSC: resistor from ROSC pin to GND [k] Note: The ROSC resistor ground return to the NCV8876 pin 3 must be independent of power grounds. fC OUT ǒ I OUT(max) 1*D ) V IN(min)D 2fL Ǔ R ESR The capacitors need to survive an RMS ripple current as follows: 3. Select Current Sense Resistor I Cout(RMS) + I OUT Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: RS + ) Ǹ D D WC ) WC 12 DȀ WC ǒ DȀ WC L R OUT T SW Ǔ 2 The use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. 6. Select Input Capacitors The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. V CL I CL Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desire current limit [A] I Cin(RMS) + V IN(WC) 2 D WC Lf sV OUT2 Ǹ3 4. Select Output Inductor 7. Select Compensator Components The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 20−40% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VOUT. After choosing a peak current ripple value, calculate the inductor value as follows: Current Mode control method employed by the NCV8876 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. L+ 8. Select MOSFET(s) In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: Q g(total) v Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: V IN(WC) D WC DI L,max f s Where: VIN(WC): VIN value as close as possible to half of VOUT [V] DWC: duty cycle at VIN(WC) DIL,max: maximum peak to peak ripple [A] The maximum average inductor current can be calculated as follows: I L,AVG + I Q(max) + I out ǸD DȀ The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: V OUTI OUT(max) V Q(max) + V OUT(max) V IN(min)h NVMFS5844NL 12 mW, 60 V SO−8FL package MOSFET is a recommended device. The Peak Inductor current can be calculated as follows: I L,peak + I L,avg ) I drv fs DI L,max 9. Select Diode 2 The output diode rectifies the output current. The average current through diode will be equal to the output current: Where: IL,peak: Peak inductor current value [A] I D(avg) + I OUT(max) 5. Select Output Capacitors The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: Additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: V D(max) + V OUT(max) www.onsemi.com 10 NCV8876 ♦ The maximum power dissipation in the diode can be calculated as follows: • P D + V f (max) I OUT(max) Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] The 4 amp, 40 V NRVB440MFS SO−8FL package Schottky diode is a recommended device. 11. Determine Feedback Loop Compensation Network 10. Design Notes The purpose of a compensation network is to stabilize the dynamic response of the converter. By optimizing the compensation network, stable regulation response is achieved for input line and load transients. Compensator design involves the placement of poles and zeros in the closed loop transfer function. Losses from the boost inductor, MOSFET, current sensing and boost diode losses also influence the gain and compensation expressions. The OTA has an ESD protection structure (RESD ≈ 502 W, data not provided in the datasheet) located on the die between the OTA output and the IC package compensation pin (VC). The information from the OTA PWM feedback control signal (VCTRL) may differ from the IC−VC signal if R2 is of similar order of magnitude as RESD . The compensation and gain expressions which follow take influence from the OTA output impedance elements into account. Type−I compensation is not possible due to the presence of RESD . The Figure 13 compensation network corresponds to a Type−II network in series with RESD . The resulting control−output transfer function is an accurate mathematical model of the IC in a boost converter topology. The model does have limitations and a more accurate SPICE model should be considered for a more detailed analysis: • The attenuating effect of large value ceramic capacitors in parallel with output electrolytic capacitor ESR is not considered in the equations. • The efficiency term h should be a reasonable operating condition estimate. • VOUT serves a dual purpose (feedback and IC power). • • • • • This is the location for connecting the compensation and current sense grounds. The IC architecture has a leading edge ISNS blanking circuit. In some instances, current pulse leading edge current spike RC filter may be required. ♦ If required, 120 pF + 750 W are a recommended evaluation starting point. The VDRV circuit has a current pulse power draw resulting in current flow from the output sense location to the IC. Trace ESL will cause voltage ripple to develop at IC pin VOUT which could affect performance. ♦ Use a 1 mF IC VOUT pin decoupling capacitor close to IC in addition to the VDRV decoupling capacitor. Classic feedback loop measurements are not possible (VOUT pin serves a dual purpose as a feedback path and IC power). Feedback loop computer modeling recommended. ♦ A step load test for stability verification is recommended. Compensation ground must be dedicated and connected directly to IC ground. ♦ Do not use vias. Use a dedicated ground trace. ROSC programming resistor ground must be dedicated and connected directly to IC ground ♦ Do not use vias. Use a dedicated ground trace. IC ground & current sense resistor ground sense point must be located on the same side of PCB. ♦ Vias introduce sufficient ESR/ESL voltage drop which can degrade the accuracy of the current feedback signal amplitude (signal bounce) and should be avoided. Star ground should be located at IC ground pad. L rL VIN Vd VOUT rCf ROUT Rds(on) VC COUT GDRV R2 RGDRV RESD C2 C1 ISNS R1 VCTRL OTA RLOW Ri R0 VREF VOUT GND Figure 13. NCV8876 OTA and Compensation www.onsemi.com 11 NCV8876 A worksheet as well as a SPICE model which may be used for selecting compensation components R2 , C1 , C2 is available at the ON Semiconductor web site (http://onsemi.com/PowerSolutions/product.do?id=NCV8 876). The following equations may be used to analyze the Figure 10 boost converter. Required input design parameters for analysis are: Vd = Boost diode Vf (V) VIN = Boost supply input voltage (V) Ri = Current sense resistor (W) RDS(on) = MOSFET RDS(on) (W) COUT = Bulk output capacitor value (F) Rsw_eq = RDS(on) + Ri, for the boost continuous conduction mode (CCM) expressions rCF = Bulk output capacitor ESR (W) ROUT = Equivalent resistance of output load (W) Pout = Output Power (W) L = Boost inductor value (H) rL = Boost inductor ESR (W) Ts = 1/fs, where fs = clock frequency (Hz) VOUT = Device specific output voltage (e.g. 6.8 V for NCV887601) (V) Vref = OTA internal voltage reference = 1.2 V R0 = OTA output resistance = 3 MW Sa = IC slope compensation (e.g. 53 mV/ms for NCV887601) gm = OTA transconductance = 1.2 mS D = Controller duty ratio D’ = 1 − D Necessary equations for describing the modulator gain (Vctrl−to−Vout gain) Hctrl_output(f) are described in Table 1. Table 1. BOOST CCM TRANSFER FUNCTION EXPRESSIONS Duty ratio (D) ȡ ȧ ȧ ȧ ȧ Ȣ −V 2R Ǹ ǒ OUT R OUT V V ƪ R ǒ V IN * R sw_eq)R *2 OUT V OUT d IN OUT V OUT Ǔ 2 ȣ ȧ ȧ ȧ ȧ Ȥ 2)2R V sw_eqV INV OUT*4V dR sw_eqV IN OUT IN 2 )R sw_eq 2V 2*4r V V *4r V 2 −4R sw_eqV OUT L d IN L OUT OUT 2R ǒVOUT 2 ) VdVINǓ OUT 1 1*D Vout/Vin DC Conversion Ratio (M) P OUT Average Inductor Current (Ilave) V INh V IN * I Laveǒr L ) R sw_eqǓ Inductor On−slope (Sn) L 1) Compensation Ramp (mc) Ri Sa Sn 1 r CFC OUT Cout ESR Zero (wz1) Right−half−plane Zero (wz2) Ǔƫ (1 * D ) L 2 ǒ R OUT * 2 Low Frequency Modulator Pole (wp1) R OUT r CFR OUT r CF ) R OUT ) Ts LM 3 mc C OUT p Ts Sampling Double Pole (wn) 1 p(m c(1 * D) * 0.5) Sampling Quality Coefficient (Qp) 1 Fm 2M ) www.onsemi.com 12 R Ǔ ǒ Ǔ T S OUT s 1 ) a 2 Sn 2 LM * rL L NCV8876 Table 1. BOOST CCM TRANSFER FUNCTION EXPRESSIONS hR OUT Hd Ri ǒ1 ) j z1Ǔ ǒ* j z2Ǔ 2pf w Control−output Transfer Function (Hctrl_output(f)) F mH d 2pf w ǒ1 ) j Ǔ ǒ1 ) j 2pf w p1 Ǔ ) ǒj 2pf wn 2pf w nQ p Ǔ 2 Once the desired cross−over frequency (fc) gain adjustment and necessary phase boost are determined from the Hctrl_output(f) gain and phase plots, the Table 2 equations may be used. It should be noted that minor compensation component value adjustments may become necessary when R2 ≤ ~10 · Resd as a result of approximations for determining components R2, C1, C2. Table 2. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES Desired OTA Gain at Cross−over Frequency fc (G) 10 ǒq Desired Phase Boost at Cross− over Frequency fc (boost) desired_G fc_gain_db 20 ǒHctrl_output(fc)Ǔ 180° * 90° Ǔ p margin * arg p 180° w p1e Select OTA Compensation Zero to Coincide with Modulator Pole at fp1 (fz) 2p f zf c ) f c 2 tan(boost) Resulting OTA High Frequency Pole Placement (fp) f c * f z tan(boost) Ǹ Compensation Resistor (R2) 1)ǒ Ǔ V OUT f pG fp Ǹ f p * f z 1.2 g m 1) Compensation Capacitor (C1) 1 2pf zR 2 Compensation Capacitor (C2) 1.2 g m 1 2pf pG V OUT OTA DC Gain (G0_OTA) V ref V OUT Low Frequency Zero (wz1e) High Frequency Zero (wz2e) ǒR 2 ) R esdǓȱ ȧ Ȳ ǒ Ǔȱ 1 R )R ȧ1 ) 2 R R C Ȳ ǒR ) R ) R Ǔȱ ȧ1 * R ǒR ) R ǓC Ȳ 1 2 R 2R esdC 2 2 1* esd 2 esd 2 Low Frequency Pole (wp1e) 1 2 0 2 2 0 esd esd 2 www.onsemi.com 13 2 fc ǒǓ fz fp g mR 0 Ǹ 1*4 Ǹ 1*4 Ǹ 1*4 R 2R esdC 2 ǒR 2 ) R esdǓ 2 C1 R 2R esdC 2 ǒR 2 ) R esdǓ 2 C1 ȳ ȧ ȴ ȳ ȧ ȴ R 2ǒR 0 ) R esdǓC 2 ǒR 0 ) R 2 ) R esdǓ 2 C1 ȳ ȧ ȴ NCV8876 Table 2. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES High Frequency Pole (wp2e) ȱ ȧ Ȳ ǒ Ǔ 1 R 0 ) R 2 ) R esd 1) 2 R ǒR ) R ǓC 2 0 esd 2 OTA Transfer Function (GOTA(f)) Ǹ 1*4 2pf 1 ) jw −G 0_OTA 1) z1e j w2pf p1e R 2ǒR 0 ) R esdǓC 2 ǒR 0 ) R 2 ) R esdǓ 2 C1 ȳ ȧ ȴ 2pf 1 ) jw 1) z2e j w2pf p2e The open−loop−response in closed−loop form to verify the gain/phase margins may be obtained from the following expressions. T(f) + G OTA(f)H ctrl_output(f) www.onsemi.com 14 NCV8876 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X S J SOLDERING FOOTPRINT* MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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