LV52133A D

LV52133A
Programmable DC-DC Converter,
±5V dual-output, Single-Inductor
Table. Correspondence table of between Vout1/2’s default voltages
and the marking vs product names
Default voltages
Marking
LV52133A0XA-VH
LV52133A5XA-VH
±5.0V
133A0 YMXX
±5.5V
133A5 YMXX
Features
 Dual-Outputs by Single-Inductor architecture
 VOUT1 default output voltage (+5.0V/+5.5V)
 VOUT2 default output voltage (–5.0V/ –5.5V)
 Adjustable both output voltages by I2C (I2C disable at standby)
 Operating voltage range 2.5V to 5.5V
 High speed inverted charge pump technology
 Short Circuit Protection
 Standby current dissipation 0.3A
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WLCSP15, 0.4mm pitch
( 2.15mm x 1.55mm, Amax=0.650 mm)
MARKING DIAGRAM
TOP view
133Ax
YMXX
Overview
LV52133A0XA and LV52133A5XA are dc-dc converters specifically
designed for LCD panels. These dc-dc converters generate two different output
voltages from a single inductor. Each of the output voltages are adjustable from
±4.1 V to ±5.7V. LCD panel power modules using these dc-dc converters can be
implemented within smaller board footprints, compared to converters that
require dual inductors. The short circuit protection function, integrated for both
positive and negative output pins, provides protection from continuous
overcurrent when the output is shorted. This feature enhances the safety of the
design. The extremely low standby current (0.3μA typical) enables longer
application operating time.
The differences of the LV52133A0XA-VH and LV52133A5XA-VH are
shown in below table.
= Device Mark
XX = Assembly lot Code
ORDERING INFORMATION
Ordering Code:
LV52133A0XA-VH
LV52133A5XA-VH
Typical Applications
 Mobile LCD panel power supply
 General around ±5.0V applications
Package
WLCSP15 (2.15x1.55)
(Pb-Free / Halogen Free)
Shipping (Qty / packing)
4000 / Tape & Reel
† For information on tape and reel specifications, including part
orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D.
http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
2
* I C Bus is a trademark of Philips Corporation.
Typical Application Diagram
© Semiconductor Components Industries, LLC, 2016
June 2016- Rev. 2
1
Publication Order Number:
LV52133A/D
LV52133A
Specifications
Absolute Maximum Ratings at Ta = 25C (Note 1)
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VINmax
VIN to GNDs
+6
V
Maximum Pin voltage1
Vpin1max
CN,VOUT2 to GNDs
–6
V
Maximum Pin voltage2
Vpin2max
LX
+7
V
Maximum Pin voltage3
Vpin3max
Other pin to GNDs
+6
V
Allowable power dissipation
Pdmax
Ta=25°C The specified board (Note2)
1
W
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
1. Stresses exceeding those listed in the Maximum Rating table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
2. Mounted on a specified board: 50mm×50mm×1mm (2 layer glass epoxy)
3. Absolute maximum ratings represent the values which cannot be exceeded for any length of time.
4. Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high
current, high voltage, or drastic temperature change, the reliability of the IC may be decrease. Please contact ON Semiconductor for the
further details.
Pd-max
Ambient temperature [°C]
(Note 2) Mounted on a specified board: 50mm×50mm×1mm (2 layer glass epoxy)
Recommended Operating Conditions at Ta = 25C (Note 5)
Parameter
Symbol
Supply voltage range
VINop
Conditions
Ratings
Unit
2.5 to 5.5
V
5. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.
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2
LV52133A
Electrical Characteristics (Note 6)
VIN=3.7V VOUT1=5.0V VOUT2=-5.0V at Ta  25C, (Unless otherwise noted)
Parameter
Ratings
Symbol
Conditions
ICC1
EN1=EN2=OFF
0.3
A
ICLBST
LX
1.2
A
VOUT1 voltage
VOUT1
Default
5.0/5.5
V
VOUT1 voltage range
VOUT1
100mVsteps by I2C
VOUT1 voltage accuracy
VOUT1
VOUT1 current
IOUT1
IOUT2=0
200
mA
VOUT1 line regulation
VLINR1
dVo=1V Io=30mA
0.3
%/V
VOUT1 load regulation
VLDR1
Io=2mA/150mA
4
mV
Discharge Resistance 1
RVO1
70

Soft-start
tssvo1
0.6
ms
–5.0/–5.5
V
min
typ
max
Unit
VIN current
Standby current
VBST Boost Converter
VBST current limit
VOUT1 LDO
4.1
5.7
–1
1
V
%
VOUT2 Inverted Charge pump
VOUT2 voltage
VOUT2
Default
VOUT2 voltage range
VOUT2R
100mV steps by I2C
VOUT2 voltage accuracy
VOUT2A
–5.7
–4.1
V
–1
1
%
VOUT2 current
IOUT2
IOUT1=0
100
mA
VOUT2 line regulation
VLINR2
dVo=1V Io=30mA
0.3
%/V
VOUT2 load regulation
VLDR2
Io=2mA/60mA
20
mV
Discharge Resistance 2
RVO2
20

Soft-start
tssvo2
0.8
ms
Oscillator
OSC frequency1
Fosc1
Boost converter
1.48
1.85
2.22
MHz
OSC frequency2
Fosc2
Inverted charge pump
0.74
0.925
1.11
MHz
Under Voltage Locked Out
UVLO up
Vuvlo_h
VIN up
2.3
V
UVLO down
Vuvlo_l
VIN down
2.1
V
High level input voltage
VINH
SDA/SCL/EN1/EN2
1.26
VIN
V
Low level input voltage
VINL
SDA/SCL/EN1/EN2
0
0.54
V
Pulldown Resistance1
Rpd1
EN1
400
k
Pulldown Resistance2
Rpd2
EN2
200
k
Control Input
6. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
LV52133A
TYPICAL OPERATING CHARACTERISTICS
VIN=3.7V at Ta  25C, (Unless otherwise noted)
Load regulation of Vout1
The load current is from Vout1 to Vout2.
Load regulation of Vout2
The load current is from Vout1 to Vout2.
Line regulation of Vout1
The load current is 20mA from Vout1 to Vout2.
Efficiency
The load current is from Vout1 to Vout2.
Line regulation of Vout2
The load current is 20mA from Vout1 to Vout2.
Startup waveform example
The output voltages are set |5.0V|.
Vbst
Vout1
Ivin
Ten1
Ten2
Ten1: EN1 pin = ON, Ten2: EN2 pin = ON
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4
Vout2
LV52133A
TYPICAL OPERATING CHARACTERISTICS
VIN=3.7V at Ta  25C, (Unless otherwise noted)
Shutdown waveform2
This case is set ENs off separately.
Shutdown waveform1
This case is set both EN off simultaneously.
Vout1
Vout1
EN2
EN1/EN2
EN1
Vout2
Vout2
Boost converter - switching waveform1
The load current is 5mA from Vout1 to Vout2.
Boost converter - switching waveform2
The load current is 50mA from Vout1 to Vout2.
LX
LX
Inductor
current
Inductor
current
ch2: offset=200mA
ch2: offset=400mA
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5
LV52133A
Package Dimensions
unit : mm
WLCSP15, 2.15x1.55
CASE 567HY
ISSUE B
E
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. BACKSIDE COATING IS OPTIONAL.
B
PIN A1
REFERENCE
BACKSIDE
COATING
A3
NOTE 4
D
DETAIL A
0.05 C
2X
0.05 C
2X
DIM
A
A1
A3
b
D
E
e
TOP VIEW
DETAIL A
MILLIMETERS
MIN
MAX
0.65
−−−
0.16
0.26
0.025 REF
0.21
0.31
2.15 BSC
1.55 BSC
0.40 BSC
A
0.10 C
A1
0.08 C
NOTE 3
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
A1
15X
PACKAGE
OUTLINE
e
b
0.05 C A B
0.03 C
E
e
0.40
PITCH
D
C
15X
0.40
PITCH
B
0.20
DIMENSIONS: MILLIMETERS
A
1
2
3
BOTTOM VIEW
LV52133A0XA-VH/LV52133A5XA-VH is as follows.
133Ax
YMXX
MARKING DIAGRAM
Top view
Top view (1)
Top view (2)
= Device Mark
XX = Assembly lot Code
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6
Bottom view
LV52133A
Pin Function
PIN #
Pin Name
Description
A1
EN2
Enable1 input pin
A2
VOUT2
VOUT2 output pin
A3
CN
Flying capacitor connection pin for charge pump
B1
EN1
Enable1 input pin
B2
SCL
I2C clock signal input pin
B3/E1
PGND
C1
VIN
Power supply voltage
C2
SDA
I2C data signal input / output pin
C3
CP
Flying capacitor connection pin for charge pump
D1
LX
Boost converter switching pin
D2
SGND
Signal Ground
D3/E2
VBST
Boost converter direct output pin
E3
VOUT1
Power Ground
VOUT1 output pin
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LV52133A
I2C serial bus communication
BITMAP ( I2C control ) / I2C disable at standby
WRITE: IC Address : 0111110x x=0:Write mode / x=1:inhibition
Sub
Address
MSB
(7)
(6)
(5)
(4)
(3)
(2)
(1)
LSB
(0)
VOUT1
0000 0000
-
-
-
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT2
0000 0001
-
-
-
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VOUT1 [V]
not use
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0*
5.1
5.2
5.3
5.4
5.5**
5.6
5.7
VOUT2 [V]
not use
–4.1
–4.2
–4.3
–4.4
–4.5
–4.6
–4.7
–4.8
–4.9
–5.0*
–5.1
–5.2
–5.3
–5.4
–5.5**
–5.6
–5.7
* :default = ±5.0V ( LV52133A0XA-VH )
** :default = ±5.5V ( LV52133A5XA-VH )
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8
LV52133A
Serial Bus Communication Specifications
Standard mode
Parameter
symbol
Conditions
min
typ
max
unit
0
-
100
kHz
SCL clock frequency
fscl
SCL clock frequency
Data set up time
ts1
SCL setup time relative to the fall of SDA
4.7
-
-
s
ts2
SDA setup time relative to the rise of SCL
250
-
-
ns
ts3
SCL setup time relative to the rise of SDA
4.0
-
-
s
th1
SCL data hold time relative to the rise of SDA
4.0
-
-
s
th2
SDA hold time relative to the fall of SCL
0
-
-
s
twL
SCL pulse width for the L period
4.7
-
-
s
twH
SCL pulse width for the H period
4.0
-
-
s
Data hold time
Pulse width
Input waveform
conditions
ton
SCL and SDA (input) rise time
-
-
1000
ns
tof
SCL and SDA (input) fall time
-
-
300
ns
Bus free time
tbuf
Time between STOP and START conditions
4.7
-
-
s
min
typ
max
unit
0
-
400
kHz
High-speed mode
Parameter
Symbol
Conditions
SCL clock frequency
fscl
SCL clock frequency
Data setup time
ts1
SCL setup time relative to the fall of SDA
0.6
-
-
s
ts2
SDA setup time relative to the rise of SCL
100
-
-
ns
ts3
SCL setup time relative to the rise of SDA
0.6
-
-
s
th1
SCL data hold time relative to the rise of SDA
0.6
-
-
s
th2
SDA hold time relative to the fall of SCL
0
-
-
s
Pulse width
twL
SCL pulse width for the L period
1.3
-
-
s
twH
SCL pulse width for the H period
0.6
-
-
s
Input waveform
conditions
ton
SCL and SDA (input) rise time
-
-
300
ns
tof
SCL and SDA (input) fall time
-
-
300
ns
Bus free time
tbuf
Time between STOP and START conditions
1.3
-
-
s
Data hold time
I2C serial transfer timing conditions
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LV52133A
When SCL is "H", change of SDA from "L" to "H"
enables the stop conditions to stop access.
Input waveform condition
I2C control transmission method
In start and stop conditions of the I2C bus, SDA
should be kept in the constant state while SCL is "H"
as shown below during data transfer.
When data transfer is not made, both SCL and SDA
are in the "H" state.
When SCL = SDA="H", change of SDA from "H" to
"L" enables the start conditions to start access.
Data transfer and acknowledgement
response
After establishment of start conditions, Data transfer
is made by one byte (8-bits). Data transfer enables
continuous transfer of any number of bytes. Each time
of the 8-bit data is transferred, the ACK signal is sent
from the receive side to the send side. The ACK signal
is issued when SDA(on the send side) is released and
SDA(on the receive side) is set "L" immediately after
fall of the clock pulse at the SCL eighth bit of data
transfer to "L". When the next 1-byte transfer is left in
the receive state after transmission of the ACK signal
from the receive side, the receive side releases SDA at
fall of the SCL ninth clock. In the I2C bus, there is no
CE signal. Instead, 7-bit slave address is assigned to
each device and the first byte of transfer is assigned to
the command (R/W) representing the 7-bit slave
address and subsequent transfer direction. Note that
only WRITE is valid in this IC. The 7-bit address is
transferred sequentially from MSB and the eighth bit
is "L" representing WRITE.
Input 1data
Input 2data (register address auto Increment)
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LV52133A
Detailed Descriptions
(PWM) regulator. At rated load, each converter
operates at continuous conduction mode (CCM). At
light loads, both converters can enter in discontinuous
conduction mode (DCM). A cycle-by-cycle peak
current limit and thermal provide value added features
to protect the device.
The LV52133A has dual-output VOUT1 (LDO) and
VOUT2 (built-in inverted charge pump) with single
inductor. Both output voltages are separately
controlled by I2C control and pin EN1/EN2. Boost
converter is a fixed-frequency pulse width modulated
LX
Block Diagram
VBST
Vbat
SW
Control
VIN
Isense
TSD
UVLO
ILIM
OSC
VBST
adj
VOUT1
adj
LDO
DISCHARGE
VOUT1
VBST
Enable1
adj
CP
Charge Pump
Control
CN
SDA
SCL
EN1
EN2
VOUT2
I2C
/EN
DISCHARGE
Enable1
Enable2
SGND
Enable2
PGND
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11
VOUT2
LV52133A
Recommendation Applications
2.5V to 5.5V
Vbat
4.7uH
LX
VIN
4.7uF
PGND
VBST
4.7uF
CP
2.2uF
VOUT1
VOUT1
CN
4.7uF
VOUT2
SGND
4.7uF
SDA
EN1
SCL
EN2
VOUT2
2.8V to 5.5V
Vbat
2.2uH
LX
VIN
4.7uF
PGND
VBST
CP
4.7uF
10uF
VOUT1
VOUT1
CN
4.7uF
SGND
VOUT2
10uF
SDA
EN1
SCL
EN2
VOUT2
Fig. Recommendation Applications
Table . Component List for Typical Characteristics Circuit
Reference
C
L
Description
Manufacturer and Part Number
2.2F, ±10%, 10V, X5R, ceramic
TDK – C1608X5R1A225K
4.7F, ±10%, 10V, X5R, ceramic
TDK – C1608X5R1A475K
10F, ±10%, 10V, X5R, ceramic
TDK – C1608X5R1A106K
2.2H, 1.1A, 120mΩ, 2.5mm×2.0mm×1.1mm
TDK – MLP2520V2R2ST0S1
4.7H, 0.8A, 220mΩ, 2.5mm×2.0mm×1.1mm
TDK – MLP2520V4R7ST0S1
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LV52133A
Inductor Selection
Start/Shutdown Sequencing
Three different electrical parameters need to be
considered when selecting an inductor, the value of
the inductor, the saturation current and the DCR.
During normal and heavy load operation, the
LV52133A is intended to operate in Continuous
Conduction Mode (CCM). The equation below can be
used to calculate the peak current.
The pins EN1/EN2 are used as enable input logic.
An active high logic level on those pins enables the
device. A built-in pull-down resistor disables the
device if the pin is left open. If a high logic signal is
applied, the LV52133A starts with timing sequence as
depicted below figure that is as in often cases of panel
power supply. In the figure, VOUT1’s ramp up time is
shown as 600s. This is the case that the VOUT1
output capacitance is selected 4.7F. If the
capacitance is 10F, the ramp up time becomes 1.3ms.
according to next formula. The Trampup had better be
kept within 2.5ms in order to avoid highly inrush
current. If the time is over 2.5ms, IC can also wake up
with larger current limiter, which is described in OCP
section. And next, time of VOUT2’s ramp-up is also
same idea as VOUT1. Please estimate by changing the
600s to 800s in the same expression.
Ipeak_p = Iout1 / (n1 x ( 1– D1 ))
+ ( VIN x D1 ) / 2 x L1 x Fosc1
VIN: battery voltage, IOUT1:load current, L:inductor
value, Fosc1: OSC frequency1, D1:duty cycle,
n1:converter efficiency varies with load current.
A good approximation is to use η = 0.85. It is
important to ensure that the inductor current rating is
high enough such that it not saturate. As the inductor
size is reduced, the peak current for a given set of
conditions increases along with higher current ripple
so it is not possible to deliver maximum output power
at lower inductor values. Finally an acceptable DCR
must be selected regarding losses in the inductor and
must be lower than 250mΩ (typical) to limit excessive
voltage drop. In addition, as DCR is reduced, overall
efficiency will improve. The inductor value is
recommended to use a 4.7H or 2.2H.
POR function
This is “Power On Reset” function to reset internal
logic circuits. This function can be worked by
reducing IC’s VIN voltage until about 1V.
Recommended 5ms
Cx
T
 600 us 
rampup
4.7uF
Typically the next step is starting of panel load in
the case of VOUT2. The timing from EN2=ON is
needed over 2.5ms and over calculated time with the
above equations. This is only to avoid unnecessary
inrush current. Even if over the time, each output
involves the unnecessary inrush current, but is able to
wake up outputs.
When each EN is off, active discharge resistance
work always in each output, and the output voltage
goes to GND voltage.
Recommended 5ms
800us
EN1
EN2
VBST
VOUT1
1.05ms
2.5ms
600us
200us
800us
VOUT2
Iin
Panel
Load
Fig. Typically Sequence Diagram
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13
LV52133A
OCP and SCP function
(2) Heavy load of during ramp up
IC has OCP and SCP function and explained the
behavior shown in figures below in some situations.
As shown in the below fig, if it is not reaching target
voltage at the end of the 2.5ms for some reasons as
large capacitance or large load current, then the OCP
is changed to 230mA mode till reaching the target
voltage. And after the reaching the target voltage,
OCP is changed to depending on VBST mode.
(1) OCP limit transition in normal operation
The OCP means “Over Current Protection” and is
equipped for preventing excessive inrush current
about Vout1 in the startup sequence and more. It
watches for limit of 40mA during 2.5msec from ramp
up of Vout1, and then changes almost free, which
mean depending on VBST current capacity.
Therefore in the case that the load current is under
230mA, VOUT1 voltage can be raised. But from the
viewpoint of suppressing the inrush current (about
500mA), the use of this 230mA is better to avoid as
much as possible by capacitance selection and timing
design of panel module.
EN1 EN2
VBST
2.5ms
IL=no load
IL<230mA
VOUT1
Depending on VBST
230mA
VOUT1
current limiter
40mA
Fig. OCP behavior in some situations
(3) SCP function
The SCP means “Short Circuit Protection”. This is
used to protect each Vout when they are connected to
the GND. SCP function becomes active when Vout
voltage reaches under 60% of its target voltage. Once
SCP is activated, the counter begins to count 10msec. If
the SCP detection is active for full 10msec, IC then gets
shut down and latch. On the other hand, if the Vout
voltage is recovered within this 10msec IC will
reactivate. This latch is released by setting EN1 and
EN2 to off.
Reference sequence design
For start up
(1) EN1=H ;
(2) After 5msec from (1), EN2=H;
(3) 5msec later, start panel load;
For shut down
(1) stop panel load;
(2) EN1 and EN2 = L;
(3) till Next EN1=H, space more than 1msec;
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LV52133A
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