NCP1532 D

NCP1532
Dual Output Step-Down
Converter 2.25 MHz
High-Efficiency, Out of
Phase Operation, Low
Quiescent Current, Source
up to 1.6 A
The NCP1532 dual step down DCDC converter is a monolithic
integrated circuit dedicated to supply core and I/O voltages of new
multimedia design in portable applications powered from 1−cell
Li−ion or 3 cell Alkaline / NiCd / NiMH batteries.
Both channels are externally adjustable from 0.9 V to 3.3 V and can
source totally up to 1.6 A, 1.0 A maximum per channel. Converters are
running at 2.25 MHz switching frequency which reduces component
size by allowing the use of small inductor (down to 1 mH) and
capacitors and operates 180° out of phase to reduce large amount of
current demand on the battery. Automatic switching PWM/PFM mode
and synchronous rectification offer improved system efficiency. The
device can also operate into fixed frequency PWM mode for low noise
applications where low ripple and good load transients are required.
Additional features include integrated soft−start, cycle−by−cycle
current limit and thermal shutdown protection. The device can also be
synchronized to an external clock signal in the range of 2.25 MHz.
The NCP1532 is available in a space saving, ultra low profile
3x3 x 0.55 mm 10 pin mDFN package.
Features
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Up to 97% Efficiency
50 mA Quiescent Current
Synchronous Rectification for Higher Efficiency
2.25 MHz Switching Frequency, 180° Out of Phase
Sources up to 1.6 A, 1.0 A Maximum per Channel
Adjustable Output Voltage from 0.9 V to 3.3 V
Mode Selection Pin: Eco Mode or Low Noise Mode
2.7 V to 5.5 V Input Voltage Range
Thermal Limit Protection
Short Circuit Protection
All pins are fully ESD Protected
This is a Pb−Free Device
MARKING
DIAGRAM
1532
AA
AaLYWG
G
UDFN10
MU SUFFIX
CASE 506AT
Aa
= Assembly Location
(may be 1 or 2 characters)
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
L
Y
W
G
(Note: Microdot may be in either location)
PIN CONNECTION
FB1
1
10
EN1
VIN
2
3
9
8
SW1
4
7
SW2
GND
5
6
MODE/
SYNC
FB2
EN2
POR
(Top View)
UDFN10
ORDERING INFORMATION
Device
Package
Shipping†
NCP1532MUAATXG
UDFN10
(Pb−Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Applications
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Cellular Phones, Smart Phones and PDAs
Digital Still Cameras
MP3 Players and Portable Audio Systems
Wireless and DSL Modems
Portable Equipment
© Semiconductor Components Industries, LLC, 2011
October, 2011 − Rev. 6
1
Publication Order Number:
NCP1532/D
VIN
2.2mH
3
VIN
5
SW1
4
GND
FB1
1
POR
8
SW2
7
FB2
10
11
OFF
ON
2
EN1
OFF
ON
6
MODE/SYNC
OFF
ON
9
EN2
10mF
POR
2.25 MHz Range
NOTE:
VOUT1
18pF
VIN or VOUT
NCP1532
2.2mH
VOUT2
18pF
10mF
Exposed pad of UDFN10 package − named pin11 − must be connected to system ground.
Figure 1. NCP1532 Typical Application
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
1
FB1
Analog Input
Feedback voltage from the output 1. This is the input to the error amplifier.
2
EN1
Digital Input
Enable for converter 1. This pin is active HIGH (higher than 1.2 V) and is turned off by
logic LOW (lower than 0.4 V.
Do not leave this pin floating.
3
VIN
Analog / Power
Input
Power supply input for the PFET power stage, analog and digital blocks. The pin must
be decoupled to ground by a 10 mF ceramic capacitor.
4
SW1
Analog Output
Connection from power MOSFETs of output 1 to the Inductor.
5
GND
Analog Ground
This pin is the GROUND reference for the analog section of the IC. The pin must be
connected to the system ground by 10 mF low ESR ceramic capacitor.
6
MODE/SYNC
Digital Input
7
SW2
Analog Output
Connection from power MOSFETs of output 2 to the Inductor.
8
POR
Digital Output
Power On Reset. This is an open drain output. This output is shutting down when each
output voltages are less than 90% of their nominal values and goes high after 120 ms
when active outputs are within regulation. A pullup resistor around 500k should be
connected between POR and VIN, VOUT1 or VOUT2 depending on the supplied device.
9
EN2
Digital Input
Enable for converter 2. This pin is active HIGH (higher than 1.2 V) and is turned off by
logic LOW (lower than 0.4 V). Do not let this pin floating.
Feedback voltage from the output 2. This is the input to the error amplifier.
10
FB2
Analog Input
11
Exposed Pad
Power Ground
Description
Combination Mode Selection and Oscillator Synchronization. If this pin is LOW, the
regulator runs in automatic switching PFM/PWM. With a HIGH level (equal or lower
Analog Input voltage), the converter runs in PWM mode only. This pin can be also synchronized to an external clock in the range of 2.25 MHz; in this case the device runs in
PWM mode only. Insert the clock before enabling the part is recommended to force
external synchronization. Do not let this pin floating.
Following rule is being used:
”0”: Eco mode, automatic switching PFM/PWM, 180° out of phase.
“1”: Low noise, forced PWM mode, 180° out of phase.
”CLK”: External synchronization, forced PWM mode, 0° in phase.
This pin is the GROUND reference for the NFET power stage of the IC. The pin must
be connected to the system ground and to both input and output capacitors.
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NCP1532
BLOCK DIAGRAM
EA1
FB1
1
EA2
UVLO
VREF
VREF
Thermal
Shutdown
EN1
VIN
3
EA2
Oscillator
SW1
4
Q1
Q2
GND
AVIN
AVIN
0°
180°
PWM/PFM
Control
PWM/PFM
Control
5
ILIMIT
ILIMIT
Figure 2. Simplified Block Diagram
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3
EN2
8
POR
7
SW2
6
MODE/SYNC
VIN
Ramp Generator
PVIN
9
Logic
Control
Voltage
Reference
EA1
FB2
VIN
2
Logic
Control
10
PVIN
Q3
Q4
NCP1532
MAXIMUM RATINGS
Rating
Minimum Voltage All Pins
Maximum Voltage All Pins (Note 1)
Maximum Voltage EN1, EN2, MODE
Thermal Resistance Junction−to−Air (UDFN10 Package)
Thermal Resistance Using Recommended Board Layout (Note 8)
Operating Ambient Temperature Range (Notes 6 and 7)
Storage Temperature Range
Junction Operating Temperature (Notes 6 and 7)
Latchup Current Maximum Rating TA = 85°C (Note 4) Other Pins
Symbol
Value
Unit
Vmin
−0.3
V
Vmax
7.0
V
Vmax
VIN + 0.3
V
RqJA
200
40
°C/W
TA
−40 to 85
°C
Tstg
−55 to 150
°C
TJ
−40 to 150
°C
Lu
$100
mA
2.0
200
kV
V
1
per IPC
ESD Withstand Voltage (Note 3)
Human Body Model
Machine Model
Vesd
Moisture Sensitivity Level (Note 5)
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C
2. According JEDEC standard JESD22−A108B
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114
Machine Model (MM) per JEDEC standard: JESD22−A115
4. Latchup current maximum rating per JEDEC standard: JESD78.
5. JEDEC Standard: J−STD−020A.
6. In applications with high power dissipation (low VIN, high IOUT), special care must be paid to thermal dissipation issues. Board design
considerations − thermal dissipation vias, traces or planes and PCB material − can significantly improve junction to air thermal resistance
RqJA (for more information, see design and layout consideration section). Environmental conditions such as ambient temperature Ta brings
thermal limitation on maximum power dissipation allowed.
The following formula gives calculation of maximum ambient temperature allowed by the application: TA(max) = TJ(max) − (RqJA x Pd)
Where
TJ is the junction temperature,
Pd is the maximum power dissipated by the device (worst case of the application), and RqJA is the junction−to−ambient thermal
resistance.
7. To prevent permanent thermal damages, this device include a thermal shutdown which engages at 180°C (typical).
8. Board recommended UDFN10 layout is described in Layout Considerations section.
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NCP1532
ELECTRICAL CHARACTERISTICS
(Typical values are referenced to TA = +25°C, Minimum and Maximum values are referenced −40°C to +85°C ambient temperature,
unless otherwise noted, operating conditions VIN = 3.6 V, VOUT1 = VOUT2 = 1.2 V, unless otherwise noted).
Conditions
Rating
Symbol
Min
Typ
Max
Unit
VIN
2.7
−
5.5
V
−
−
50
60
70
−
ISTB
−
0.3
1.0
mA
VUVLO
2.2
2.4
2.55
V
VUVLOH
−
100
−
mV
INPUT VOLTAGE
Input Voltage Range
Quiescent Current,
No Switching, No Load
No Load
MODE/SYNC = GND
Standby Current
EN1 = EN2 = GND
Under Voltage Lockout
VIN Falling
Under Voltage Hysteresis
IQ
mA
ANALOG AND DIGITAL PIN
Positive Going Input High Voltage Threshold
EN1, EN2, MODE/SYNC
VIH
1.2
−
−
V
Negative Going Input High Voltage Threshold
EN1, EN2, MODE/SYNC
VIL
−
−
0.4
V
Digital Threshold Hysteresis
EN1, EN2, MODE/SYNC
VHYS
−
100
−
External Synchronization (Note 11)
Minimum
Maximum
MODE/SYNC
FSYNC
−
−
1.8
3.0
−
−
mV
MHz
POWER ON RESET (Note 9)
Power On Reset Threshold
VOUT Falling
Power On Reset Hysteresis
Power On Reset Delay (See Page 12)
VPORT
−
89%
−
V
VPORH
−
3%
−
V
TPOR
−
116
−
ms
VFB
−
0.6
−
V
VOUT
−
0.9
−
V
OUTPUT PERFORMANCES
Feedback Voltage Threshold
FB1, FB2
Minimum Output Voltage
Maximum Output Voltage
VOUT
−
3.3
−
V
Output Voltage Accuracy (Note 10)
Room Temperature
Overtemperature Range
DVOUT
−
−3%
$1%
$2%
−
+3%
%
Output Voltage load regulation
NCP1532MUAATXG
Overtemperature
Load = 100 mA to 600 mA
VLOADR
−
−0.6
−
Load transient response
Rise/Falltime 1 ms
10 mA to 100 mA load step
(PFM to PWM mode)
200 mA to 600 mA load step
(PWM to PWM mode)
VLOADT
−
40
−
−
85
−
Output Voltage Line Regulation
Load = 100 mA
VIN = 2.7 V to 5.5 V
VLINER
−
0.05
−
%
Line Transient Response
Load = 100 mA
3.6 V to 3.2 V Line Step
(Falltime = 50 ms)
VLINET
−
6.0
−
mVPP
Output Voltage Ripple
IOUT = 0 mA
IOUT = 300 mA
VRIPPLE
−
−
8.0
3.0
−
−
mVPP
Soft−Start Time
Time from EN to 90% of Output
Voltage
tSTART
−
230
350
ms
FSW
1.8
2.25
2.7
MHz
D
−
−
100
%
Switching Frequency
Duty Cycle
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5
%
mV
NCP1532
ELECTRICAL CHARACTERISTICS
(Typical values are referenced to TA = +25°C, Minimum and Maximum values are referenced −40°C to +85°C ambient temperature,
unless otherwise noted, operating conditions VIN = 3.6 V, VOUT1 = VOUT2 = 1.2 V, unless otherwise noted).
Rating
Conditions
Symbol
Min
Typ
Max
Unit
High−Side MOSFET On−Resistance
RONHS
−
400
−
mW
Low−Side MOSFET On−Resistance
RONLS
−
300
−
mW
High−Side MOSFET Leakage Current
ILEAKHS
−
0.05
−
mA
Low−Side MOSFET Leakage Current
ILEAKLS
−
0.01
−
mA
IPK
1.2
1.6
−
A
Thermal Shutdown Threshold
TSD
−
180
−
°C
Thermal Shutdown Hysteresis
TSDH
−
40
−
°C
POWER SWITCHES
PROTECTION
DC−DC Short Circuit Protection
Peak Inductor Current
9. Refer to Power On Reset section for more information.
10. The overall output voltage tolerance depends upon the accuracy of the external resistor (R1 and R2).
11. Guaranteed by design.
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NCP1532
TABLE OF GRAPHS
TYPICAL CHARACTERISTICS FOR STEP DOWN CONVERTER
Efficiency
h
FIGURE
vs. Output Current
3, 4, 5, 6, 7, 8
Iq ON
Quiescent Current, PFM no load
vs. Input Voltage
11
Iq OFF
Standby Current, EN Low
vs. Input Voltage
10
vs. Ambient Temperature
16
vs. Load Current
13
FSW
Switching Frequency
VLOADR
Load Regulation
VLOADT
Load Transient Response
VLINER
Line Regulation
tSTART
Soft Start
18
Short Circuit Protection
19
IPK
14, 15
vs. Output Current
12
VUVLO
Under Voltage Lockout Threshold
vs. Ambient Temperature
20
VIL, VIH
Enable Threshold
vs. Ambient Temperature
21
1000
Iout1 (mA)
950
900
850
800
750
700
650
Eff (%)
600
0.9−0.95
550
0.85−0.9
500
0.8−0.85
450
0.75−0.8
400
0.7−0.75
350
300
250
200
150
100
50
Iout2 (mA)
0
1000
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
Figure 3. Efficiency vs. Output Current (VIN = 3.6 V, VOUT1 = 1.8 V, VOUT2 = 1.8 V, Temperature = 255C)
MODE/SYNC Pin = GND
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NCP1532
90
80
80
EFFICIENCY (%)
100
90
EFFICIENCY (%)
100
70
60
50
PFM
40
30
20
50
0
100
200
300
400
500
30
0
600
PWM
1000
Figure 5. Efficiency vs. Output Current
VIN = 3.6 V, VOUT1 = 1.2 V, EN2 = GND
100
95
90
90
85
85
80
−40°C
75
70
65
85°C
25°C
60
80
70
2.7 V
65
60
3.6 V
55
50
45
45
200
400
600
800
IOUT1, OUTPUT CURRENT (mA)
VBAT = 5.5 V
75
50
40
0
1000
Figure 6. Efficiency vs. Output Current
VIN = 3.6 V, VOUT1 = 1.2 V, EN2 = GND,
Temperature = 255C
200
400
600
800
IOUT1, OUTPUT CURRENT (mA)
1000
Figure 7. Efficiency vs. Output Current
VOUT1 = 1.2 V, EN2 = GND, Temperature = 255C
100
100
95
VOUT = 3.3 V
90
99
98
80
EFFICIENCY (%)
85
VOUT = 1.2 V
75
70
65
60
55
97
96
95
94
93
92
50
91
45
40
100
Figure 4. Efficiency vs. Output Current
VIN = 3.6 V, VOUT1 = 1.2 V, EN2 = GND
95
0
10
IOUT1, OUTPUT CURRENT (mA)
100
40
1
IOUT1, OUTPUT CURRENT (mA)
55
EFFICIENCY (%)
PFM
40
10
EFFICIENCY (%)
EFFICIENCY (%)
60
20
PWM
10
0
70
90
0
200
400
600
800
1000
5.5
5.0
4.5
4.0
3.5
3.0
IOUT1, OUTPUT CURRENT (mA)
VIN, INPUT VOLTAGE (V)
Figure 8. Efficiency vs. Output Current
VIN = 3.6 V, EN2 = GND, Temperature = 255C
Figure 9. Maximum Efficiency vs. Input Voltage
VOUT1 = VOUT2 = 3.3 V IOUT1 = IOUT2 = 100 mA
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8
60
0.9
55
Iq, QUIESCENT CURRENT (mA)
1.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
3.0
3.5
4.0
4.5
45
40
35
30
25
3.5
4.0
4.5
5.0
5.5
Figure 10. Standby Current vs. Input Voltage
VIN = 3.6 V, EN1 = EN2 = GND,
Temperature = 255C
Figure 11. Quiescent Current vs. Input Voltage
VIN = 3.6 V, VFB1 = VFB2 = 0.8 V
15
15
85°C
0
25°C
−40°C
−10
−15
−20
5.2
3.0
VIN, INPUT VOLTAGE (V)
20
−5
Buck2
Buck1
VIN, INPUT VOLTAGE (V)
10
LINE REG (mV)
50
20
5
Buck1 & Buck2
20
2.5
5.5
5.0
LOAD REGULATION (mV)
ISB, STANDBY CURRENT (mA)
NCP1532
10
5
−40°C
0
−5
85°C
25°C
−10
−15
4.7
4.2
3.7
3.2
−20
2.7
0
200
400
600
800
VIN, INPUT VOLTAGE (V)
IOUT1, OUTPUT CURRENT (mA)
Figure 12. Line Regulation
VOUT1 = 1.2 V, IOUT1 = 100 mA, EN2 = GND
Figure 13. Load Regulation
VIN = 3.6 V, VOUT1 = 1.2 V, EN2 = GND
Figure 14. Load Transient and Crosstalk,
VIN = 3.6 V VOUT1 = 1.2 V, IOUT1 from
200 mA to 600 mA VOUT2 = 1.2 V,
IOUT2 = 600 mA, 8 mV Crosstalk
1000
Figure 15. Load Transient and Crosstalk,
VIN = 3.6 V VOUT1 = 1.2 V, IOUT1 from 200 mA
to 600 mA VOUT2 = 1.2 V, IOUT2 = 600 mA,
8 mV Crosstalk
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NCP1532
5
4
FSW, DRIFT (%)
3
2
3.6 V
1
0
−1
VBAT = 5.5 V
−2
2.7 V
−3
−4
−5
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 16. Switching Frequency vs.
Temperature
Figure 17. External Synchronization,
Fsync = 2.93 MHz
2.5
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
2.41
2.4
2.39
2.38
2.37
2.36
2.35
−50
Figure 19. Current Peak Inductor Protection
VIN = 3.6 V, VOUT1 = 1.2 V, IOUT1 Short to GND,
EN2 = GND
1.2
1.1
UVLOrise
ENABLE THRESHOLD (V)
UVLO THRESHOLD (V)
Figure 18. Soft−Start Typical Behavior
VIN = 3.6 V, VOUT1 = VOUT2 = 1.2 V,
IOUT1 = IOUT2 = 600 mA
UVLOfall
−25
0
25
50
75
TEMPERATURE (°C)
100
125
1.0
0.9
0.8
VIH
0.7
VIL
0.6
0.5
0.4
−50
Figure 20. UVLO Thresholds VIN = 3.6 V,
IOUT1 = IOUT2 = 2 mA
−25
0
25
50
75
TEMPERATURE (°C)
100
Figure 21. Enable Thresholds VIN = 3.6 V,
IOUT1 = IOUT2 = 2 mA
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10
125
NCP1532
DC/DC OPERATION DESCRIPTION
Detailed Description
PWM comparator resets the flip−flop, Q1 is turned OFF
while the synchronous switch Q2 is turned ON. Q2 replaces
the external Schottky diode to reduce the conduction loss
and improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
completely turned OFF before Q2 is being turned ON.
The NCP1532 uses a constant frequency, current mode
step−down architecture. Both the main (P−channel
MOSFET) and synchronous (N−channel MOSFET)
switches are internal.
The output voltages are set by the external resistor divider
in the range of 0.9 V to 3.3 V and can source 1600 mA
totally depending on device option.
The NCP1532 works with two modes of operation;
PWM/PFM depending on the current required. In PWM
mode, the device can supply voltage with a tolerance of
$3% and 90% efficiency or better. Lighter load currents
cause the device to automatically switch into PFM mode to
reduce current consumption (Iq = 50 mA) and extended
battery life. For low noise applications, by pulling the
MODE/SYNC Pin to VIN, the device operates in PWM
mode only.
Additional features include soft−start, undervoltage
protection, current overload protection and thermal
shutdown protection. As shown on Figure 1, only six
external components are required for implementation. The
part uses an internal reference voltage of 0.6 V. It is
recommended to keep NCP1532 in shutdown until the input
voltage is 2.7 V or higher. To reduce power demand on the
battery, the two DC−DC operates out of phase. This reduces
significantly spikes on Vin line. Using external
synchronization, the two channels are working on same
signal phase. See MODE/SYNC section for more
information.
Figure 22. PWM Switching Waveforms
VIN = 3.6 V, VOUT1 = VOUT2 = 1.2 V,
IOUT1 = IOUT2 = 100 mA
PFM Operating Mode
Under light load conditions, the NCP1532 enters in low
current PFM mode of operation to reduce power
consumption. The output regulation is implemented by
pulse frequency modulation. If the output voltage drops
below the threshold of PFM comparator a new cycle will be
initiated by the PFM comparator to turn on the switch Q1.
Q1 remains ON during the minimum on time of the structure
while Q2 is in its current source mode. The peak inductor
current depends upon the drop between input and output
voltage. After a short dead time delay where Q1 is switched
OFF, Q2 is turned in its ON state. The negative current
detector will detect when the inductor current drops below
zero and sends the signal to turn Q2 in current source mode
to prevent a too large deregulation of the output voltage.
When the output voltage falls below the threshold of the
PFM comparator, a new cycle starts immediately.
PWM Operating Mode
In this mode, the output voltage of the device is regulated
by modulating the on−time pulse width of the main switch
Q1 at a fixed 2.25 MHz frequency.
The switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor
(Q1) and switches the lower side transistor in either ON state
or in current source mode.
At the beginning of each cycle, the main switch Q1 is
turned ON by the rising edge of the internal oscillator clock.
The inductor current ramps up until the sum of the current
sense signal and compensation ramp becomes higher than
the error amplifier’s voltage. Once this has occurred, the
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NCP1532
Power On Reset
The Power On Reset (POR) is pulled low when either
active converter is out of 89% of their regulation. When
active outputs are in the range of regulation, a counter starts
to provide the POR signal with a delay equal to 262,144
clock cycles. The delay is depending on internal clock
frequency. If only one channel is active, POR runs only on
the active output until the other converter is disabled. When
this regulator becomes enabled, POR drops down until the
second output reaches its voltage range. A pullup resistor
(around 500 k) is needed to this open drain output. This
resistor may be connected to VIN or to an output voltage of
one regulator if the device supplied cannot accept VIN on the
IO. In the case of POR being tied to VIN, POR is high when
NCP1532 is off. In the case of POR being tied to VOUT, POR
is low when NCP1532 is off.
Figure 23. PFM Switching Waveforms
VIN = 3.6 V, VOUT1 = VOUT2 = 1.2 V,
IOUT1 = IOUT2 = 0 mA
Soft−Start
The NCP1532 uses soft−start to limit the inrush current
when the device is initially powered up or enabled.
Soft−start is implemented by gradually increasing the
reference voltage until it reaches the full reference voltage.
During startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference voltage
will switch to the regular reference voltage.
Figure 24. POR Behavior vs. VOUT1
Cycle−by−Cycle Current Limitation
From the block diagram (Figure 2), an ILIM comparator is
used to realize cycle−by−cycle current limit protection. The
comparator compares the SW pin voltage with the reference
voltage, which is biased by a constant current. If the inductor
current reaches the limit, the ILIM comparator detects the
SW voltage falling below the reference voltage and releases
the signal to turn off the switch Q1. The cycle−by−cycle
current limit is set at 1600 mA (nom).
Leave the POR pin unconnected when not used.
Mode Selection and Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which
provides mode selection and frequency synchronization.
When this pin is connected to ground, auto−switching
PFM/PWM mode is selected which provides the best
efficiency at light load and quiescent current with a good
ripple compromise (less than 8 mV). Connecting this pin to
VIN enables PWM mode of operation, which provides the
best low noise solution, low ripple and low load transient
performance.
NCP1532 can also be synchronized to an external clock
signal in the range from internal switching frequency to
3.0 MHz. Lower frequency causes the part enters one time
in PFM/PWM mode, and the other time in PWM mode.
Insert the clock before enabling the part is recommended to
force external synchronization. This function allows
synchronizing NCP1532 with another switching device
such as the switching output of another DC to DC converter
forced in PWM mode. This decreases noise dispersion
generated by the converters.
Low Dropout Operation
The NCP1532 offers a low input to output voltage
difference. The NCP1532 can operate at 100% duty cycle on
both channels.
In this mode the PMOS (Q1) remains completely ON. The
minimum input voltage to maintain regulation can be
calculated as:
V IN(min) + V OUT(max) ) (I OUT
(R DS(on)_R INDUCTOR)
(eq. 1)
•
•
•
•
VOUT: Output Voltage (V)
IOUT: Maximum Output Current
RDS(on): P−Channel Switch RDS(on)
RINDUCTOR: Inductor Resistance (DCR)
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12
NCP1532
Undervoltage Lockout
Thermal Shutdown
The Input voltage VIN must reach 2.4 V (typ) before the
NCP1532 enables the DC/DC converter output to begin the
start up sequence (see soft−start section). The UVLO
threshold hysteresis is typically 100 mV.
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction Temperature is exceeded. If the junction
temperature exceeds 180°C, the device shuts down. In this
mode all power transistors and control circuits are turned
off. The device restarts in soft start after the temperature
drops below 140°C. This feature is provided to prevent
catastrophic failures from accidental device overheating.
Shutdown Mode
When the EN pin has applied voltage of less than 0.4 V,
the NCP1532 will be disabled. In shutdown mode, the
internal reference, oscillator and most of the control
circuitries are turned off. Therefore, the typical current
consumption will be 0.3 mA (typical value). Applying a
voltage above 1.2 V to EN pin will enable the DC/DC
converter for normal operation. The device will go through
soft−start to normal operation.
Short Circuit Protection
When one output is shorted to ground, the device limits
the inductor current. The duty−cycle is minimum and the
consumption on the input line is 300 mA (typ). When the
short circuit condition is removed, the device returns to the
normal mode of operation.
APPLICATION INFORMATION
Output Voltage Selection
Table 1. LIST OF INPUT CAPACITOR
The output voltage is programmed through an external
resistor divider connected from VOUT to FB then to GND.
For low power consumption and noise immunity, the
resistor from FB to GND (R2) should be in the [100 kW
600 k] range. If R2 is 200 k given the VFB is 0.6 V, the
current through the divider will be 3.0 mA.
The formula below gives the value of VOUT, given the
desired R1 and the R2 value:
V OUT + V FB
•
•
•
•
ǒ1 ) R1 Ǔ
R2
Murata
Taiyo Yuden
TDK
GRM21BR61A106
10 mF
JMK212BJ106
10 mF
C2012X5R1A106
10 mF
Output L−C Filter Design Considerations
The NCP1532 is built in 2.25 MHz frequency and uses
current mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
Due to the nature of the buck converter, the output L−C
filter must be selected to work with internal compensation.
For NCP1532, the internal compensation is internally fixed
and it is optimized for an output filter of L = 2.2 mH and
COUT = 10 mF.
The corner frequency is given by:
(eq. 2)
VOUT: Output Voltage (V)
VFB: Feedback Voltage = 0.6 V
R1: Feedback Resistor from VOUT to FB
R2: Feedback Resistor from FB to GND
Input Capacitor Selection
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is IO, max/2.
For NCP1532, a low profile ceramic capacitor of 10 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to the VIN Pin. Capacitors with 10 V rated voltage
are recommended to avoid DC bias effect over input voltage
range.
f+
1
2p ǸL
C OUT
+
1
2p Ǹ2.2 mH
10mF
+ 34 kHz
(eq. 3)
The device operates with inductance value of 2.2 mH. If
the corner frequency is moved, it is recommended to check
the loop stability depending of the accepted output ripple
voltage and the required output current. Take care to check
the loop stability. The phase margin is usually higher than
45°.
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13
NCP1532
Output Capacitor Selection
Table 2. Table 2: L−C FILTER EXAMPLE
Inductance (L)
Output Capacitor (COUT)
1.0 mH
22 mF
2.2 mH
10 mF
4.7 mH
4.7 mF
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric. We recommend to place a
capacitor with rated voltage much higher than the output
voltage selected by the external divider. Capacitors with
10 V rated voltages are recommended from 2.0 V to 3.3 V
output voltages.
The output ripple voltage in PWM mode is given by:
Inductor Selection
The inductor parameters directly related to device
performances are saturation current and DC resistance and
inductance value. The inductor ripple current (DIL)
decreases with higher inductance:
DI L +
V OUT
L
f SW
ǒ
1*
Ǔ
V OUT
V IN
DV OUT + DI L
(eq. 4)
Murata
The saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
DI L
2
Taiyo Yuden
TDK
(eq. 5)
• IL(max): Maximum Inductor Current
• IO(max): Maximum Output Current
TDK
VLF3010AT series
TFC252005 series
Taiyo Yuden
Coil craft
f SW
C OUT
Ǔ
) ESR (eq. 6)
GRM219R61A475
4.7 mF
GRM21BR61A106
10 mF
JMK212BY475MG
4.7 mF
JMK212BJ106MG
10 mF
C2012X5R1A475
4.7 mF
C2012X5R1A106
10 mF
The feed−forward capacitor sets the feedback loop
response and is critical to obtain good loop stability. Given
that the compensation is internally fixed, an 18 pF or higher
ceramic capacitor is needed. Choose a small ceramic
capacitor X7R or X5R or COG dielectric.
Table 3. LIST OF INDUCTOR
MIPW3226 series
4
Feed−Forward Capacitor Selection
The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3 W for good efficiency.
FDK
1
Table 4. LIST OF OUTPUT CAPACITOR
• DIL: Peak−to−Peak Inductor Ripple Current
• L: Inductor Value
• fSW: Switching Frequency
I L(max) + I O(max) )
ǒ
LQ CBL2012
DO1605 Series
LPS4018 series
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NCP1532
LAYOUT CONSIDERATIONS
Electrical Layout Considerations
capacitor is recommended to meet compensation
requirements. A four layer PCB with a ground plane
and a power plane will help NCP1532 noise immunity
and loop stability.
Implementing a high frequency DC−DC converter
requires respect of some rules to get a powerful portable
application. Good layout is key to prevent switching
regulators to generate noise to application and to
themselves.
Electrical layout guide lines are:
• Use short and large traces when large amount of current
is flowing.
• Keep the same ground reference for input and output
capacitors to minimize the loop formed by high current
path from the battery to the ground plane.
• Isolate feedback pin from the switching pin and the
current loop to protect against any external parasitic
signal coupling. Add a feed−forward capacitor between
VOUT and FB which adds a zero to the loop and
participates to the good loop stability. A 18 pF
SW1
trace
Thermal Layout Considerations
High power dissipation in small package leads to thermal
consideration such as:
• Enlarge the VIN trace and add several vias that are
connected to power plane.
• Connect the GND pin to the top plane.
• Join top, bottom and each ground plane together using
several free vias in order to increase dissipation
capability.
For high ambient temperature and high power dissipation
requirements, refer to notes 7, 8, and 9 to prevent any
thermal issue.
FB1
trace
Vout1
trace
En1
trace
Vin trace
PGND
POR
trace
En2
trace
MODE
/SYNC
trace
SW2
trace
Vout2
trace
Figure 25.
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15
FB2
trace
GND
plane
NCP1532
PACKAGE DIMENSIONS
UDFN10 3x3, 0.5P
CASE 506AT
ISSUE A
D
PIN ONE
REFERENCE
0.15 C
2X
2X
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
ÍÍÍ
ÍÍÍ
ÍÍÍ
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
A3
0.10 C
A
10X
0.08 C
MIN
0.45
0.00
0.18
2.40
1.70
0.30
MILLIMETERS
NOM
MAX
0.50
0.55
0.03
0.05
0.127 REF
0.25
0.30
3.00 BSC
2.50
2.60
3.00 BSC
1.80
1.90
0.50 BSC
0.19 TYP
0.40
0.50
SOLDERING FOOTPRINT*
A1
C
2.6016
SEATING
PLANE
D2
10X
L
1
e
5
8X
2.1746
1.8508
3.3048
E2
10X
10X
K
10
0.5651
6
b
10X
10X
0.3008
0.10 C A
0.05 C
B
0.5000 PITCH
DIMENSIONS: MILLIMETERS
NOTE 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1532/D